CN212135427U

CN212135427U - Time delay-based reconfigurable PUF circuit

Info

Publication number: CN212135427U
Application number: CN202021215844.5U
Authority: CN
Inventors: 唐明; 刘树波; 乔彦淇
Original assignee: Wuhan University WHU
Current assignee: Wuhan University WHU
Priority date: 2020-06-28
Filing date: 2020-06-28
Publication date: 2020-12-11
Anticipated expiration: 2030-06-28

Abstract

The utility model discloses a but PUF circuit of reassortment based on time delay, wherein: the PUF time delay module comprises a 4-bit register reg0, n serial time delay units and a 1-bit register reg 1; the PUF measuring module comprises a 1-bit register reg2, a result comparator and a D trigger; the input signal of the register reg0 is PUF input excitation, the output end of the register reg0 is connected with the input ends of n series-connected delay units, two output ends of the series-connected delay units are respectively connected with the input ends of the register reg1 and the register reg2, one path of output signal of the register reg1 is used as the output signal of the PUF delay module, the other path of output signal of the register reg1 and the output signal of the register reg2 are respectively connected with two input ends of the result comparator, the output end of the result comparator is connected with the input end of the D trigger, and the output signal of the D trigger is the output signal of the reconfigurable PUF circuit. The utility model has the characteristics of simple easy realization, higher stability and randomness, hardware resource consumption are few and the excitation response is to a large amount etc.

Description

Time delay-based reconfigurable PUF circuit

Technical Field

The utility model relates to an information security field especially relates to a but PUF circuit of reassortment based on time delay.

Background

With the development of the internet of things and embedded technology, more and more hardware equipment security problems are paid extensive attention by researchers. Common hardware devices are formed by integrated circuits and are vulnerable to security threats such as intrusion, counterfeiting, copying and the like. Physical Unclonable Functions (PUFs) were proposed in the early 2000 s, which utilized the physical properties of silicon materials and the variability of IC appearance during production as a unique identifier for each chip. Because of the differences of the IC in the production process, the PUF not only ensures the uniqueness of the chip, but also prevents the chip from being cloned effectively. With this feature, the PUF provides a secure, robust, low-cost mechanism to authenticate the chip. Since the PUF does not need to store a secret key in the non-volatile memory, it can be applied in cryptographic algorithms, effectively protecting against physical hacking type attacks. At the same time, the PUF itself has good randomness, which can be used as a random source for a true random number generator. The application scene comprises the following steps: mobile devices, resource constrained devices, RFID tags, etc. These application scenarios need to satisfy both the security requirement and the low cost requirement, so that the PUF is suitable for the above scenarios. From the point of view of the PUF concept, it has been proposed to divide it into two classes, non-electronic PUFs and electronic PUFs.

In recent years, intellectual property protection of FPGA hardware designs has become a requirement of many IP vendors. With the development of embedded systems and internet of things technologies, the realization of PUFs on digital PUFs is receiving more and more attention, and the security problem in FPGAs is receiving more and more attention. Related applications on the FPGA need encryption and authentication functions for safety reasons, and as the realization of the PUF on the FPGA does not additionally increase a large amount of resource overhead, the realization of the PUF on the FPGA receives great attention of people. Digital circuit PUFs can be divided into storage-based PUFs and delay-based PUFs, depending on the implementation principle.

The storage-based PUF is mainly composed of three representative types, namely SRAM PUF, flip-flop PUF, and butterfly PUF. Typical delay-based PUF types have three types: an arbiter PUF, a ring oscillator based PUF, and a glitch PUF.

The digital circuit-based PUFs mainly include SRAM PUFs, trigger PUFs, butterfly PUFs, arbiter PUFs, RO PUFs and burr PUFs, but various systems have various defects when being implemented on FPGAs. For example, SRAM PUFs and flip-flop PUFs cannot produce new random state outputs in a device that is continuously powered on; the butterfly PUF has symmetry requirements on a circuit structure; the arbiter PUF also has a high requirement on the symmetry of the two paths; the RO-based PUF has high requirements on layout and wiring on the FPGA, and the design complexity is increased.

There are minimum units of PUF generation in circuit designs of arbiter PUFs, RO PUFs, and glitch PUFs (each piece of PUF combination circuit produces a one-bit response), and existing delay-based PUFs rarely use the delay of a path in a circuit directly, but rather use a method of generating a 1-bit response using an n-bit input vector as a stimulus to represent the relative path delay between two identical layout paths. For example, Nguyen and the like use two exclusive-or arbiters PUF as one PUF cell to generate a single-bit response, which consumes more hardware resources, and can generate fewer PUF responses under the same resource limit. The existing PUF design based on time delay does not directly use path time delay, but has certain limitation on a mode of generating response by utilizing stimulus, certain PUF cells with poor diversity in a PUF circuit cannot be effectively reflected from the response, and the flexibility is lacked, so that the uniqueness of the PUF is reduced.

In summary, there are two main problems with the current delay-based PUFs. Firstly, the existing PUF design based on time delay generates response under an excitation response structure, and more resources are consumed; secondly, the PUF design based on time delay does not utilize specific path time delay, and certain PUF cells with poor uniqueness cannot be abandoned due to unknown time delay, so that the uniqueness of the PUF is reduced.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model lies in providing a but PUF circuit of reassortment based on time delay to the defect among the prior art.

The utility model provides a technical scheme that its technical problem adopted is:

the utility model provides a time delay-based reconfigurable PUF circuit, which comprises a PUF time delay module, a PUF measuring module and a configurable signal module; wherein:

the PUF time delay module comprises a 4-bit register reg0, n serial time delay units and a 1-bit register reg1 which are sequentially connected; the PUF measuring module comprises a 1-bit register reg2, a result comparator and a D trigger which are connected in sequence; the configurable signal module is connected with each time delay unit; an input signal of a 4-bit register reg0 in the PUF time delay module is PUF input excitation, an output end of a register reg0 is connected with input ends of n serial time delay units, two output ends of the serial time delay units are respectively connected with input ends of a register reg1 and a register reg2, one path of output signal of the register reg1 is used as an output signal of the PUF time delay module, the other path of output signal of the register reg1 and an output signal of a register reg2 are respectively connected with two input ends of a result comparator, an output end of the result comparator is connected with an input end of a D trigger, and an output signal of the D trigger is an output signal of a reconfigurable PUF circuit.

Further, the utility model discloses an every time delay unit includes 2 LUTs of 4 inputs and a MUX of 1 of 2 selection, and two output of 2 LUTs of 4 inputs are connected with two input data terminal of MUX respectively, can dispose the intercommunication condition that the reassortment signal of signal module output decides two LUTs as the select terminal input of MUX, and the output of MUX is single time delay unit's output signal.

Further, in the first delay unit of the present invention, 4 input terminals of the 4-input LUT are connected to 4 output terminals of the 4-bit register reg0, and the connection modes of the two 4-input LUTs are the same.

Further, the utility model discloses a delay unit quantity n among the PUF delay module decides according to the path time delay of the logic circuit that LUT constitutes among the delay unit.

Further, the utility model discloses a quantity n value of time delay unit is more than or equal to 2.

Further, the result comparator of the present invention is an exclusive or gate with 2 inputs and 1 output.

The utility model discloses the beneficial effect who produces is: the utility model discloses a but reassortment PUF circuit based on time delay: 1. the MUX of each time delay unit is configured through a configurable signal module, so that the serial time delay units can obtain combined circuit paths with different layouts, more excitation response pairs are obtained, and meanwhile, a PUF time delay path with higher PUF stability can be selected according to a configuration signal; 2. the structure is flexible, the realization is simple, the stability and the uniqueness are good, and less hardware resources can be consumed under the condition of generating the same number of excitation response pairs.

Drawings

The invention will be further explained with reference to the drawings and examples, wherein:

fig. 1 is an overall PUF construction diagram of an embodiment of the present invention;

fig. 2 is a circuit diagram of the PUF time delay module according to the embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.

As shown in fig. 1, the time delay-based reconfigurable PUF circuit according to the embodiment of the present invention includes a PUF time delay module, a PUF measurement module, and a configurable signal module; wherein:

Each delay unit comprises two 4-input LUTs (Look-Up-tables) and 1 MUX (data selector), wherein the output ends of the two LUTs are respectively connected to the two input ends of the MUX, and the path of the delay unit is selected by a signal of the configurable signal module. The difference between the two 4-input LUTs is their different layouts on the FPGA, even though their structures are the same, the wiring is the same.

As shown in fig. 2, the delay unit includes two LUTs, both of which are 4-input and gates, and a MUX. The 2 series delay units comprise an AND gate 1, an AND gate 2, an AND gate 3, an AND gate 4, a MUX1 and a MUX 2. The input ends of the AND gate 1 and the AND gate 2 are respectively connected with the output end of the register reg0, the output ends of the AND gate 1 and the AND gate 2 are arbitrarily connected with two input ends of a MUX1, the input ends of the AND gate 3 and the AND gate 4 are connected with the output end of the MUX1, the output ends of the AND gate 3 and the AND gate 4 are arbitrarily connected with two input ends of a MUX2, and the output end of the MUX2 is connected with the input end of the reg 1.

The result comparator comprises an exclusive or gate having its input connected to the outputs of registers reg1 and reg2, and its output connected to the input of the D flip-flop.

In order to make the technical solution of the present invention clearer, the following description is made of a specific embodiment of the present invention.

The excitation signal is an input signal of the PUF circuit and is fed to an input terminal of a register reg0, the registers reg0 and reg1 are controlled by a clock signal clk0, and the register reg2 is controlled by another clock signal clk 1. The signals are sent to a time delay unit connected in series, the signals are output by the time delay unit and divided into two data signals which are respectively sent to the input ends of a register reg1 and a register reg2, because a path time delay relation exists in a combination circuit, the values of the register reg1 and the register reg2 may not be equal, the two signals are judged whether to be consistent through a result comparator, if the data of the register reg1 and the register reg2 are the same, 0 is finally output, otherwise, 1 is output and serves as the final result of the final PUF circuit. In addition, the control signal of the configurable signal module is used as the input signal of the selection ends of the MUX1 and the MUX2 to determine the connection mode of the time delay unit and the gate.

It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are considered to be within the scope of the invention as defined by the following claims.

Claims

1. A delay-based reconfigurable PUF circuit, comprising a PUF delay module, a PUF measurement module, and a configurable signal module; wherein:

2. The delay-based reconfigurable PUF circuit according to claim 1, wherein each delay cell comprises 2 LUTs with 4 inputs and a 1-out-of-2 MUX, two output terminals of the 2 LUTs with 4 inputs are respectively connected to two input data terminals of the MUX, the reconfigurable signal output by the configurable signal module is used as the input terminal of the MUX to determine the connection condition of the two LUTs, and the output terminal of the MUX is the output signal of a single delay cell.

3. The delay-based reconfigurable PUF circuit according to claim 2, wherein in the first delay cell, the 4 inputs of the 4-input LUT are connected to the 4 outputs of the 4-bit register reg0, respectively, and the two 4-input LUTs are connected in the same manner.

4. The delay-based reconfigurable PUF circuit according to claim 2, wherein the number n of delay cells in the PUF delay module is determined according to the path delay of the logic circuit composed of LUTs in the delay cells.

5. The delay-based reconfigurable PUF circuit according to claim 4, wherein the number n of delay cells is greater than or equal to 2.

6. The delay-based reconfigurable PUF circuit of claim 1, wherein the result comparator is a 2-input-1-output exclusive or gate.