CN115905087A

CN115905087A - Data processing method and device, electronic equipment and storage medium

Info

Publication number: CN115905087A
Application number: CN202211654190.XA
Authority: CN
Inventors: 赵魁
Original assignee: Lenovo Beijing Information Technology Ltd
Current assignee: Lenovo Beijing Information Technology Ltd
Priority date: 2022-12-22
Filing date: 2022-12-22
Publication date: 2023-04-04

Abstract

The present disclosure provides a data processing method, an apparatus, an electronic device, and a storage medium, wherein the method includes: a master controller included in the mainboard sends a switching instruction to a switching controller included in a Complex Programmable Logic Device (CPLD) on the backboard, so that the switching controller establishes connection between a general backboard management integrated circuit bus and a system integrated circuit bus; the master controller sends an identifier of a universal backboard management integrated circuit bus to be monitored to the CPLD, so that a first integrated circuit bus selector included in the CPLD transmits data on the universal backboard management integrated circuit bus corresponding to the identifier to the system integrated circuit bus; the mainboard receives data transmitted on a system integrated circuit bus based on a second integrated circuit bus selector included by the mainboard controller and sends the data to a resolver included by the mainboard controller; and a log module included in the mainboard controller receives analysis data corresponding to the data transmitted on the system integrated circuit bus and sent by the analyzer.

Description

Data processing method and device, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a data processing method and apparatus, an electronic device, and a storage medium.

Background

In a server application scenario, a disk array card (RAID) is a common PCIE device that tells a serial computer expansion bus (pci Express), and is used to combine a plurality of hard disks into an array group for storage expansion and data backup. With the development of the technology, a Universal Backplane Management (UBM) protocol is commonly used by the disk array card to perform information interaction with a controller (such as a CPLD chip) on the Backplane so as to obtain an in-place state of the hard disk, a disk order index of the hard disk, and perform operations such as resetting and lighting on the hard disk.

Compared with the previously used Serial GPIO Bus (SGPIO) protocol, the complexity of the newly adopted UBM protocol is greatly increased. It adds the handshake mechanism between the main and standby devices and expands a large number of communication instructions. When the SGPIO protocol is used, even if the communication between the disk array card and the back plate controller fails, only the disk sequence and the spot light control of the hard disk are influenced, but the SGPIO protocol can still be normally used under a system; however, after using the UBM protocol, once the two-party communication fails, the system can not identify the hard disk at all. Therefore, it becomes important to ensure normal communication between upstream and downstream through UBM and to effectively capture and analyze data anomalies.

Disclosure of Invention

The present disclosure provides a data processing method, an apparatus, an electronic device, and a storage medium, to at least solve the above technical problems in the prior art.

According to a first aspect of the present disclosure, there is provided a data processing method comprising:

a master controller included in a mainboard sends a switching instruction to a switching controller included in a Complex Programmable Logic Device (CPLD) on a backboard so that the switching controller establishes connection between a general backboard management integrated circuit bus and a system integrated circuit bus;

the master controller sends an identifier of a universal backboard management integrated circuit bus to be monitored to the CPLD, so that a first integrated circuit bus selector included in the CPLD transmits data on the universal backboard management integrated circuit bus corresponding to the identifier to the system integrated circuit bus;

the mainboard receives data transmitted on the system integrated circuit bus based on a second integrated circuit bus selector included by the mainboard controller and sends the data to a resolver included by the mainboard controller;

and a log module included in the mainboard controller receives analysis data corresponding to the data transmitted on the system integrated circuit bus and sent by the analyzer.

According to a second aspect of the present disclosure, there is provided a motherboard comprising a motherboard controller, the motherboard controller comprising a second integrated circuit bus selector, a parser, a log module, and an integrated circuit bus bypass;

the second integrated circuit bus selector is used for establishing the connection between a system integrated circuit bus and a master controller integrated circuit bus or the connection between the system integrated circuit bus and a resolver based on the instruction of the master controller included in the mainboard;

the analyzer is used for analyzing the data transmitted by the system integrated circuit bus;

the log module is used for receiving and outputting the data which is analyzed by the analyzer and transmitted by the system integrated circuit bus;

and the basic circuit bus bypass is used for controlling the connection or disconnection between the system integrated circuit bus and the master integrated circuit bus based on the instruction of the master controller included by the mainboard.

According to a third aspect of the present disclosure, there is provided a back plate comprising: the complex programmable logic device CPLD comprises a switching controller and a first integrated circuit bus selector;

the switching controller is used for controlling a gating path of the first integrated circuit bus selector; establishing connection between a universal backboard management integrated circuit bus and a system integrated circuit bus based on a switching instruction sent by a main controller; detecting basic circuit bus signals on two sides of a first integrated circuit bus selector;

the first integrated circuit bus selector is used for establishing connection between any universal backboard management integrated circuit bus and the system integrated circuit bus based on the switching controller.

According to a fourth aspect of the present disclosure, there is provided a data processing apparatus, the apparatus comprising:

the system comprises a first sending unit, a second sending unit and a control unit, wherein the first sending unit is used for sending a switching instruction to a switching controller included in a Complex Programmable Logic Device (CPLD) on a backboard based on a main controller on a mainboard so that the switching controller establishes connection between a general backboard management integrated circuit bus and a system integrated circuit bus;

the second sending unit is used for sending the identifier of the universal backboard management integrated circuit bus to be monitored to the CPLD based on the master controller so that the first integrated circuit bus selector included in the CPLD transmits the data on the universal backboard management integrated circuit bus corresponding to the identifier to the system integrated circuit bus;

the receiving unit is used for receiving data transmitted on the system integrated circuit bus based on a second integrated circuit bus selector included in the mainboard controller and sending the data to a parser included in the mainboard controller;

and the log processing unit is used for receiving analysis data corresponding to the data transmitted on the system integrated circuit bus and sent by the analyzer based on a log module included in the mainboard controller.

According to a fifth aspect of the present disclosure, there is provided an electronic device comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods of the present disclosure.

According to a sixth aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of the present disclosure.

The data processing method of the present disclosure sends a switching instruction to a switching controller included in a CPLD on a backplane through a master controller included in a motherboard, so that the switching controller establishes a connection between a general backplane management integrated circuit bus and a system integrated circuit bus; the master controller sends an identifier of a universal backboard management integrated circuit bus to be monitored to the CPLD, so that a first integrated circuit bus selector included in the CPLD transmits data on the universal backboard management integrated circuit bus corresponding to the identifier to the system integrated circuit bus; the mainboard receives data transmitted on the system integrated circuit bus based on a second integrated circuit bus selector included by the mainboard controller and sends the data to a resolver included by the mainboard controller; and a log module included in the mainboard controller receives analysis data corresponding to the data transmitted on the system integrated circuit bus and sent by the analyzer. Therefore, data abnormity can be captured and analyzed, maintenance and debugging are carried out in time, and normal operation of the system is guaranteed.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:

in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

FIG. 1 is a schematic diagram illustrating a disk array card information interaction in the related art;

FIG. 2 is a schematic diagram illustrating a system design circuit provided by an embodiment of the present disclosure;

FIG. 3 illustrates an alternative schematic diagram of a system design circuit provided by an embodiment of the present disclosure;

FIG. 4 is a schematic flow chart diagram illustrating an alternative data processing method provided by the embodiment of the present disclosure;

FIG. 5 illustrates an alternative schematic diagram of a system design circuit provided by embodiments of the present disclosure;

FIG. 6 is a schematic flow chart diagram illustrating an alternative data processing method provided by the embodiment of the present disclosure;

FIG. 7 is a schematic diagram illustrating an alternative structure of a data processing apparatus according to an embodiment of the present disclosure;

fig. 8 shows a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, features and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

In a server application scenario, a raid card is a common PCIE device, and is used to form an array group from multiple hard disks for storage expansion and data backup. With the development of technology, a disk array card generally adopts a general backplane management protocol to perform information interaction with a controller (such as a CPLD chip) on a backplane so as to obtain an in-place state of a hard disk, a disk order index of the hard disk, and perform operations such as resetting and lighting on the hard disk.

Fig. 1 is a schematic diagram illustrating information interaction between disk array cards in the related art.

As shown in fig. 1, the newly adopted UBM protocol is much more complex than the previously used serial interface bus protocol. It adds the handshake mechanism between the main and standby devices and expands a large amount of communication instructions. When the SGPIO protocol is used, even if the communication between the disk array card and the back plate controller fails, only the disk sequence and the spot light control of the hard disk are influenced, but the SGPIO protocol can still be normally used under a system; however, after using the UBM protocol, once the two-party communication fails, the system cannot identify the hard disk at all. Therefore, it becomes important to ensure normal communication between upstream and downstream through UBM and to effectively capture and analyze data anomalies.

The main communication link of the UBM protocol is a "two-wire transmission format", i.e., an IIC communication protocol, an Integrated Circuit bus (IIC, I2C) protocol. When data analysis is performed, the IIC instruction needs to be analyzed so as to analyze and judge the behaviors of the master and slave devices. Since we cannot add debugging information on the master device (i.e. the disk array card), we can only consider adding the corresponding debugging module on the autonomously developed slave device (i.e. the controller on the backplane). However, when the backplane is designed, due to the requirements of physical space and cost, the logic resources of the used controller are often very limited, so that the protocol printing module cannot be added, and a debugging tool (such as a serial port and the like) cannot be conveniently connected. Therefore, at present, the UBM signal on the backplane can only be directly measured by the oscilloscope, and the IIC instruction can be analyzed by the logic analyzer. This operation not only requires flying wires on the backplane to match the use of the logic analyzer, but also fails to achieve trouble shooting of communication logs anywhere.

In view of the problems in the foregoing solutions, the present disclosure provides a data processing method, which can solve some or all of the above technical problems.

Fig. 2 shows a schematic diagram of a system design circuit provided by an embodiment of the present disclosure.

In the design of the main board, there is often enough space for placing debugging interfaces (such as serial ports). Therefore, the UBM signal is looped to the mainboard, and is analyzed by the processing chip on the mainboard and output through the debugging interface, so that the UBM signal loop is an ideal solution. In the current general design, the communication interface between the backplane and the motherboard is usually only one group of System I2C, and the communication interface is connected to the motherboard BMC as the backplane management function. Fig. 2 shows that looping signals of the UBM link to the System I2C link to resolve the I2C command on the motherboard is a feasible solution. The present disclosure further refines fig. 2.

Fig. 3 shows an alternative schematic diagram of a system design circuit provided by the embodiment of the disclosure.

In some embodiments, as shown in fig. 3, the motherboard may be a mothers Board on which a Central Processing Unit (CPU), RAID, baseboard control manager or master (BMC), motherboard controller, etc. are integrated; the Backplane may be a Backplane with a CPLD integrated thereon. The mainboard controller can be a BMC or a Field Programmable Gate Array (FPGA).

The bus for data transmission between the mainboard and the backboard is a System integrated circuit bus (System I2C); the bus for data transmission in the backplane is a universal backplane management integrated circuit bus (UBM I2C or UBM (I2C)).

In specific implementation, the motherboard controller is integrated with a second integrated circuit bus selector (I2C MUX on the motherboard controller), an Analyzer (I2C Analyzer), a Log module (UART Log), and an integrated circuit bus Bypass (I2C Bypass on the motherboard controller).

The second integrated circuit bus selector is configured to establish, based on an instruction of the master controller included in the motherboard, a connection between a System integrated circuit bus and a master controller integrated circuit bus (i.e., a System I2C link is looped to the master controller I2C link), or a connection between the System integrated circuit bus and a parser (i.e., the System I2C link is looped to an I2C Analyzer module inside the motherboard controller); the analyzer is used for analyzing the data transmitted by the system integrated circuit bus (i.e. analyzing UBM (I2C) instructions); the log unit is used for receiving and outputting the data which is analyzed by the analyzer and transmitted by the system integrated circuit bus; the basic circuit bus bypass is used for controlling connection or disconnection between a system integrated circuit bus and a main controller integrated circuit bus (namely controlling connection or disconnection between a main controller I2C link and a main board controller I2C Mux) based on an instruction of a main controller included in the main board.

In specific implementation, a switching controller (MUX Control) and a first integrated circuit bus selector (I2C MUX on the CPLD) are integrated on the CPLD.

Wherein the switching controller (MUX Control) is configured to Control a gating path of the first integrated circuit bus selector; establishing connection between a universal backboard management integrated circuit bus and a system integrated circuit bus based on a switching instruction sent by a main controller; detecting basic circuit bus signals on two sides of a first integrated circuit bus selector; the first integrated circuit bus selector is used for establishing connection between any universal backboard management integrated circuit bus and the system integrated circuit bus based on the switching controller.

Fig. 4 shows an alternative flow chart of the data processing method provided by the embodiment of the disclosure.

Step S401, the main controller included in the main board sends a switching instruction to the switching controller included in the complex programmable logic device on the backplane, so that the switching controller establishes a connection between the universal backplane management integrated circuit bus and the system integrated circuit bus.

In some embodiments, as shown in fig. 3, the master on the motherboard (BMC) sends a switch instruction to a switch controller (MUX Control) included in the CPLD on the backplane, so that the switch controller (MUX Control) establishes a connection between a universal backplane management integrated circuit bus (UBM I2C) and a System integrated circuit bus (System I2C).

In specific implementation, after power is on, the first integrated circuit bus selector (I2C Mux on the CPLD) is connected with the System integrated circuit bus (System I2C), so that the master controller (BMC) can normally access the registers in the CPLD on the backplane to manage the backplane.

Specifically, the master controller connects the System integrated circuit bus (System I2C) and the master integrated circuit bus (master controller itself I2C) based on the second integrated circuit bus selector (I2 CMUX on the main board); the backboard connects the System integrated circuit bus (System I2C) and a Register link (Register link) based on the I2CMux on the first integrated circuit bus selector (CPLD); at this time, the default I2C path is: BMC I2C- > I2C Bypass- > I2C Mux- > System I2C- > CPLD I2C Mux- > CPLD Register I2C on the mainboard. Such that a switching instruction sent by the master is sent by the master to the switching controller based on the master integrated circuit bus, the system integrated circuit bus, and the registration link.

When the debugging mode needs to be started, the master controller (BMC) issues a switching instruction to the switching controller (MUX Control) through the register in the CPLD on the backboard, and the Mux Control establishes connection between the universal backboard management integrated circuit bus and the system integrated circuit bus.

Step S402, the master controller sends the identifier of the universal backboard management integrated circuit bus to be monitored to the CPLD, so that the first integrated circuit bus selector included in the CPLD transmits the data on the universal backboard management integrated circuit bus corresponding to the identifier to the system integrated circuit bus.

In some embodiments, the master sends the identifier of the generic backplane management integrated circuit bus to the switching controller (MUX Control) based on the master integrated circuit bus (master itself I2C), the System integrated circuit bus (System I2C- > Register link), and the registration link (i.e. BMC I2C- > System I2C- > Register link), so that the switching controller establishes the connection between the generic backplane management integrated circuit bus (UBM I2C) and the System integrated circuit bus (System I2C) corresponding to the identifier, disconnects the connection between the System integrated circuit bus (System I2C) and the registration link (Register link), and detects the basic circuit bus signal of I2CMux on both sides of the first integrated circuit bus selector (cpl).

In specific implementation, the master controller monitors one or more UBM I2C links, and when the debugging mode is started, the master controller needs to identify a backplane management integrated circuit bus (UBM I2C) to be monitored in a register of the CPLD. The identifier of the backplane management integrated circuit bus (UBM I2C) may be a serial number of the backplane management integrated circuit bus (UBM I2C), that is, a serial number capable of distinguishing any UBM I2C from other UBM I2C.

In specific implementation, after receiving the switching instruction, the switching controller (Mux Control) establishes a connection between the universal backplane management integrated circuit bus (UBM I2C) corresponding to the identifier and the System integrated circuit bus (System I2C), disconnects the connection between the System integrated circuit bus (System I2C) and the registration link (Register link), and detects a basic circuit bus signal on both sides of the first integrated circuit bus selector.

Step S403, the motherboard receives data transmitted on the system integrated circuit bus based on a second integrated circuit bus selector included in the motherboard controller, and sends the data to an analyzer included in the motherboard controller.

In some embodiments, the master controller controls an integrated circuit bus Bypass (I2C Bypass) included in the motherboard controller to be turned off to disconnect the connection between the system integrated circuit bus and a master integrated circuit bus (master own I2C), and to establish a connection between the system integrated circuit bus and a parser so that the parser receives data transmitted on the system integrated circuit bus based on the second integrated circuit bus selector.

In specific implementation, the main controller closes the I2C Bypass, so that the connection between the main board controller I2C Mux and the main controller I2C is disconnected. At the same time, the route of the motherboard controller I2C Mux is selected to I2C Analyzer. At this time, the I2C path is: UBM I2C- > CPLD I2C Mux- > System I2C- > I2C Mux- > I2C Analyzer of mainboard controller. After the I2C path is established, the motherboard controller automatically parses all UBM I2C instructions, translates them, and outputs them to the parser through the serial port.

Step S404, a log module included in the motherboard controller receives analysis data corresponding to the data transmitted on the system integrated circuit bus and sent by the analyzer.

In some embodiments, the log module included in the motherboard controller receives parsing data corresponding to data transmitted on the system integrated circuit bus and sent by the parser.

In some embodiments, after completion of the debugging, the master controls an integrated circuit bus bypass (I2 CBypass) to be turned on to establish a connection between the system integrated circuit bus and the master integrated circuit bus; issuing an integrated circuit bus command to a backplane to cause a connection between the system integrated circuit bus and the registration link to be established based on the switch controller in response to the switch controller detecting a signal mismatch on both sides of the first integrated circuit bus selector.

In specific implementation, after the debugging test is completed, when the master controller needs to restore the control on the CPLD register, the master controller opens the I2C Bypass, switches the I2C Mux of the motherboard controller to the I2C link of the master controller, and simultaneously sends out any I2C instruction to the backplane. At this time, on the System I2C link, there are both the signal sent by the master and the UBM I2C signal forwarded by the CPLD I2C Mux, and the two signals overlap (based on the I2C electrical characteristics, if either of the two pulls the signal low, the signal on the link is low, and only if both pulls the signal high, the signal on the link is high).

In step S402, after the modulation mode is turned on, the switching controller (Mux Control) detects the basic circuit bus signals on both sides of the first ic bus selector, and when it is detected that the signal states on both sides of the CPLD I2C Mux are inconsistent, the CPLD I2C Mux does not correctly transmit the UBM I2C state to the System I2C link. Therefore, the Mux Control module determines that the master needs to take over the link again and switches the CPLD I2C Mux back to the BP Register I2C. At this point, the I2C communication path is restored to the default state after power-up.

Therefore, through the data processing method provided by the embodiment of the disclosure, the signal of the UBM link is looped to the System I2C link, and the I2C instruction is analyzed on the mainboard, so that data anomaly can be effectively captured and analyzed, and a communication log can be captured at any time and any place for troubleshooting.

Fig. 5 shows another alternative schematic diagram of a system design circuit provided by the embodiment of the disclosure.

In the system design circuit shown in fig. 3, the function of the motherboard controller may be implemented by a BMC or an FPGA, and the BMC is used as a management chip, which is advantageous in logic processing. And the protocol analysis is carried out on the real-time signal and an instruction log is output, so that a large amount of BMC processing resources are consumed, and the normal service of BMC is possibly influenced. Therefore, with such a demand, an FPGA chip on the motherboard is undoubtedly a better choice.

As a preferred scheme, the FPGA is adopted to be connected to a System I2C link in an abutting mode, the UBM link can be analyzed in real time, and a corresponding I2C instruction is output through a serial port. By utilizing the high-speed processing capability of the FPGA, the testing requirement can be realized, and the influence on other services of the system can be avoided.

In some embodiments, as shown in fig. 5, the motherboard may be a motherboard with a Central Processing Unit (CPU), RAID, baseboard control manager or master (BMC), and FPGA integrated thereon; the Backplane may be a Backplane with a CPLD integrated thereon.

In specific implementation, a second integrated circuit bus selector (I2C MUX on FPGA), a parser (I2C Analyzer), a Log module (UART Log) and an integrated circuit bus Bypass (I2C Bypass on FPGA) are integrated on the FPGA.

The second integrated circuit bus selector is used for establishing connection between a System integrated circuit bus and a master controller integrated circuit bus (namely, connecting a System I2C link to a master controller I2C link) or connection between the System integrated circuit bus and a parser (namely, connecting the System I2C link to an FPGA internal I2C Analyzer module) based on an instruction of a master controller included in the mainboard; the analyzer is used for analyzing the data transmitted by the system integrated circuit bus (i.e. analyzing UBM (I2C) instructions); the log unit is used for receiving and outputting the data which is analyzed by the analyzer and transmitted by the system integrated circuit bus; and the basic circuit bus bypass is used for controlling the connection or disconnection between the system integrated circuit bus and the main controller integrated circuit bus (namely controlling the connection or disconnection between the main controller I2C link and the FPGA I2C Mux) based on the instruction of the main controller included by the mainboard.

Wherein the switch controller (MUX Control) is configured to Control a gating path of the first integrated circuit bus selector; establishing connection between a general backboard management integrated circuit bus and a system integrated circuit bus based on a switching instruction sent by a master controller; detecting basic circuit bus signals on two sides of a first integrated circuit bus selector; after the debugging mode is started, the Reg I2C is disconnected with the System I2C, and the instruction sent by the main controller can not be received any more. Therefore, the Mux Control module cannot know that the master needs to turn off the debugging function and reestablish the connection with the Reg I2C through the register. At this point, the Mux Control module will turn on the auto-detect mechanism. The first integrated circuit bus selector is used for establishing connection between any universal backboard management integrated circuit bus and the system integrated circuit bus based on the switching controller.

Fig. 6 is a schematic flow chart of another alternative data processing method provided by the embodiment of the present disclosure, which will be described with reference to fig. 5.

Step S601, a system power-on process.

In some embodiments, after the system is powered on, a master controller (BMC) on the motherboard gates the FPGA I2C Mux as its own I2C; the backplane CPLD gates the I2C mux to the Register link by default. Thus, the default I2C path is: BMC I2C- > I2C Bypass- > FPGA I2C Mux- > (System I2C) - > CPLD I2C Mux- > CPLD Register I2C.

Step S602, the debug mode is turned on.

In some embodiments, when debug mode is turned on, the master writes enable control to the CPLD registers and selects the sequence number of the UBM I2C link to monitor. Upon receiving the command (switching instruction), the CPLD I2CMux will act as the master of the System I2C link and pass the selected UBM I2C onto the System I2C link. At the same time, mux Control starts the auto-monitoring mechanism.

The main controller closes the I2C Bypass module, so that the connection between the FPGA I2C Mux and the main controller I2C is disconnected. Meanwhile, the FPGA I2C Mux is routed to the I2C Analyzer. After completing steps 2-3, the I2C path is: UBM I2C- > CPLD I2C Mux- > (System I2C) - > FPGA I2C Mux- > I2C Analyzer

After the I2C link is established, the FPGA can automatically analyze all UBM I2C instructions, translate the instructions and output the instructions through a serial port.

Step S603, turn off the debug mode.

In some embodiments, after the debugging test is completed, when the master needs to restore the control on the CPLD register, the master opens the I2C Bypass module, switches the FPGA I2C Mux to the I2C link of the master, and simultaneously issues any I2C instruction to the backplane. At this time, on the System I2C link, there are both the signal sent by the master and the UBM I2C signal forwarded by the CPLD I2C Mux, and the two signals overlap together (based on the I2C electrical characteristics, if either of the two pulls the signal low, the signal on the link is low, and only if both pulls the signal high, the signal on the link is high).

The Mux Control module detects that the signal states on the two sides of the CPLD I2C Mux are inconsistent, and the CPLD I2CMux does not correctly transmit the state of the UBM I2C to the System I2C link. Therefore, the Mux Control module determines that the master needs to take over the link again and switches the CPLD I2C Mux back to the BP Register I2C. At this point, the I2C communication path is restored to the default state after power-up.

Therefore, the System I2C link is connected through the FPGA in an abutting mode, the UBM link can be analyzed in real time, and a corresponding I2C instruction is output through a serial port. By utilizing the high-speed processing capability of the FPGA, the testing requirement can be realized, and the influence on other services of the system can be avoided.

Fig. 7 shows an alternative structural diagram of a data processing apparatus provided in an embodiment of the present disclosure, which will be described according to various parts.

In some embodiments, the data processing apparatus 700 includes a first transmitting unit 701, a second transmitting unit 702, a receiving unit 703, and a log processing unit 704.

The first sending unit 701 is configured to send a switching instruction to a switching controller included in a complex programmable logic device on a backplane based on a master controller on a motherboard, so that the switching controller establishes a connection between a general backplane management integrated circuit bus and a system integrated circuit bus;

the second sending unit 702 is configured to send, to the CPLD, an identifier of a universal backplane management integrated circuit bus to be monitored based on the master controller, so that a first integrated circuit bus selector included in the CPLD transmits data on the universal backplane management integrated circuit bus corresponding to the identifier to the system integrated circuit bus;

the receiving unit 703 is configured to receive, based on a second integrated circuit bus selector included in the motherboard controller, data transmitted on the system integrated circuit bus, and send the data to an analyzer included in the motherboard controller;

the log processing unit 704 is configured to receive, based on a log module included in the motherboard controller, analysis data corresponding to data transmitted on the system integrated circuit bus and sent by the analyzer.

In some embodiments, the data processing apparatus 700 further comprises a power-on unit 705.

The power-on unit 705 is configured to enable the master to connect the system integrated circuit bus to a master integrated circuit bus based on the second integrated circuit bus selector; causing the backplane to connect the system integrated circuit bus with a registration link based on the first integrated circuit bus selector; such that a switching instruction sent by the master is sent by the master to the switching controller based on the master integrated circuit bus, the system integrated circuit bus, and the registration link.

The second sending unit 702 is specifically configured to enable the master controller to send an identifier of the universal backplane management integrated circuit bus to the switching controller based on the master integrated circuit bus, the system integrated circuit bus, and the registration link, so that the switching controller establishes a connection between the universal backplane management integrated circuit bus corresponding to the identifier and the system integrated circuit bus, disconnects the connection between the system integrated circuit bus and the registration link, and detects a basic circuit bus signal on both sides of the first integrated circuit bus selector.

In some embodiments, the data processing apparatus 700 further comprises a debugging unit 706.

The debugging unit 706 is configured to enable the master controller to control an integrated circuit bus bypass included in the motherboard controller to be closed, so as to disconnect the connection between the system integrated circuit bus and the master controller integrated circuit bus, and establish a connection between the system integrated circuit bus and a parser, so that the parser receives data transmitted on the system integrated circuit bus based on the second integrated circuit bus selector.

In some embodiments, the debug unit 706 is further configured to cause the master to control the integrated circuit bus bypass to be opened to establish a connection between the system integrated circuit bus and the master integrated circuit bus;

issuing an integrated circuit bus command to a backplane to cause a connection between the system integrated circuit bus and the registration link to be established based on the switch controller in response to the switch controller detecting a signal mismatch on both sides of the first integrated circuit bus selector.

The present disclosure also provides an electronic device and a readable storage medium according to an embodiment of the present disclosure.

FIG. 8 illustrates a schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not intended to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 8, the electronic device 800 includes a computing unit 801 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 802 or a computer program loaded from a storage unit 808 into a Random Access Memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the electronic apparatus 800 can also be stored. The calculation unit 801, the ROM 802, and the RAM 803 are connected to each other by a bus 804. An input/output (I/O) interface 805 is also connected to bus 804.

A number of components in the electronic device 800 are connected to the I/O interface 805, including: an input unit 806, such as a keyboard, a mouse, or the like; an output unit 807 such as various types of displays, speakers, and the like; a storage unit 808, such as a magnetic disk, optical disk, or the like; and a communication unit 809 such as a network card, modem, wireless communication transceiver, etc. The communication unit 809 allows the electronic device 800 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.

Computing unit 801 may be a variety of general and/or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various dedicated Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, and the like. The calculation unit 801 executes the respective methods and processes described above, such as the data processing method. For example, in some embodiments, the data processing method may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and/or installed onto the electronic device 800 via the ROM 802 and/or the communication unit 809. When loaded into RAM 803 and executed by the computing unit 801, a computer program may perform one or more steps of the data processing method described above. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the data processing method by any other suitable means (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user may provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the Internet.

The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server with a combined blockchain.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present disclosure may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method of data processing, the method comprising:

a main controller included in the mainboard sends a switching instruction to a switching controller included in a Complex Programmable Logic Device (CPLD) on the backboard, so that the switching controller establishes connection between a general backboard management integrated circuit bus and a system integrated circuit bus;

2. The method according to claim 1, before the master comprised by the motherboard sends a switch instruction to the switch controller comprised by the complex programmable logic device CPLD on the backplane, the method further comprising:

the master controller is connected with the system integrated circuit bus and the master integrated circuit bus based on the second integrated circuit bus selector;

the backplane connects the system integrated circuit bus with a registration link based on the first integrated circuit bus selector;

such that a switch instruction sent by the master is sent by the master to the switch controller based on the master integrated circuit bus, the system integrated circuit bus, and the registration link.

3. The method of claim 2, said master sending to the CPLD an identification of the generic backplane management integrated circuit bus to be monitored, comprising:

the master controller sends the identifier of the universal backboard management integrated circuit bus to the switching controller based on the master controller integrated circuit bus, the system integrated circuit bus and the registration link, so that the switching controller establishes the connection between the universal backboard management integrated circuit bus corresponding to the identifier and the system integrated circuit bus, disconnects the connection between the system integrated circuit bus and the registration link, and detects basic circuit bus signals on two sides of the first integrated circuit bus selector.

4. The method of claim 2, further comprising:

the main controller controls an integrated circuit bus bypass included by the main board controller to be closed so as to disconnect the connection between the system integrated circuit bus and the main controller integrated circuit bus and establish the connection between the system integrated circuit bus and a resolver, so that the resolver receives data transmitted on the system integrated circuit bus based on the second integrated circuit bus selector.

5. The method of claim 3, further comprising:

the main controller controls the integrated circuit bus bypass to be opened so as to establish the connection between the system integrated circuit bus and the main controller integrated circuit bus;

6. A motherboard comprising a motherboard controller, the motherboard controller comprising a second integrated circuit bus selector, a parser, a log module, and an integrated circuit bus bypass;

7. A backboard comprises a Complex Programmable Logic Device (CPLD), wherein the CPLD comprises a switching controller and a first integrated circuit bus selector;

8. A data processing apparatus, the apparatus comprising:

the system comprises a first sending unit, a second sending unit and a switching unit, wherein the first sending unit is used for sending a switching instruction to a switching controller included in a Complex Programmable Logic Device (CPLD) on a backboard based on a main controller on a mainboard so that the switching controller establishes connection between a general backboard management integrated circuit bus and a system integrated circuit bus;

9. An electronic device, comprising:

at least one processor; and

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-5.

10. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method according to any one of claims 1-5.