CN113918383A

CN113918383A - Core board resetting method, device, equipment, storage medium and program product

Info

Publication number: CN113918383A
Application number: CN202111185662.7A
Authority: CN
Inventors: 吴志勇
Original assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Current assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Priority date: 2021-10-12
Filing date: 2021-10-12
Publication date: 2022-01-11
Also published as: WO2023061327A1

Abstract

The disclosure provides a core board resetting method, a core board resetting device, core board resetting equipment, a storage medium and a program product, relates to the field of cloud computing, and can be applied to a cloud platform. One embodiment of a method for resetting a core board includes: monitoring the working state of the core board through a Micro Control Unit (MCU); outputting a power reset signal to the core board through the MCU under the condition that the working state of the core board is detected to be abnormal; and performing power-off reset on the core board. This embodiment provides a scheme that low-cost core plate resets based on MCU control, can realize that the operating condition of core plate is automatic power off when unusual resets.

Description

Core board resetting method, device, equipment, storage medium and program product

Technical Field

The disclosure relates to the field of cloud computing, and particularly relates to a method, a device, equipment and a storage medium for resetting a core board, which can be applied to a cloud platform.

Background

Currently, an ARM (Advanced RISC Machines) server core board generally includes an on-board SOC (System on Chip), a network controller, and a power supply Chip. When the core board network is abnormal (such as the network controller or the SOC is abnormal), the core board needs to be powered off and reset.

Disclosure of Invention

The embodiment of the disclosure provides a core board resetting method, a core board resetting device, core board resetting equipment, a core board resetting storage medium and a core board resetting program product.

In a first aspect, an embodiment of the present disclosure provides a core board resetting method, including: monitoring the working state of the core board through a Micro Control Unit (MCU); outputting a power reset signal to the core board through the MCU under the condition that the working state of the core board is detected to be abnormal; and performing power-off reset on the core board.

In a second aspect, an embodiment of the present disclosure provides a core board reset device, including: the monitoring module is configured to monitor the working state of the core board through the MCU; the output module is configured to output a power reset signal to the core board through the MCU under the condition that the core board working state is detected to be abnormal; a reset module configured to power-off reset the core board.

In a third aspect, an embodiment of the present disclosure provides an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method as described in any one of the implementations of the first aspect.

In a fourth aspect, the disclosed embodiments propose a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method as described in any one of the implementations of the first aspect.

In a fifth aspect, the present disclosure provides a computer program product including a computer program, which when executed by a processor implements the method as described in any implementation manner of the first aspect.

The core board reset method, device, equipment, storage medium and program product provided by the embodiments of the present disclosure provide a low-cost core board reset scheme based on MCU control, which can implement automatic power-off reset when the operating state of the core board is abnormal. The problem that automatic reset cannot be achieved when SOC faults occur is solved, and the problem that the reset cost of a core board is high is solved.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

Other features, objects, and advantages of the disclosure will become apparent from a reading of the following detailed description of non-limiting embodiments which proceeds with reference to the accompanying drawings. The drawings are included to provide a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:

FIG. 1 is a schematic diagram of core board reset of scenario 1 in the background art;

FIG. 2 is a schematic diagram of core board reset of scenario 2 in the background art;

FIG. 3 is a flow diagram of one embodiment of a core board reset method according to the present disclosure;

FIG. 4 is a flow diagram of yet another embodiment of a core board reset method according to the present disclosure;

FIG. 5 is a schematic diagram of the core board reset of the present disclosure;

FIG. 6 is a schematic structural diagram of one embodiment of a core board reset device according to the present disclosure;

fig. 7 is a block diagram of an electronic device for implementing the core board reset method according to an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of the embodiments of the disclosure are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

It should be noted that, in the present disclosure, the embodiments and features of the embodiments may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

In the related art, the core board is mainly subjected to a power-off reset operation through the following two schemes (scheme 1 and scheme 2). Fig. 1 shows a schematic diagram of the reset of the core board of scheme 1. As shown in fig. 1, the on-board SOC receives a power control signal from the power chip, and performs power-off reset on the power chip when an abnormality occurs in a polling detection manner. However, when the SOC itself loses control, the reset cannot be performed. Fig. 2 shows a schematic diagram of the reset of the core board of scheme 2. As shown in fig. 2, a switching signal of the power chip is led out to an external BMC (Baseboard Management Controller) control module, and when a network anomaly is detected, the power-off reset is performed on the core board with a fault manually or automatically. However, the BMC control module has a high cost and requires a large investment in software and hardware development.

Fig. 3 illustrates a flow 300 of one embodiment of a core board reset method according to the present disclosure. The core board resetting method comprises the following steps:

step 301, monitoring the working state of the core board through the MCU.

In this embodiment, the main execution body of the reset method of the core board may monitor the operating state of the core board through an MCU (Micro Control Unit).

Generally, one end of the MCU may be connected to the SOC of the core board for monitoring the SOC and the operating state of the network controller. When the core board works normally, the SOC may output the heartbeat signal to the MCU in a normal cycle. When the core board has a fault, the SOC cannot output the heartbeat signal to the MCU, or the heartbeat signal can be output to the MCU only after a certain time.

And step 302, outputting a power reset signal to the core board through the MCU under the condition that the abnormal working state of the core board is detected.

In this embodiment, in the case that the core board is detected to have an abnormal operating state, the execution main body may output a power reset signal to the core board through the MCU.

Generally, the other end of the MCU may be connected to a power chip of the core board, for outputting a power reset signal to the power chip. When the core board is operating normally, the MCU may periodically receive a heartbeat signal from the SOC. At this time, the MCU may determine that the core board is in a normal operating state and will not output a power reset signal to the power chip. When the core board fails, the MCU cannot receive the heartbeat signal from the SOC, or can receive the heartbeat signal from the SOC after a certain time. At this time, the MCU may determine that the core board is in an abnormal operating state, and output a power reset signal to the power chip.

Step 303, performing power-off reset on the core board.

In this embodiment, the execution main body may perform power-off reset on the core board when the power chip receives a power reset signal.

Generally, the power chip can automatically restart its switch to complete the power-off reset of the core board.

The core board reset method provided by the embodiment of the disclosure provides a low-cost core board reset scheme based on MCU control, and can realize automatic power-off reset when the working state of the core board is abnormal. The problem that automatic reset cannot be achieved when SOC faults occur is solved, and the problem that the reset cost of a core board is high is solved.

With continued reference to fig. 4, a flow 400 of yet another embodiment of a core board reset method according to the present disclosure is shown.

Typically, a network of a plurality of core boards is connected in a server chassis through one or more network switching modules (switches) and performs uplink and downlink transmission of network signals. Therefore, in this embodiment, the MCU is added to the switch board where the network switching module is located, and the MCU may be used to control the reset of the core board. MCU is added on the existing switchboard bottom plate, and extra occupied space is not needed.

In general, the core board may include an SOC, a network controller, and a power supply chip. The MCU may connect the SOC and the power chip simultaneously. On one hand, the heartbeat signal output by the SOC can be accessed to the MCU and is used for monitoring the working state of the core board. On the other hand, a power reset signal of the power chip can be accessed to the MCU for controlling the core board to be reset after power off.

In practical applications, the SOC and the MCU may be provided with a GPIO (General-purpose input/output) port. When the operating condition of nuclear core plate is normal, SOC can pass through GPIO output heartbeat signal, and heartbeat signal inserts MCU's first GPIO mouth, and MCU can monitor GPIO's state, monitors the operating condition of nuclear core plate promptly. Meanwhile, the power reset signal is connected to a second GPIO port of the MCU, and the MCU can perform output control on the GPIO pin, namely, the power reset of the core board is controlled.

In this embodiment, the core board resetting method includes the following steps:

step 401, detecting a heartbeat signal of the SOC input through a first GPIO port of the MCU by polling and interrupting.

In this embodiment, the main executing body of the core board resetting method may detect the heartbeat signal of the SOC input through the first GPIO port of the MCU by polling and interrupting.

Generally, the SOC and MCU may be provided with GPIO ports. When the operating condition of nuclear core plate is normal, SOC can pass through GPIO output heartbeat signal, and heartbeat signal inserts MCU's first GPIO mouth, and MCU can monitor GPIO's state, monitors the operating condition of nuclear core plate promptly.

Step 402, determining core board faults when the state of the heartbeat signal of the SOC is abnormal.

In the present embodiment, the execution subject described above may determine that the core board is malfunctioning in the case where the state of the heartbeat signal of the SOC is abnormal.

In general, the MCU may periodically receive a heartbeat signal from the SOC when the core board is operating normally. At this time, the MCU may determine that the operating state of the core board is normal. When the core board fails, the MCU cannot receive the heartbeat signal from the SOC, or can receive the heartbeat signal from the SOC after a certain time. At this time, the MCU may determine that the operating state of the core board is abnormal.

In some embodiments, in the case where the heartbeat signal of the SOC cannot be detected, the execution subject may determine that the SOC is faulty; in the case where the frequency abnormality of the heartbeat signal of the SOC is detected, the execution body may determine that the network controller is malfunctioning. Thereby can carry out accurate location to nuclear core plate trouble.

And step 403, outputting a power reset signal to the power chip through a second GPIO port of the MCU under the condition that the core board is detected to be abnormal in working state.

In this embodiment, when the core board is detected to have an abnormal operating state, the execution main body may output a power reset signal to the power chip through the second GPIO port of the MCU.

Generally, the MCU may set GPIO ports. The power reset signal is connected to a second GPIO port of the MCU, and the MCU can output control to the GPIO pin, namely, the power reset of the core board is controlled.

Step 404, power-off reset is performed on the core board.

In this embodiment, the specific operation of step 404 has been described in detail in step 303 in the embodiment shown in fig. 3, and is not described herein again.

As can be seen from fig. 4, compared with the embodiment corresponding to fig. 3, the core board resetting method in this embodiment highlights the step of core board monitoring. Therefore, the SOC and the MCU in the solution described in this embodiment can be provided with GPIO ports. The SOC outputs heartbeat signals through the GPIO, the heartbeat signals are connected into the first GPIO port of the MCU, and the MCU monitors the state of the GPIO, so that the working state of the core board is monitored.

With further reference to fig. 5, a schematic diagram of the core board reset of the present disclosure is shown. As shown in fig. 5, the network switching module includes a plurality of ports: port 1, …, port N. The network switching module is connected with a plurality of core boards through ports: core board #1, …, core board # N. One port of the network switching module is connected with a core board. And adding an MCU on the switch bottom plate where the network switching module is positioned. The MCU comprises a plurality of GPIO ports. For each core board, the SOC outputs heartbeat signals through the GPIO, the heartbeat signals are connected to the first GPIO port of the MCU, and the MCU can monitor the state of the GPIO, namely the working state of the core board. Meanwhile, a power reset signal of the MCU is connected to a second GPIO port of the MCU, and the MCU can perform output control on the GPIO pin, namely, the power reset of the core board is controlled.

With further reference to fig. 6, as an implementation of the methods shown in the above figures, the present disclosure provides an embodiment of a core board resetting apparatus, which corresponds to the method embodiment shown in fig. 3, and which may be applied in various electronic devices.

As shown in fig. 6, the core board resetting device 600 of the present embodiment may include: a monitoring module 601, an output module 602, and a reset module 603. The monitoring module 601 is configured to monitor the operating state of the core board through the MCU; an output module 602 configured to output a power reset signal to the core board through the MCU, if the core board operating state is detected to be abnormal; a reset module 603 configured to power down reset the core board.

In this embodiment, in the core board resetting device 600: the specific processing of the monitoring module 601, the output module 602, and the reset module 603 and the technical effects thereof can refer to the related descriptions of step 301 and step 303 in the corresponding embodiment of fig. 3, which are not repeated herein.

In some optional implementation manners of this embodiment, the server chassis is connected to a network of the core board through the network switching module, and the MCU is added to the board of the switch where the network switching module is located, and is used to control the reset of the core board.

In some optional implementation manners of this embodiment, the core board includes a system on chip SOC, a network controller, and a power supply chip, a heartbeat signal output by the SOC is accessed to the MCU for monitoring the operating state of the core board, and a power supply reset signal of the power supply chip is accessed to the MCU for controlling the core board to reset when the core board is powered off.

In some optional implementation manners of this embodiment, the SOC outputs a heartbeat signal through the general purpose input/output GPIO, the heartbeat signal is accessed to the first GPIO port of the MCU, and the power reset signal is accessed to the second GPIO port of the MCU.

In some optional implementations of this embodiment, the monitoring module 601 includes: the detection sub-module is configured to detect a heartbeat signal of the SOC input through a first GPIO port of the MCU in a polling and interruption mode; a determination submodule configured to determine a core board failure in a case where a state of a heartbeat signal of the SOC is abnormal.

In some optional implementations of this embodiment, the determining sub-module is further configured to: determining SOC faults under the condition that heartbeat signals of the SOC cannot be detected; and determining that the network controller fails when the frequency of the heartbeat signal of the SOC is detected to be abnormal.

In some optional implementations of this embodiment, the output module 602 is further configured to: and outputting a power supply reset signal to the power supply chip through a second GPIO port of the MCU.

The present disclosure also provides an electronic device, a readable storage medium, and a computer program product according to embodiments of the present disclosure.

FIG. 7 illustrates a schematic block diagram of an example electronic device 700 that can be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 7, the device 700 comprises a computing unit 701, which may perform various suitable actions and processes according to a computer program stored in a Read Only Memory (ROM)702 or a computer program loaded from a storage unit 708 into a Random Access Memory (RAM) 703. In the RAM 703, various programs and data required for the operation of the device 700 can also be stored. The computing unit 701, the ROM 702, and the RAM 703 are connected to each other by a bus 704. An input/output (I/O) interface 705 is also connected to bus 704.

Various components in the device 700 are connected to the I/O interface 705, including: an input unit 706 such as a keyboard, a mouse, or the like; an output unit 707 such as various types of displays, speakers, and the like; a storage unit 708 such as a magnetic disk, optical disk, or the like; and a communication unit 709 such as a network card, modem, wireless communication transceiver, etc. The communication unit 709 allows the device 700 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

Computing unit 701 may be a variety of general purpose and/or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, and so forth. The calculation unit 701 executes the respective methods and processes described above, such as the core board reset method or the core board reset method. For example, in some embodiments, the core board reset method or the core board reset method may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 708. In some embodiments, part or all of a computer program may be loaded onto and/or installed onto device 700 via ROM 702 and/or communications unit 709. When a computer program is loaded into RAM 703 and executed by the computational unit 701, one or more steps of the core board reset method or the core board reset method described above may be performed. Alternatively, in other embodiments, the compute unit 701 may be configured to perform the core board reset method or the core board reset method in any other suitable manner (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), and the Internet.

The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server with a combined blockchain.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in this disclosure may be performed in parallel or sequentially or in a different order, as long as the desired results of the technical solutions provided by this disclosure can be achieved, and are not limited herein.

The above detailed description should not be construed as limiting the scope of the disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A core board reset method, comprising:

monitoring the working state of the core board through a Micro Control Unit (MCU);

under the condition that the core board working state is detected to be abnormal, outputting a power reset signal to the core board through the MCU;

and performing power-off reset on the core board.

2. The method of claim 1, wherein a network of the core board is connected via a network switch module within a server chassis, and the MCU is added to a switch board on which the network switch module is located, the MCU being configured to control the reset of the core board.

3. The method of claim 2, wherein the core board comprises a System On Chip (SOC), a network controller and a power chip, the SOC outputs a heartbeat signal to be connected to the MCU for monitoring the operating state of the core board, and the power chip has a power reset signal to be connected to the MCU for controlling the power-off reset of the core board.

4. The method of claim 3, wherein the SOC outputs the heartbeat signal through a General Purpose Input Output (GPIO), the heartbeat signal is coupled into a first GPIO port of the MCU, and the power reset signal is coupled into a second GPIO port of the MCU.

5. The method of claim 4, wherein the monitoring the operating state of the core board by the MCU comprises:

detecting a heartbeat signal of the SOC input through a first GPIO port of the MCU in a polling and interruption mode;

and determining the core board fault under the condition that the heartbeat signal state of the SOC is abnormal.

6. The method of claim 5, wherein the determining the core board fault in the event of an abnormal state of a heartbeat signal of the SOC comprises:

determining the SOC fault if the heartbeat signal of the SOC cannot be detected;

determining that the network controller is faulty if the frequency of the heartbeat signal of the SOC is detected to be abnormal.

7. The method of claim 5 or 6, wherein said outputting a power reset signal to said core board by said MCU comprises:

and outputting the power supply reset signal to the power supply chip through a second GPIO port of the MCU.

8. A core board reset device comprising:

the monitoring module is configured to monitor the working state of the core board through the MCU;

an output module configured to output a power reset signal to the core board through the MCU in case that the core board operating state is detected to be abnormal;

a reset module configured to power-down reset the core board.

9. The apparatus of claim 8, wherein the network of the core board is connected via a network switch module in the server chassis, and the MCU is added to the switch board where the network switch module is located, and the MCU is configured to control the reset of the core board.

10. The apparatus of claim 9, wherein the core board comprises a system on chip SOC, a network controller and a power chip, the SOC outputs a heartbeat signal to the MCU for monitoring the operating status of the core board, and the power chip has a power reset signal to the MCU for controlling the core board to reset after power off.

11. The apparatus of claim 10, wherein the SOC outputs the heartbeat signal through a General Purpose Input Output (GPIO), the heartbeat signal being coupled to a first GPIO port of the MCU, the power reset signal being coupled to a second GPIO port of the MCU.

12. The apparatus of claim 11, wherein the monitoring module comprises:

the detection sub-module is configured to detect a heartbeat signal of the SOC input through a first GPIO port of the MCU in a polling and interruption mode;

a determining sub-module configured to determine the core board failure in case a heartbeat signal state of the SOC is abnormal.

13. The apparatus of claim 12, wherein the determination submodule is further configured to:

14. The apparatus of claim 12 or 13, wherein the output module is further configured to:

15. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

16. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of any one of claims 1-7.

17. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1-7.