WO2023061327A1

WO2023061327A1 - Core board reset method and apparatus, device, storage medium and program product

Info

Publication number: WO2023061327A1
Application number: PCT/CN2022/124359
Authority: WO
Inventors: 吴志勇
Original assignee: 北京百度网讯科技有限公司
Priority date: 2021-10-12
Filing date: 2022-10-10
Publication date: 2023-04-20
Also published as: CN113918383A

Abstract

The present application provides a core board reset method and apparatus, a device, a storage medium and a program product, which relate to the field of cloud computing, and which may be applied to a cloud platform. A specific embodiment of the core board reset method comprises: monitoring a working state of a core board by means of a micro control unit (MCU); when detected that the working state of the core board is abnormal, outputting a power reset signal to the core board by means of the MCU; and performing a power-off reset on the core board. The embodiment provides a low-cost core board reset solution based on MCU control, which may achieve automatic power-off reset when the working state of a core board is abnormal.

Description

Core board reset method, device, equipment, storage medium and program product

This patent application claims the priority of the Chinese patent application with the application number 202111185662.7 and the title of the invention "core board reset method, device, equipment, storage medium and program product" submitted on October 12, 2021. The full text of the application Incorporated into this application by reference.

technical field

The disclosure relates to the field of cloud computing, can be applied to cloud platforms, and specifically relates to a core board reset method, device, equipment and storage medium.

Background technique

At present, the ARM (Advanced RISC Machines, RISC microprocessor) server core board usually includes an on-board SOC (System on Chip, system-on-chip), network controller and power supply chip. When the core board network is abnormal (for example, the network controller or SOC is abnormal), it is necessary to perform a power-off reset operation on the core board.

Contents of the invention

Embodiments of the present disclosure provide a core board reset method, device, equipment, storage medium, and program product.

In the first aspect, the embodiment of the present disclosure proposes a method for resetting the core board, including: monitoring the working state of the core board through a micro control unit MCU; when detecting an abnormal working state of the core board, outputting power to the core board through the MCU Reset signal; power off and reset the core board.

In the second aspect, the embodiment of the present disclosure proposes a core board reset device, including: a monitoring module configured to monitor the working state of the core board through a micro control unit MCU; an output module configured to detect the core board working state In case of abnormality, the MCU outputs a power reset signal to the core board; the reset module is configured to reset the core board after power-off.

In a third aspect, an embodiment of the present disclosure provides an electronic device, including: at least one processor; and a memory connected to the at least one processor in communication; wherein, the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by Executed by at least one processor, so that at least one processor can execute the method described in any implementation manner of the first aspect.

In a fourth aspect, the embodiments of the present disclosure provide a non-transitory computer-readable storage medium storing computer instructions, the computer instructions are used to make a computer execute the method described in any implementation manner in the first aspect.

In a fifth aspect, the embodiments of the present disclosure provide a computer program product, including a computer program. When the computer program is executed by a processor, the method described in any implementation manner in the first aspect is implemented.

The core board reset method, device, equipment, storage medium and program product provided by the embodiments of the present disclosure provide a low-cost core board reset solution based on MCU control, which can realize automatic power-off reset when the core board is in an abnormal working state . Not only solves the problem that the SOC cannot be automatically reset when the SOC fails, but also solves the problem of high cost of resetting the core board.

It should be understood that what is described in this section is not intended to identify key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will be readily understood through the following description.

Description of drawings

Other features, objects and advantages of the present disclosure will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings. The accompanying drawings are used to better understand the present solution, and do not constitute a limitation to the present disclosure. in:

Fig. 1 is the schematic diagram of the reset of the core board of scheme 1 in the background technology;

Fig. 2 is the schematic diagram of the core board reset of scheme 2 in the background technology;

Fig. 3 is a flow chart according to an embodiment of the core board reset method of the present disclosure;

Fig. 4 is the flow chart of another embodiment of the core board resetting method according to the present disclosure;

Fig. 5 is the schematic diagram of the reset of the core board of the present disclosure;

6 is a schematic structural view of an embodiment of a core board reset device according to the present disclosure;

Fig. 7 is a block diagram of an electronic device used to implement the method for resetting a core board according to an embodiment of the present disclosure.

Detailed ways

Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and they should be regarded as exemplary only. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

It should be noted that, in the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and embodiments.

In related technologies, the power-off reset operation of the core board is mainly performed through the following two schemes (Scheme 1 and Scheme 2). FIG. 1 shows a schematic diagram of core board reset in solution 1. As shown in Figure 1, the on-board SOC connects the power control signal to the power chip, and through polling detection, when an abnormality occurs, the power chip is powered off and reset. However, when the SOC itself is out of control, it cannot be reset. FIG. 2 shows a schematic diagram of core board reset in solution 2. As shown in Figure 2, the switching signal of the power chip is connected to the external BMC (Baseboard Management Controller, Baseboard Management Controller) control module. When an abnormality is detected in the network, the faulty core board is manually or automatically reset after power-off. However, the cost of the BMC control module is relatively high, requiring more investment in software and hardware development.

FIG. 3 shows a process 300 of an embodiment of a method for resetting a core board according to the present disclosure. The method for resetting the core board includes the following steps:

Step 301, monitor the working status of the core board through the micro control unit MCU.

In this embodiment, the execution subject of the core board reset method can monitor the working state of the core board through an MCU (Micro Control Unit, Micro Control Unit).

Usually, one end of the MCU can be connected to the SOC of the core board to monitor the working status of the SOC and the network controller. When the core board is working normally, the SOC can output the heartbeat signal to the MCU in a normal cycle. When the core board fails, the SOC cannot output the heartbeat signal to the MCU, or the heartbeat signal can only be output to the MCU after a certain period of time.

Step 302 , outputting a power reset signal to the core board through the MCU when an abnormal working state of the core board is detected.

In this embodiment, when an abnormal working state of the core board is detected, the execution subject may output a power reset signal to the core board through the MCU.

Usually, the other end of the MCU can be connected to the power chip of the core board for outputting a power reset signal to the power chip. When the core board is working normally, the MCU can periodically receive the heartbeat signal from the SOC. At this time, the MCU can determine that the working state of the core board is normal, and will not output a power reset signal to the power chip. When the core board fails, the MCU cannot receive the heartbeat signal from the SOC, or can receive the heartbeat signal from the SOC after a certain period of time. At this time, the MCU can determine that the working state of the core board is abnormal, and will output a power reset signal to the power chip.

Step 303, perform a power-off reset on the core board.

In this embodiment, when the power supply chip receives a power reset signal, the execution subject may perform a power-off reset on the core board.

Usually, the power chip can automatically restart its switch to complete the power-off reset of the core board.

The core board reset method provided by the embodiments of the present disclosure provides a low-cost core board reset solution based on MCU control, which can realize automatic power-off reset of the core board when the working state of the core board is abnormal. Not only solves the problem that the SOC cannot be automatically reset when the SOC fails, but also solves the problem of high cost of resetting the core board.

Continue to refer to FIG. 4 , which shows a process 400 of another embodiment of the core board reset method according to the present disclosure.

Usually, one or more network switching modules (switches) in the server chassis are connected to the network of multiple core boards, and the uplink and downlink transmission of network signals is performed. Therefore, in this embodiment, an MCU is provided on the switch backplane where the network switch module is located, and the MCU can be used to control the reset of the core board. Add an MCU to the existing switch chassis without occupying additional space.

Generally, the core board can include SOC, network controller and power chip. MCU can connect SOC and power chip at the same time. On the one hand, the heartbeat signal output by the SOC can be connected to the MCU to monitor the working status of the core board. On the other hand, the power reset signal of the power chip can be connected to the MCU to control the power-off reset of the core board.

In practical applications, SOC and MCU can set GPIO (General-purpose input/output, general-purpose input and output) ports. When the working state of the core board is normal, the SOC can output the heartbeat signal through the GPIO, and the heartbeat signal is connected to the first GPIO port of the MCU, and the MCU can monitor the state of the GPIO, that is, the working state of the core board. At the same time, the power reset signal is connected to the second GPIO port of the MCU, and the MCU can control the output of the GPIO pin, that is, control the power reset of the core board.

In this embodiment, the method for resetting the core board includes the following steps:

Step 401: Detect the heartbeat signal of the SOC input through the first GPIO port of the MCU by means of polling and interrupting.

In this embodiment, the execution subject of the core board reset method may detect the heartbeat signal of the SOC input through the first GPIO port of the MCU by polling and interrupting.

Usually, SOC and MCU can set GPIO port. When the working state of the core board is normal, the SOC can output the heartbeat signal through the GPIO, and the heartbeat signal is connected to the first GPIO port of the MCU, and the MCU can monitor the state of the GPIO, that is, the working state of the core board.

Step 402, if the state of the heartbeat signal of the SOC is abnormal, it is determined that the core board is faulty.

In this embodiment, when the state of the heartbeat signal of the SOC is abnormal, the execution subject may determine that the core board is faulty.

Usually, when the core board is working normally, the MCU can periodically receive the heartbeat signal from the SOC. At this time, the MCU can determine that the working state of the core board is normal. When the core board fails, the MCU cannot receive the heartbeat signal from the SOC, or can receive the heartbeat signal from the SOC after a certain period of time. At this time, the MCU may determine that the working state of the core board is abnormal.

In some embodiments, if the heartbeat signal of the SOC cannot be detected, the execution subject may determine that the SOC is faulty; if the frequency of the heartbeat signal of the SOC is abnormal, the execution subject may determine that the network controller is faulty. In this way, the core board fault can be accurately located.

Step 403 , outputting a power reset signal to the power chip through the second GPIO port of the MCU in the case of detecting that the working state of the core board is abnormal.

In this embodiment, when an abnormal working state of the core board is detected, the execution subject may output a power reset signal to the power chip through the second GPIO port of the MCU.

Usually, MCU can set GPIO port. The power reset signal is connected to the second GPIO port of the MCU, and the MCU can control the output of the GPIO pin, that is, control the power reset of the core board.

Step 404, perform a power-off reset on the core board.

In this embodiment, the specific operation of step 404 has been introduced in detail in step 303 in the embodiment shown in FIG. 3 , and will not be repeated here.

It can be seen from FIG. 4 that, compared with the embodiment corresponding to FIG. 3 , the core board reset method in this embodiment highlights the steps of core board monitoring. Therefore, the SOC and the MCU in the solution described in this embodiment can set the GPIO port. The SOC outputs a heartbeat signal through the GPIO, and the heartbeat signal is connected to the first GPIO port of the MCU, and the MCU monitors the state of the GPIO, thereby realizing the monitoring of the working state of the core board.

Further referring to FIG. 5 , it shows a principle diagram of the reset of the core board of the present disclosure. As shown in Figure 5, the network switching module includes multiple ports: port 1,..., port N. The network switching module is connected to multiple core boards through ports: core board #1,..., core board #N. Wherein, one port of the network switching module is connected to one core board. Set the MCU on the switch chassis where the network switch module is located. The MCU includes multiple GPIO ports. For each core board, its SOC outputs a heartbeat signal through GPIO, and the heartbeat signal is connected to the first GPIO port of the MCU. The MCU can monitor the state of the GPIO, that is, monitor the working state of the core board. At the same time, the power reset signal is connected to the second GPIO port of the MCU, and the MCU can control the output of the GPIO pin, that is, control the power reset of the core board.

Further referring to FIG. 6 , as an implementation of the methods shown in the above figures, the present disclosure provides an embodiment of a core board reset device. The device embodiment corresponds to the method embodiment shown in FIG. 3 , and the device specifically It can be applied to various electronic devices.

As shown in FIG. 6 , the core board reset device 600 of this embodiment may include: a monitoring module 601 , an output module 602 and a reset module 603 . Wherein, the monitoring module 601 is configured to monitor the working state of the core board through the micro control unit MCU; the output module 602 is configured to output a power reset signal to the core board through the MCU when an abnormal working state of the core board is detected; The reset module 603 is configured to perform a power-off reset on the core board.

In this embodiment, in the core board reset device 600: the specific processing of the monitoring module 601, the output module 602 and the reset module 603 and the technical effects brought by them can refer to the steps 301-303 in the corresponding embodiment of FIG. Relevant descriptions will not be repeated here.

In some optional implementations of this embodiment, the network switching module in the server chassis is connected to the network of the core board, and an MCU is set on the switch chassis where the network switching module is located, and the MCU is used to control the reset of the core board.

In some optional implementations of this embodiment, the core board includes a system-on-chip SOC, a network controller, and a power chip. The heartbeat signal output by the SOC is connected to the MCU for monitoring the working status of the core board. The power chip The power reset signal connected to the MCU is used to control the power-off reset of the core board.

In some optional implementations of this embodiment, the SOC outputs a heartbeat signal through a general-purpose input and output GPIO, the heartbeat signal is connected to the first GPIO port of the MCU, and the power reset signal is connected to the second GPIO port of the MCU.

In some optional implementations of this embodiment, the monitoring module 601 includes: a detection submodule configured to detect the heartbeat signal of the SOC input through the first GPIO port of the MCU through polling and interruption; the determination submodule , configured to determine a failure of the core board when the state of the heartbeat signal of the SOC is abnormal.

In some optional implementations of this embodiment, the determining submodule is further configured to: determine that the SOC is faulty when the heartbeat signal of the SOC cannot be detected; and determine that the frequency of the heartbeat signal of the SOC is abnormal , to determine network controller failure.

In some optional implementation manners of this embodiment, the output module 602 is further configured to: output a power reset signal to the power chip through the second GPIO port of the MCU.

According to the embodiments of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

FIG. 7 shows a schematic block diagram of an example electronic device 700 that may be used to implement embodiments of the present disclosure. Electronic device is intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. Electronic devices may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are by way of example only, and are not intended to limit implementations of the disclosure described and/or claimed herein.

As shown in FIG. 7, the device 700 includes a computing unit 701 that can execute according to a computer program stored in a read-only memory (ROM) 702 or loaded from a storage unit 708 into a random-access memory (RAM) 703. Various appropriate actions and treatments. In the RAM 703, various programs and data necessary for the operation of the device 700 can also be stored. The computing unit 701, ROM 702, and RAM 703 are connected to each other through a bus 704. An input/output (I/O) interface 705 is also connected to the bus 704 .

Multiple components in the device 700 are connected to the I/O interface 705, including: an input unit 706, such as a keyboard, a mouse, etc.; an output unit 707, such as various types of displays, speakers, etc.; a storage unit 708, such as a magnetic disk, an optical disk, etc. ; and a communication unit 709, such as a network card, a modem, a wireless communication transceiver, and the like. The communication unit 709 allows the device 700 to exchange information/data with other devices over a computer network such as the Internet and/or various telecommunication networks.

The computing unit 701 may be various general-purpose and/or special-purpose processing components having processing and computing capabilities. Some examples of computing units 701 include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processing processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 701 executes various methods and processes described above, such as a core board reset method or a core board reset method. For example, in some embodiments, the core board reset method or the core board reset method may be implemented as a computer software program, which is tangibly embodied in a machine-readable medium, such as the storage unit 708 . In some embodiments, part or all of the computer program may be loaded and/or installed on the device 700 via the ROM 702 and/or the communication unit 709. When the computer program is loaded into the RAM 703 and executed by the computing unit 701, the core board reset method or one or more steps of the core board reset method described above can be performed. Alternatively, in other embodiments, the computing unit 701 may be configured to execute a core board reset method or a core board reset method in any other appropriate manner (for example, by means of firmware).

Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips Implemented in a system of systems (SOC), load programmable logic device (CPLD), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include being implemented in one or more computer programs executable and/or interpreted on a programmable system including at least one programmable processor, the programmable processor Can be special-purpose or general-purpose programmable processor, can receive data and instruction from storage system, at least one input device, and at least one output device, and transmit data and instruction to this storage system, this at least one input device, and this at least one output device an output device.

Program codes for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special purpose computer, or other programmable data processing devices, so that the program codes, when executed by the processor or controller, make the functions/functions specified in the flow diagrams and/or block diagrams Action is implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include one or more wire-based electrical connections, portable computer discs, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, compact disk read only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination of the foregoing.

To provide for interaction with the user, the systems and techniques described herein can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user. ); and a keyboard and pointing device (eg, a mouse or a trackball) through which a user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and can be in any form (including Acoustic input, speech input or, tactile input) to receive input from the user.

The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., as a a user computer having a graphical user interface or web browser through which a user can interact with embodiments of the systems and techniques described herein), or including such backend components, middleware components, Or any combination of front-end components in a computing system. The components of the system can be interconnected by any form or medium of digital data communication, eg, a communication network. Examples of communication networks include: Local Area Network (LAN), Wide Area Network (WAN) and the Internet.

A computer system may include clients and servers. Clients and servers are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, a server of a distributed system, or a server combined with a blockchain.

It should be understood that steps may be reordered, added or deleted using the various forms of flow shown above. For example, each step described in the present disclosure may be executed in parallel, sequentially, or in a different order, as long as the desired result of the technical solution provided by the present disclosure can be achieved, no limitation is imposed herein.

The specific implementation manners described above do not limit the protection scope of the present disclosure. It should be apparent to those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made depending on design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

A core board reset method, comprising:

Monitor the working status of the core board through the micro control unit MCU;

In the case of detecting that the working state of the core board is abnormal, outputting a power reset signal to the core board through the MCU;

Perform a power-off reset on the core board.
The method according to claim 1, wherein the network switching module in the server chassis is connected to the core board network, and the MCU is arranged on the switch chassis where the network switching module is located, and the MCU is used to control the reset of the core board .
The method according to claim 2, wherein the core board includes a system-on-chip (SOC), a network controller, and a power supply chip, and the heartbeat signal output by the SOC is connected to the MCU for working on the core board. The state is monitored, and the power reset signal of the power chip is connected to the MCU to control the power-off reset of the core board.
The method according to claim 3, wherein the SOC outputs the heartbeat signal through a general-purpose input and output GPIO, the heartbeat signal is connected to the first GPIO port of the MCU, and the power reset signal is connected to the The second GPIO port of the MCU.
The method according to claim 4, wherein the monitoring of the operating state of the core board by a micro control unit MCU includes:

Detecting the heartbeat signal of the SOC input through the first GPIO port of the MCU by polling and interrupting;

If the state of the heartbeat signal of the SOC is abnormal, it is determined that the core board is faulty.
The method according to claim 5, wherein, in the case of an abnormal state of the heartbeat signal of the SOC, determining that the core board is faulty comprises:

When the heartbeat signal of the SOC cannot be detected, determine that the SOC is faulty;

If it is detected that the frequency of the heartbeat signal of the SOC is abnormal, it is determined that the network controller is faulty.
The method according to claim 5 or 6, wherein said outputting a power reset signal to said core board through said MCU comprises:

Outputting the power reset signal to the power chip through the second GPIO port of the MCU.
A core board reset device, comprising:

The monitoring module is configured to monitor the working state of the core board through the micro control unit MCU;

The output module is configured to output a power reset signal to the core board through the MCU when an abnormal working state of the core board is detected;

The reset module is configured to perform a power-off reset on the core board.
The device according to claim 8, wherein the network switching module in the server chassis is connected to the core board network, and the MCU is arranged on the switch chassis where the network switching module is located, and the MCU is used to control the reset of the core board .
The device according to claim 9, wherein the core board includes a system-on-chip (SOC), a network controller, and a power supply chip, and the heartbeat signal output by the SOC is connected to the MCU for the operation of the core board. The state is monitored, and the power reset signal of the power chip is connected to the MCU to control the power-off reset of the core board.
The device according to claim 10, wherein the SOC outputs the heartbeat signal through a general-purpose input and output GPIO, the heartbeat signal is connected to the first GPIO port of the MCU, and the power reset signal is connected to the The second GPIO port of the MCU.
The device according to claim 11, wherein the monitoring module comprises:

The detection submodule is configured to detect the heartbeat signal of the SOC input through the first GPIO port of the MCU by means of polling and interruption;

The determining submodule is configured to determine that the core board is faulty when the state of the heartbeat signal of the SOC is abnormal.
The device according to claim 12, wherein the determining submodule is further configured to:

When the heartbeat signal of the SOC cannot be detected, determine that the SOC is faulty;

If it is detected that the frequency of the heartbeat signal of the SOC is abnormal, it is determined that the network controller is faulty.
The apparatus according to claim 12 or 13, wherein the output module is further configured to:

Outputting the power reset signal to the power chip through the second GPIO port of the MCU.
An electronic device comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor, the instructions are executed by the at least one processor, so that the at least one processor can perform any one of claims 1-7. Methods.
A non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the method according to any one of claims 1-7.
A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1-7.