CN115902561A - Avalanche tolerance test circuit and test method thereof - Google Patents
Avalanche tolerance test circuit and test method thereof Download PDFInfo
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- CN115902561A CN115902561A CN202211398815.0A CN202211398815A CN115902561A CN 115902561 A CN115902561 A CN 115902561A CN 202211398815 A CN202211398815 A CN 202211398815A CN 115902561 A CN115902561 A CN 115902561A
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Abstract
The application provides an avalanche tolerance test circuit and a test method thereof. The avalanche tolerance test circuit comprises a power supply, a bus capacitor and a test circuit connected with a tested device, wherein the power supply is used for charging the bus capacitor in a capacitor charging stage, the bus capacitor is used for charging an inductor in the test circuit in an inductor charging stage, the test circuit is used for disconnecting the tested device from the power supply and the bus capacitor in the inductor charging stage and when the stored energy of the inductor reaches a preset target stored energy, and enabling the tested device to be in an avalanche state in the avalanche test stage until the current flowing through the tested device is reduced to 0A, and in the process, when the tested device breaks down a short circuit or the avalanche voltage is abnormal, the tested device is short-circuited and is connected into a discharge resistor to release the energy stored by the inductor. The method and the device realize the failure protection of the tested device, so that the tested device subjected to the avalanche tolerance test is effectively protected after failure, and the analysis of the tested device after failure is facilitated.
Description
[ technical field ] A method for producing a semiconductor device
The application relates to the technical field of power electronic device testing, in particular to an avalanche tolerance testing circuit and a testing method thereof.
[ background of the invention ]
In practical application, not only the main loop of the power semiconductor device has inductance, but also stray inductance is distributed in the power semiconductor device, when the power semiconductor device is turned off, a release path of inductance energy is disconnected, so that the inductance generates a high voltage applied to the turned-off power semiconductor device, and when the high voltage exceeds a certain value, the power semiconductor device enters an avalanche breakdown state, and if the avalanche energy exceeds a certain value, the power semiconductor device is completely damaged. Therefore, the research on the avalanche tolerance of the power semiconductor device is necessary, which has very important significance for analyzing the cause of the avalanche failure of the power semiconductor device, optimizing the avalanche tolerance of the power semiconductor device from the aspect of a circuit structure and the like, can provide a reference for a user to select the power semiconductor device, and can also provide an idea for a manufacturer to develop a new generation of power semiconductor devices with excellent avalanche tolerance characteristics.
In the related art, when a power semiconductor device is tested by using an avalanche tolerance test apparatus, the avalanche tolerance test apparatus still has many disadvantages, such as: the energy storage of the inductor cannot be consumed quickly, so that the power semiconductor device to be tested cannot be protected effectively after failure, and even the test equipment can be damaged, which is not favorable for the analysis of the power semiconductor device after failure and the effective protection of the test equipment; rapid fault response cannot be achieved, analysis after the power semiconductor device fails is not facilitated, and effective protection of test equipment is also not facilitated; the precise control of the inductor current in a single pulse cannot be achieved, that is, a certain time is required to wait for the power semiconductor device to cool every interval, then the pulse time is controlled, and the inductor current gradually approaches the target value by repeating the test of the avalanche tolerance for multiple times.
Therefore, there is a need for an improvement in the circuit structure of the avalanche capability test apparatus described above.
[ summary of the invention ]
The application provides an avalanche tolerance test circuit and a test method thereof, and aims to solve the problem that a power semiconductor device for performing avalanche tolerance test in the related technology cannot be effectively protected after failure.
In order to solve the above technical problem, a first aspect of the embodiments of the present application provides an avalanche tolerance test circuit, including a power supply, a bus capacitor, and a test circuit, where the power supply is connected to the bus capacitor, the bus capacitor is connected to the test circuit, the test circuit is used for connecting a device under test, the test circuit includes an inductor, a gate driving voltage of the device under test is less than or equal to 0V, and a test of the device under test by the avalanche tolerance test circuit includes a capacitor charging stage, an inductor charging stage, and an avalanche test stage that are sequentially performed in a time sequence; wherein:
the power supply is used for charging the bus capacitor in the capacitor charging stage;
the bus capacitor is used for charging the inductor in the inductor charging stage;
the test circuit is used for disconnecting the device to be tested from the power supply and the bus capacitor in an inductor energy charging stage and when the energy storage of the inductor reaches a preset target energy storage, enabling the device to be tested to be in an avalanche state in an avalanche test stage until the current flowing through the device to be tested is reduced to 0A, and in the process, when the device to be tested breaks down and is short-circuited or the avalanche voltage is abnormal, short-circuiting the device to be tested and connecting the discharge resistor to release the energy stored by the inductor.
A second aspect of the embodiments of the present application provides an avalanche tolerance test method, which is applied to an avalanche tolerance test circuit, where the avalanche tolerance test circuit includes a power supply, a bus capacitor, and a test circuit, the power supply is connected to the bus capacitor, the bus capacitor is connected to the test circuit, the test circuit is used to connect a device under test, the test circuit includes an inductor, a gate driving voltage of the device under test is less than or equal to 0V, and a test of the device under test by the avalanche tolerance test circuit includes a capacitor charging stage, an inductor charging stage, and an avalanche test stage that are sequentially performed in time sequence; the avalanche tolerance test method comprises the following steps:
the power supply charges the bus capacitor in the capacitor charging stage;
the bus capacitor charges the inductor in the inductor charging stage;
the test circuit disconnects the device to be tested from the power supply and the bus capacitor in the inductor charging stage and when the stored energy of the inductor reaches the preset target stored energy, and enables the device to be tested to be in an avalanche state in the avalanche test stage until the current flowing through the device to be tested is reduced to 0A, and in the process, when the device to be tested is broken down and short-circuited or the avalanche voltage is abnormal, the device to be tested is short-circuited and is connected into the discharge resistor to release the energy stored by the inductor.
As can be seen from the above description, the present application has the following advantages compared with the related art:
the power supply, the bus capacitor and the test circuit jointly form an avalanche tolerance test circuit, and the test of the avalanche tolerance test circuit on the tested device is divided into a capacitor charging stage, an inductor charging stage and an avalanche test stage which are sequentially carried out in time sequence. In practical application, the power supply charges the bus capacitor in a capacitor charging stage; the bus capacitor charges the inductor in the inductor charging stage; the test circuit is used for disconnecting the electrical connection between the tested device and the power supply and the bus capacitor in the inductor energy charging stage and when the energy storage of the inductor reaches the preset target energy storage, enabling the tested device to be in an avalanche state in the avalanche test stage until the current flowing through the tested device is reduced to 0A, and in the process, when the tested device is in breakdown short circuit or the avalanche voltage is abnormal, the tested device is in short circuit and is connected into the discharge resistor to release the energy stored by the inductor. Therefore, in the process of performing the avalanche tolerance test on the device to be tested, when the device to be tested is in a breakdown short circuit or the avalanche voltage is abnormal (namely when the device to be tested fails), the short circuit of the device to be tested can be realized and the discharge resistor is connected to release the energy stored in the inductor, namely, the failure protection of the device to be tested is realized, so that the device to be tested which performs the avalanche tolerance test can be effectively protected after the device to be tested fails, and the analysis after the device to be tested fails is facilitated.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the related art or the embodiments of the present application, the drawings needed to be used in the description of the related art or the embodiments of the present application will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, not all embodiments, and other drawings can be obtained by those skilled in the art without inventive efforts.
Fig. 1 is a schematic diagram of a conventional avalanche tolerance test topology;
fig. 2 is a block diagram of an avalanche tolerance test circuit provided in an embodiment of the present application;
fig. 3 is a schematic circuit structure diagram of an avalanche tolerance test circuit provided in an embodiment of the present application;
fig. 4 is a timing diagram of an avalanche tolerance test circuit provided in an embodiment of the present application;
fig. 5 is a schematic circuit structure diagram of an avalanche tolerance test circuit provided in an embodiment of the present application;
fig. 6 is a schematic flow chart of an avalanche tolerance testing method provided in the embodiment of the present application.
[ detailed description ] A
In order to make the objects, technical solutions and advantages of the present application more obvious and understandable, the present application will be clearly and completely described below in conjunction with the embodiments of the present application and the corresponding drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. It should be understood that the embodiments of the present application described below are only used for explaining the present application and are not used for limiting the present application, that is, all other embodiments obtained by a person of ordinary skill in the art without making creative efforts based on the embodiments of the present application belong to the protection scope of the present application. In addition, the technical features involved in the embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 is a schematic diagram of a conventional avalanche tolerance test topology. The test process of the traditional avalanche tolerance test topology comprises two stages, wherein the first stage is that a switching tube Q1 and a tested device DUT are switched on, a power supply VDD, the switching tube Q1, an inductor L and the tested device DUT form a power loop (1), the power supply VDD charges the inductor L, the current of the inductor L is increased linearly, and the current of the inductor L depends on the switching tube Q1 and the switching time of the tested device DUT; the second stage is that the switch tube Q1 and the device under test DUT are turned off, and the diode, the device under test DUT and the inductor L form a power loop (2), and the device under test DUT enters into an avalanche state. The traditional avalanche tolerance test topology has some disadvantages, such as: firstly, when the DUT is short-circuited, the energy stored in the inductor L is consumed through the diode, the DUT, the inductor L resistor and the loop resistor, which results in longer energy consumption time, aggravates the damage of the DUT, and is not conducive to the analysis after the DUT fails; secondly, when a DUT (device under test) is open-circuited, extremely high voltage can appear at two ends of the DUT, and great damage risk is brought to a measuring instrument with avalanche tolerance; thirdly, in the process of measuring the avalanche tolerance of the inductor L, the inductance value is unstable, so that real-time sampling is needed to control the current of the inductor L, and the delay is large, thereby resulting in poor accuracy of inductor current control.
To this end, an embodiment of the present application provides an avalanche tolerance test circuit, a block diagram of the avalanche tolerance test circuit is shown in fig. 2, the avalanche tolerance test circuit includes a power supply VCC, a bus capacitor C1, and a test circuit, where the power supply VCC is connected to the bus capacitor C1, the bus capacitor C1 is connected to the test circuit, the test circuit is used to connect a device under test DUT, the test circuit includes an inductor L1, a gate driving voltage of the device under test DUT is less than or equal to 0V, and a test of the device under test DUT by the avalanche tolerance test circuit includes a capacitor charging phase, an inductor charging phase, and an avalanche test phase that are sequentially performed in time sequence. It should be noted that, in the embodiment of the present application, no special requirement is made on the power VCC and the bus capacitor C1, the power VCC meeting the specified parameters (such as output voltage, voltage output accuracy, etc.) can be selected according to the requirement of the practical application, the capacity of the bus capacitor C1 can be calculated according to the drop rate of the bus voltage, and the capacitor with low stray inductance is selected to be better applied.
Specifically, the power supply VCC is used to charge the bus capacitor C1 during the capacitor charging phase; the bus capacitor C1 is used for charging the inductor L1 in the inductor charging stage; the test circuit is used for disconnecting the DUT from the power supply VCC and the bus capacitor C1 during the inductor charging phase and when the stored energy of the inductor L1 reaches the preset target stored energy, and enabling the DUT to be in an avalanche state during the avalanche test phase until the current flowing through the DUT is reduced to 0A, and in the process, when the DUT breaks down a short circuit or the avalanche voltage is abnormal, the DUT is short-circuited and is connected into the discharge resistor to release the energy stored by the inductor L1. Since the bus capacitor C1 has a sufficiently large capacity, the bus voltage can be maintained well in the inductive charging stage.
It can be understood that, since the capacitor charging stage, the inductor charging stage and the avalanche testing stage are sequentially performed in time sequence, in practical application, the capacitor charging stage is performed first, that is, the bus capacitor C1 is charged by the power supply VCC; then, an inductor energy charging stage is carried out, namely, the inductor L1 is charged through the bus capacitor C1 (at the moment, the bus capacitor C1 is charged completely), and when the stored energy of the inductor L1 reaches a preset target stored energy, the test circuit can disconnect the connection between the DUT and the power supply VCC and the bus capacitor C1, which means that the DUT is about to enter an avalanche state; finally, the avalanche test stage is performed, that is, the DUT is formally put into the avalanche state by the test circuit until the current flowing through the DUT is reduced to 0A, and during this process, when the DUT is short-circuited or the avalanche voltage is abnormal, the test circuit will short-circuit the DUT and switch in the discharge resistor to release the energy stored in the inductor L1.
Therefore, in the process of performing the avalanche tolerance test on the DUT, when the DUT is in a short-circuit breakdown state or the avalanche voltage is abnormal (that is, when the DUT fails), the embodiment of the present application can realize short-circuiting the DUT and connecting the discharge resistor to release the energy stored in the inductor L1, that is, realize failure protection of the DUT, so that the DUT subjected to the avalanche tolerance test can be effectively protected after failing, which is beneficial to analysis of the DUT subjected to failure.
In some embodiments, please further refer to fig. 3, wherein fig. 3 is a schematic circuit structure diagram of an avalanche tolerance test circuit according to an embodiment of the present disclosure. The test circuit includes, in addition to an inductor L1, a first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a first resistor R1, a second resistor R2, a third resistor R3, and a diode D1, wherein the first resistor R1 is used as the discharge resistor, one end of a bus capacitor C1 is connected to the drain of the first switch tube Q1, and the other end is connected to the anode of the diode D1, the source of the first switch tube Q1 and the cathode of the diode D1 are connected to one end of the inductor L1, the other end of the inductor L1 is connected to one end of the first resistor R1 and the drain of the third switch tube Q3, the other end of the first resistor R1 is connected to the drain of the second switch tube Q2, the source of the second switch tube Q2 and the third switch tube Q3 are connected to the drain of the third switch tube Q4, the source of the fourth switch tube Q4 is connected to one end of the second resistor R2, the other end of the second resistor R2 and the anode of the diode D1 are used for connecting the DUT to the source of the DUT, and the fourth switch tube Q3 and the drain of the fourth switch tube Q3 are connected to the DUT.
Specifically, in the inductor energy charging stage, the first switch tube Q1, the third switch tube Q3 and the fourth switch tube Q4 are turned on, the bus capacitor C1 charges the inductor L1, and when the stored energy of the inductor L1 reaches the preset target stored energy (which is equivalent to the current of the second resistor R2 reaching the preset target current), the first switch tube Q1 is turned off, the diode D1 is turned on, and the connection between the DUT to be tested and the bus capacitor C1 and the power source VCC is turned off, that is, the DUT to be tested is about to enter the avalanche state. In the stage of the avalanche period, the fourth switching tube Q4 is turned off, the current flowing through the fourth switching tube Q4 is rapidly reduced and transferred to the device under test DUT, and meanwhile, since the gate driving voltage of the device under test DUT is less than or equal to 0V, the device under test DUT formally enters into the avalanche state until the current flowing through the third resistor R3 is reduced to 0A, and in the process, when the device under test DUT is broken down and short-circuited or the avalanche voltage is abnormal, the third switching tube Q3 is turned off, and the second switching tube Q2 and the fourth switching tube Q4 are rapidly turned on, so that the energy stored in the inductor L1 is released through the first resistor R1 and the device under test DUT is short-circuited. Preferably, the inductor L1 is a variable inductor, and the first resistor R1 is a variable resistor.
The first switching tube Q1, the second switching tube Q2, the third switching tube Q3, and the fourth switching tube Q4 may be power switching tubes or mechanical switching tubes, such as an IGBT (Insulated Gate Bipolar Transistor) or a relay. The diode D1 may be a freewheeling diode D1, or may be replaced by a power switch or a mechanical switch. The second resistor R2 and the third resistor R3 can adopt sampling resistors and can be replaced by shunts.
In some embodiments, still referring to fig. 2, the avalanche capability test circuit described above further includes a control circuit, in addition to the power source VCC, the bus capacitor C1 and the test circuit, the control circuit is connected to the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4, so as to control the on/off of the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4 through the control circuit. The control circuit may control the on and off of the first switch tube Q1, the second switch tube Q2, the third switch tube Q3 and the fourth switch tube Q4 through the driver (the drivers of the first switch tube Q1, the second switch tube Q2, the third switch tube Q3 and the fourth switch tube Q4 correspond to U1, U2, U3 and U4 in fig. 2, respectively), that is, the control circuit outputs a driving signal to the corresponding driver to drive the corresponding switch tube, so as to implement the on and off of the corresponding switch tube.
Further, the control circuit is also connected to the second resistor R2, the third resistor R3 and the device under test DUT, in which case the control circuit is configured to: collecting the voltage of a second resistor R2, and controlling a first switching tube Q1 and a fourth switching tube Q4 to be disconnected when the voltage of the second resistor R2 is greater than or equal to a preset first voltage threshold; collecting the voltage of a third resistor R3, and controlling a first switching tube Q1 and a third switching tube Q3 to be disconnected and a second switching tube Q2 and a fourth switching tube Q4 to be conducted when the voltage of the third resistor R3 is greater than or equal to a preset second voltage threshold; the arrangement can control the inductive current more quickly and accurately. The control circuit can control the on and off of the DUT (U5 in fig. 2 corresponds to the driver of the DUT), that is, output the driving signal to the driver of the DUT to drive the DUT, so as to realize the on and off of the DUT.
As one embodiment, still referring to fig. 2, the control circuit includes a control chip XP and a first comparator COMP1, wherein a non-inverting input terminal of the first comparator COMP1 is connected to the second resistor R2, an inverting input terminal and an output terminal of the first comparator COMP1 are connected to the control chip XP, and the control chip XP is connected to the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4. Specifically, the first comparator COMP1 is configured to collect a voltage of the second resistor R2, and compare the voltage of the second resistor R2 with a preset first voltage threshold; the control chip XP is used for controlling the first switch tube Q1 and the fourth switch tube Q4 to be disconnected when a comparison result of the first comparator COMP1 is that the voltage of the second resistor R2 is greater than or equal to a preset first voltage threshold.
In this embodiment, the control chip XP may output a first voltage threshold to the first comparator COMP1 according to a setting of a user, then the first comparator COMP1 collects a voltage across the second resistor R2 (or may sample after voltage division), when a current flowing through the second resistor R2 reaches a preset target value, a sampling voltage of the second resistor R2 is just greater than the first voltage threshold, so that a level of the first comparator COMP1 is inverted (that is, a comparison result of the first comparator COMP1 is that the voltage across the second resistor R2 is greater than or equal to the first voltage threshold), and a level inversion signal is generated to the control chip XP, and the control chip XP outputs a driving signal to the first switching tube Q1 and the fourth switching tube Q4 after receiving the level inversion signal, so as to control the first switching tube Q1 and the fourth switching tube Q4 to be disconnected.
As another embodiment, still referring to fig. 2, the control circuit further includes a second comparator COMP2 in addition to the control chip XP and the first comparator COMP1, a non-inverting input terminal of the second comparator COMP2 is connected to the third resistor R3, an inverting input terminal and an output terminal of the second comparator COMP2 are connected to the control chip XP, and the control chip XP is connected to the device under test DUT. Specifically, the second comparator COMP2 is configured to collect a voltage of the third resistor R3, and compare the voltage of the third resistor R3 with a preset second voltage threshold; the control chip XP is used for controlling the first switching tube Q1 and the third switching tube Q3 to be disconnected, and the second switching tube Q2 and the fourth switching tube Q4 to be connected when the comparison result of the second comparator COMP2 is that the voltage of the third resistor R3 is greater than or equal to a preset second voltage threshold value.
In this embodiment, the control chip XP may output a second voltage threshold to the second comparator COMP2 according to a setting of a user, then the second comparator COMP2 collects a voltage across the third resistor R3 (or may sample after voltage division), when a current flowing through the third resistor R3 reaches a preset target value, the sampled voltage across the third resistor R3 is just greater than the second voltage threshold, so that a level of the second comparator COMP2 is inverted (that is, a comparison result of the second comparator COMP2 is that the voltage across the third resistor R3 is greater than or equal to the second voltage threshold), and a level inversion signal is generated and sent to the control chip XP, and the control chip XP receives the level inversion signal and then outputs a driving signal to the first switching tube Q1, the second switching tube Q2, the third switching tube Q3, and the fourth switching tube Q4 to control the first switching tube Q1 to be disconnected from the third switching tube Q3, and the second switching tube Q2 to be connected to the fourth switching tube Q4.
It should be noted that the above embodiments are only preferred implementations of the embodiments of the present application, and are not only limitations on specific circuit structures and control logics of the test circuit and the control circuit; in this regard, a person skilled in the art can flexibly set the setting according to the actual application scenario on the basis of the embodiment of the present application.
To sum up, the embodiment of the present application provides an avalanche tolerance test circuit, which implements failure protection of a device under test DUT, so that the device under test DUT performing avalanche tolerance test can be effectively protected after failure, which is beneficial to analysis of the device under test DUT after failure, and meanwhile, the inductor current can be controlled more quickly and accurately, and the requirement of avalanche tolerance measurement accuracy is met. Referring to fig. 4, in fig. 4, Q4_ PWM represents a driving signal output by the control chip XP to the fourth switching tube Q4, IL represents a current of the inductor L1, I _ R3 represents a current of the third resistor R3, and V _ DUT represents a voltage of the device under test DUT. Further, if the measurement accuracy of the avalanche energy is not considered, or the device under test DUT is not driven, the circuit structure of the avalanche tolerance test circuit can be simplified as shown in fig. 5.
Fig. 6 is a schematic flow chart of an avalanche tolerance testing method provided in the embodiment of the present application. The embodiment of the application also provides an avalanche tolerance test method, which is realized based on the avalanche tolerance test circuit, and the avalanche tolerance test method comprises the following steps 601 to 603.
In the embodiment of the application, the test of the avalanche tolerance of the DUT is divided into three stages, namely a capacitor charging stage, an inductor charging stage and an avalanche test stage, and the capacitor charging stage, the inductor charging stage and the avalanche test stage are sequentially performed in time sequence, so that the capacitor charging stage needs to be performed first, that is, the bus capacitor C1 is charged through the power supply VCC.
In this embodiment of the application, after the capacitor charging phase is finished, an inductor charging phase is further required, that is, the inductor L1 is charged through the bus capacitor C1, and when the stored energy of the inductor L1 reaches a preset target stored energy, the test circuit disconnects the DUT from the power source VCC and the bus capacitor C1, which means that the DUT is about to enter an avalanche state.
In the embodiment of the present application, after the inductor energy charging stage is ended, an avalanche test stage is further required, that is, the DUT enters an avalanche state formally through the test circuit until the current flowing through the DUT is reduced to 0A, and in this process, when the DUT is short-circuited through breakdown or the avalanche voltage is abnormal, the test circuit shorts the DUT and connects to the discharge resistor, so as to release the energy stored in the inductor L1.
Therefore, in the process of performing the avalanche tolerance test on the DUT, when the DUT is in a breakdown short circuit or the avalanche voltage is abnormal (i.e., when the DUT fails), the method for performing the avalanche tolerance test can short the DUT and access the discharge resistor to release the energy stored in the inductor L1, i.e., achieve the failure protection of the DUT, so that the DUT can be effectively protected after the DUT is failed, and the method is favorable for analyzing the DUT after the DUT fails.
It should be noted that, the embodiments in the present disclosure are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the product class embodiment, since it is similar to the method class embodiment, the description is relatively simple, and for the relevant points, refer to the partial description of the method class embodiment.
It is further noted that, within the context of this application, relational terms such as first and second, and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. An avalanche tolerance test circuit is characterized by comprising a power supply, a bus capacitor and a test circuit, wherein the power supply is connected with the bus capacitor, the bus capacitor is connected with the test circuit, the test circuit is used for connecting a device under test, the test circuit comprises an inductor, the grid driving voltage of the device under test is less than or equal to 0V, and the test of the device under test by the avalanche tolerance test circuit comprises a capacitor charging stage, an inductor charging stage and an avalanche test stage which are sequentially carried out in time sequence; wherein:
the power supply is used for charging the bus capacitor in the capacitor charging stage;
the bus capacitor is used for charging the inductor in the inductor charging stage;
the test circuit is used for disconnecting the device under test from the power supply and the bus capacitor in the inductor charging stage and when the stored energy of the inductor reaches a preset target stored energy, enabling the device under test to be in an avalanche state in the avalanche test stage until the current flowing through the device under test is reduced to 0A, and in the process, when the device under test breaks down and is short-circuited or the avalanche voltage is abnormal, short-circuiting the device under test and switching in a discharge resistor to release the energy stored in the inductor.
2. The avalanche tolerance test circuit according to claim 1, wherein the test circuit further comprises a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a first resistor, a second resistor, a third resistor and a diode, one end of the bus capacitor is connected to the drain of the first switch tube, the other end of the bus capacitor is connected to the anode of the diode, the source of the first switch tube and the cathode of the diode are connected to one end of the inductor, the other end of the inductor is connected to one end of the first resistor and the drain of the third switch tube, the other end of the first resistor is connected to the drain of the second switch tube, the sources of the second switch tube and the third switch tube are connected to the drain of the fourth switch tube, the source of the fourth switch tube is connected to one end of the second resistor, the other end of the second resistor and the anode of the diode are used for connecting the device under test through the third resistor, and the sources of the second switch tube and the third switch tube and the drain of the fourth switch tube are used for connecting the device under test; wherein:
in the inductive charging stage, the first switch tube, the third switch tube and the fourth switch tube are connected, the bus capacitor charges the inductor, and when the stored energy of the inductor reaches a preset target stored energy, the first switch tube is disconnected, the diode is connected, and the connection among the device to be tested, the bus capacitor and the power supply is disconnected;
in the avalanche test phase, the fourth switch tube is turned off, the current flowing through the fourth switch tube is reduced and transferred to the device under test, so that the device under test is in an avalanche state until the current flowing through the third resistor is reduced to 0A, and in the process, when the device under test is in a breakdown short circuit or the avalanche voltage is abnormal, the third switch tube is turned off, the second switch tube and the fourth switch tube are turned on, so that the energy stored in the inductor is released through the first resistor and the device under test is short-circuited, wherein the first resistor serves as the discharge resistor.
3. The avalanche tolerance test circuit according to claim 2, further comprising a control circuit, wherein the control circuit is connected to the first switch tube, the second switch tube, the third switch tube and the fourth switch tube, and the control circuit is configured to control the first switch tube, the second switch tube, the third switch tube and the fourth switch tube to be turned on and off.
4. The avalanche tolerance test circuit of claim 3, wherein the control circuit is further connected to the second resistor, the third resistor, and the device under test, the control circuit further being configured to:
collecting the voltage of the second resistor, and controlling the first switching tube and the fourth switching tube to be disconnected when the voltage of the second resistor is greater than or equal to a preset first voltage threshold;
and collecting the voltage of the third resistor, and controlling the first switch tube to be disconnected with the third switch tube and the second switch tube to be connected with the fourth switch tube when the voltage of the third resistor is greater than or equal to a preset second voltage threshold value.
5. The avalanche tolerance test circuit according to claim 4, wherein the control circuit comprises a control chip and a first comparator, wherein a non-inverting input terminal of the first comparator is connected to the second resistor, an inverting input terminal and an output terminal of the first comparator are connected to the control chip, and the control chip is connected to the first switch tube, the second switch tube, the third switch tube and the fourth switch tube; wherein:
the first comparator is used for collecting the voltage of the second resistor and comparing the voltage of the second resistor with a preset first voltage threshold value;
the control chip is used for controlling the fourth switching tube to be switched off when the comparison result of the first comparator is that the voltage of the second resistor is greater than or equal to a preset first voltage threshold value.
6. The avalanche tolerance test circuit according to claim 5, wherein the control circuit further comprises a second comparator, a non-inverting input terminal of the second comparator is connected to the third resistor, an inverting input terminal and an output terminal of the second comparator are connected to the control chip, and the control chip is connected to the device under test; wherein:
the second comparator is used for collecting the voltage of the third resistor and comparing the voltage of the third resistor with a preset second voltage threshold value;
the control chip is used for controlling the device under test to be closed when the comparison result of the second comparator is that the voltage of the third resistor is greater than or equal to a preset second voltage threshold value.
7. The avalanche tolerance test circuit according to claim 2, wherein the inductance is a variable inductance and the first resistance is a variable resistance.
8. The avalanche tolerance test circuit of claim 2, wherein the second resistance and/or the third resistance is replaced with a shunt.
9. The avalanche capability test circuit of claim 2, wherein the diode is an IGBT replacement.
10. The avalanche tolerance test method is applied to an avalanche tolerance test circuit, and is characterized in that the avalanche tolerance test circuit comprises a power supply, a bus capacitor and a test circuit, wherein the power supply is connected with the bus capacitor, the bus capacitor is connected with the test circuit, the test circuit is used for connecting a device under test, the test circuit comprises an inductor, the grid driving voltage of the device under test is less than or equal to 0V, and the test of the device under test by the avalanche tolerance test circuit comprises a capacitor charging stage, an inductor charging stage and an avalanche test stage which are sequentially performed in time sequence;
the avalanche tolerance test method comprises the following steps:
the power supply charges the bus capacitor in the capacitor charging stage;
the bus capacitor charges the inductor in the inductor charging stage;
the test circuit is used for disconnecting the device under test from the power supply and the bus capacitor in the inductor charging stage and when the stored energy of the inductor reaches the preset target stored energy, enabling the device under test to be in an avalanche state in the avalanche test stage until the current flowing through the device under test is reduced to 0A, and in the process, when the device under test breaks down short circuit or the avalanche voltage is abnormal, the device under test is short-circuited and a discharge resistor is switched in to release the energy stored by the inductor.
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| CN202211398815.0A CN115902561A (en) | 2022-11-09 | 2022-11-09 | Avalanche tolerance test circuit and test method thereof |
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| CN202211398815.0A CN115902561A (en) | 2022-11-09 | 2022-11-09 | Avalanche tolerance test circuit and test method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117250386A (en) * | 2023-11-17 | 2023-12-19 | 深圳青铜剑技术有限公司 | Method and device for correcting delay of voltage and current probe of oscilloscope |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117250386A (en) * | 2023-11-17 | 2023-12-19 | 深圳青铜剑技术有限公司 | Method and device for correcting delay of voltage and current probe of oscilloscope |
| CN117250386B (en) * | 2023-11-17 | 2024-01-09 | 深圳青铜剑技术有限公司 | Method and device for correcting delay of voltage and current probe of oscilloscope |
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