CN115902561A - Avalanche endurance test circuit and test method thereof - Google Patents

Abstract

The present application provides an avalanche endurance test circuit and a test method thereof. Among them, the avalanche withstand test circuit includes a power supply, a bus capacitor and a test circuit connected to the device under test. The power supply is used to charge the bus capacitor during the capacitor charging phase, and the bus capacitor is used to charge the inductance in the test circuit during the inductor charging phase. , the test circuit is used to disconnect the device under test from the power supply and the bus capacitor during the inductance charging stage and when the energy storage of the inductance reaches the preset target energy storage, and to make the device under test in the avalanche test stage In the avalanche state, until the current flowing through the device under test is reduced to 0A, and during the process, when the device under test is broken down and short-circuited or the avalanche voltage is abnormal, short-circuit the device under test and connect the discharge resistor to release the energy stored in the inductor. The application realizes the failure protection of the device under test, so that the device under test subjected to the avalanche endurance test is effectively protected after failure, which is beneficial to the analysis of the device under test after failure.

Description

Avalanche endurance test circuit and test method thereof

【Technical field】

The present application relates to the technical field of power electronic device testing, in particular to an avalanche endurance test circuit and a test method thereof.

【Background technique】

Power semiconductor devices are mainly used for power conversion and circuit control of power electronic equipment. In practical applications, not only the main circuit has inductance, but also stray inductance is distributed inside. When the power semiconductor device is turned off, the release path of inductive energy will be Disconnect, so that the inductor generates a high voltage applied to the power semiconductor device that is turned off, and when the high voltage exceeds a certain value, the power semiconductor device will enter the state of avalanche breakdown. If the avalanche energy exceeds a certain value, then the power semiconductor device will will be completely damaged. It can be seen that the research on the avalanche tolerance of power semiconductor devices is very necessary, which is of great significance to the analysis of the reasons for the avalanche failure of power semiconductor devices and the optimization of the avalanche tolerance of power semiconductor devices from the circuit structure. It provides a reference basis for users to choose power semiconductor devices, and can also provide ideas for manufacturers to develop a new generation of power semiconductor devices with excellent avalanche withstand characteristics.

In related technologies, when testing power semiconductor devices through avalanche withstand test equipment, there are still many disadvantages in avalanche withstand test equipment, such as: the energy storage of the inductor cannot be quickly consumed, so that the power semiconductor device under test cannot be effectively protected after failure. It will even cause damage to the test equipment, which is not conducive to the analysis of power semiconductor devices after failure, and is not conducive to the effective protection of test equipment; it cannot achieve fast fault response, which is not conducive to the analysis of power semiconductor devices after failure, and is also not conducive to the protection of power semiconductor devices. Effective protection of test equipment; precise control of the inductor current within a single pulse cannot be achieved, that is to say, it is necessary to wait for a certain period of time to cool down the power semiconductor device before controlling the pulse time, and it is necessary to repeat the test of avalanche resistance for many times In order to make the inductor current gradually approach the target value.

Therefore, it is necessary to improve the circuit structure of the above-mentioned avalanche withstand test equipment.

【Content of invention】

The present application provides an avalanche withstand test circuit and a test method thereof, aiming at solving the problem in the related art that the power semiconductor devices subjected to the avalanche withstand test cannot be effectively protected after failure.

In order to solve the above technical problems, the first aspect of the embodiment of the present application provides an avalanche withstand test circuit, including a power supply, a bus capacitor and a test circuit. The power supply is connected to the bus capacitor, and the bus capacitor is connected to the test circuit. The test circuit is used to connect the The test device, the test circuit includes an inductor, the gate drive voltage of the device under test is less than or equal to 0V, and the test of the device under test by the avalanche withstand test circuit includes the capacitor charging stage, the inductor charging stage and the avalanche test stage in sequence. ;in:

The power supply is used to charge the bus capacitor during the capacitor charging phase;

The bus capacitor is used to charge the inductor during the charging phase of the inductor;

The test circuit is used to disconnect the device under test from the power supply and the bus capacitor during the charging phase of the inductor and when the energy storage of the inductor reaches the preset target energy storage, and to make the device under test in an avalanche during the avalanche test phase. state, until the current flowing through the device under test decreases to 0A, and during the process, when the device under test breaks down and short-circuits or the avalanche voltage is abnormal, short-circuit the device under test and connect the discharge resistor to release the energy stored in the inductor.

The second aspect of the embodiment of the present application provides an avalanche withstand test method, which is applied to an avalanche withstand test circuit. The avalanche withstand test circuit includes a power supply, a bus capacitor, and a test circuit. The power supply is connected to the bus capacitor, wherein the bus capacitor is connected to the test circuit. Circuit, the test circuit is used to connect the device under test, the test circuit includes an inductor, the gate drive voltage of the device under test is less than or equal to 0V, and the test of the device under test by the avalanche withstand test circuit includes the capacitor charging stage sequentially performed in sequence, Inductive charging stage and avalanche test stage; the avalanche endurance test method includes:

The power supply charges the bus capacitor during the capacitor charging phase;

The bus capacitor charges the inductor during the charging phase of the inductor;

The test circuit is in the inductance charging stage and when the energy storage of the inductance reaches the preset target energy storage, disconnect the device under test from the power supply and the bus capacitor, and make the device under test in an avalanche state during the avalanche test stage, Until the current flowing through the device under test decreases to 0A, and during the process, when the device under test breaks down and short-circuits or the avalanche voltage is abnormal, short-circuit the device under test and connect the discharge resistor to release the energy stored in the inductor.

As can be seen from the above description, compared with related technologies, the beneficial effects of the present application are:

The avalanche endurance test circuit is composed of the power supply, the bus capacitance and the test circuit, and the test of the device under test by the avalanche endurance test circuit is divided into a capacitor charging stage, an inductance charging stage and an avalanche test stage which are sequentially carried out in sequence. In practical applications, the power supply charges the busbar capacitor during the capacitor charging stage; the busbar capacitor charges the inductor during the inductor charging stage; the test circuit is in the inductor charging stage and when the energy storage of the inductor reaches the preset target energy storage, the Open the electrical connection between the device under test and the power supply and bus capacitance, and make the device under test in an avalanche state during the avalanche test until the current flowing through the device under test is reduced to 0A, and the device under test When the breakdown short circuit or avalanche voltage is abnormal, short circuit the device under test and connect the discharge resistor to release the energy stored in the inductor. It can be seen that during the avalanche withstand test of the device under test, when the device under test breaks down and is short-circuited or the avalanche voltage is abnormal (that is, when the device under test fails), the application can realize the short circuit of the device under test and connect the discharge The resistor releases the energy stored in the inductance, which realizes the failure protection of the device under test, so that the device under test subjected to the avalanche withstand test can be effectively protected after failure, which is beneficial to the analysis of the device under test after failure.

【Description of drawings】

In order to more clearly illustrate the related technologies or the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required in the description of the related technologies or the embodiments of the present application. Obviously, the accompanying drawings in the following description These are only some embodiments of the present application, not all embodiments. For those skilled in the art, other drawings can also be obtained according to these drawings without creative work.

Figure 1 is a schematic diagram of the principle of the traditional avalanche endurance test topology;

Fig. 2 is the modular block diagram of the avalanche endurance test circuit that the embodiment of the present application provides;

FIG. 3 is a schematic diagram of a circuit structure of an avalanche withstand test circuit provided in an embodiment of the present application;

FIG. 4 is a timing diagram of the avalanche endurance test circuit provided by the embodiment of the present application;

FIG. 5 is a schematic diagram of another circuit structure of the avalanche withstand test circuit provided by the embodiment of the present application;

Fig. 6 is a schematic flow chart of the avalanche endurance test method provided in the embodiment of the present application.

【Detailed ways】

In order to make the purpose, technical solutions and advantages of the application more obvious and easy to understand, the application will be clearly and completely described below in conjunction with the embodiments of the application and the corresponding drawings, wherein the same or similar symbols throughout represent the same or similar elements or elements having the same or similar functions. It should be understood that the various embodiments of the application described below are only used to explain the application, and are not intended to limit the application, that is, based on the various embodiments of the application, those skilled in the art will not make any inventive step All other embodiments obtained under the premise of labor all belong to the scope of protection of this application. In addition, the technical features involved in the various embodiments of the present application described below may be combined with each other as long as they do not constitute a conflict with each other.

Figure 1 is a schematic diagram of the principle of a traditional avalanche endurance test topology. The test process of the traditional avalanche withstand test topology includes two stages. In the first stage, the switch tube Q1 and the device under test DUT are turned on, and the power supply VDD, switch tube Q1, inductor L and the device under test DUT form a power loop (1), The power supply VDD charges the inductor L, the current of the inductor L increases linearly, and the current of the inductor L depends on the time when the switch tube Q1 and the device under test DUT are turned on; the second stage is that the switch tube Q1 and the device under test DUT are turned off, The diode, the device under test DUT and the inductor L form a power loop (2), and at this time the device under test DUT enters an avalanche state. There are some disadvantages in the traditional avalanche withstand test topology, for example: first, when the device under test DUT is short-circuited, the energy stored in the inductor L will be consumed by the diode, the device under test DUT, the resistance of the inductor L and the loop resistance, which will lead to energy consumption requiring A longer time will aggravate the damage of the DUT under test, which is not conducive to the analysis after the DUT of the DUT fails; secondly, when the DUT of the DUT is open, a very high voltage will appear at both ends, which is the limit of the avalanche tolerance. The measuring instrument brings a great risk of damage; third, the inductance value of the inductance L is unstable during the avalanche withstand measurement process, so real-time sampling is required to control the current of the inductance L, and the delay is relatively large, resulting in the inductance current The control accuracy is poor.

To this end, the embodiment of the present application provides an avalanche withstand test circuit, the module block diagram of the avalanche withstand test circuit is shown in Figure 2, the avalanche withstand test circuit includes a power supply VCC, a bus capacitor C1 and a test circuit, wherein the power supply VCC Connected to the bus capacitor C1, the bus capacitor C1 is connected to the test circuit, the test circuit is used to connect the device under test DUT, the test circuit includes inductor L1, the gate drive voltage of the device under test DUT is less than or equal to 0V, the avalanche withstand test circuit is The test of the device under test DUT includes the capacitor charging stage, the inductor charging stage and the avalanche test stage which are sequentially carried out in sequence. It should be noted that the embodiment of the present application has no special requirements on the power supply VCC and the bus capacitor C1, and the power supply VCC that satisfies the specified parameters (such as output voltage, voltage output accuracy, etc.) can be selected according to the needs of practical applications, and can be selected according to The sag rate of the bus voltage is used to calculate the capacity of the bus capacitor C1, and it is better for the application to choose a capacitor with low stray inductance.

Specifically, the power supply VCC is used to charge the bus capacitor C1 in the capacitor charging phase; the bus capacitor C1 is used to charge the inductor L1 in the inductor charging phase; the test circuit is used in the inductor charging phase and when the energy storage of the inductor L1 reaches When the preset target energy is stored, disconnect the DUT from the power supply VCC and the bus capacitor C1, and make the DUT in the avalanche state during the avalanche test until the current flowing through the DUT decreases. As small as 0A, and during this process, when the device under test is short-circuited or the avalanche voltage is abnormal, the device under test DUT is short-circuited and a discharge resistor is connected to release the energy stored in the inductor L1. Wherein, since the capacity of the bus capacitor C1 is large enough, the bus voltage can be well maintained during the charging phase of the inductor.

It can be understood that since the capacitor charging stage, the inductor charging stage and the avalanche test stage are sequentially performed sequentially, in practical applications, the capacitor charging stage is performed first, that is, the bus capacitor C1 is charged through the power supply VCC; after that, the Inductor charging phase, that is, to charge the inductor L1 through the bus capacitor C1 (at this time, the bus capacitor C1 has been charged), and when the energy storage of the inductor L1 reaches the preset target energy storage, the test circuit will disconnect the device under test The connection between the DUT and the power supply VCC and the bus capacitor C1 means that the device under test DUT is about to enter the avalanche state; finally, the avalanche test stage is carried out, that is, the test circuit is used to make the device under test DUT officially enter the avalanche state until the flow through the The current of the DUT under test is reduced to 0A, and during this process, when the DUT under test is short-circuited or the avalanche voltage is abnormal, the test circuit will short-circuit the DUT under test and connect the discharge resistor to release the energy stored in the inductor L1 .

It can be seen from the above that during the avalanche withstand test of the device under test DUT, when the device under test DUT is broken down and short-circuited or the avalanche voltage is abnormal (that is, when the device under test DUT fails), the embodiment of the present application can realize the short-circuit tested The device DUT is connected to the discharge resistor to release the energy stored in the inductance L1, which realizes the failure protection of the device under test DUT, so that the DUT of the device under test for the avalanche withstand test can be effectively protected after failure, which is beneficial to the device under test. Analysis after DUT failure.

In some implementation manners, please refer to FIG. 3 , which is a schematic circuit structure diagram of an avalanche withstand test circuit provided in an embodiment of the present application. In addition to the inductor L1, the test circuit also includes a first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a first resistor R1, a second resistor R2, a third resistor R3 and a diode D1, wherein the first resistor R1 is used as the discharge resistor mentioned above, one end of the bus capacitor C1 is connected to the drain of the first switching tube Q1, the other end is connected to the anode of the diode D1, the source of the first switching tube Q1, the diode The cathode of D1 is connected to one end of the inductor L1, the other end of the inductor L1 is connected to one end of the first resistor R1 and the drain of the third switching tube Q3, the other end of the first resistor R1 is connected to the drain of the second switching tube Q2, and the second switch The sources of the tube Q2 and the third switching tube Q3 are connected to the drain of the fourth switching tube Q4, the source of the fourth switching tube Q4 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is used for the anode of the diode D1. The device under test DUT is connected through the third resistor R3, the sources of the second switch Q2 and the third switch Q3, and the drain of the fourth switch Q4 are used to connect the device under test DUT.

Specifically, in the inductor charging stage, the first switch Q1, the third switch Q3 and the fourth switch Q4 are turned on, the bus capacitor C1 charges the inductor L1, and when the energy storage of the inductor L1 reaches the preset target When storing energy (equivalent to the current of the second resistor R2 reaching the preset target current), the first switch tube Q1 is turned off, the diode D1 is turned on, and the connection between the device under test DUT and the bus capacitor C1 and the power supply VCC is disconnected , that is, the device under test DUT is about to enter an avalanche state. During the avalanche period, the fourth switch tube Q4 is turned off, and the current flowing through the fourth switch tube Q4 decreases rapidly and is transferred to the device under test DUT. At the same time, since the gate drive voltage of the device under test DUT is less than or equal to 0V, The device under test DUT officially enters the avalanche state until the current flowing through the third resistor R3 decreases to 0A, and during this process, when the device under test DUT breaks down and short-circuits or the avalanche voltage is abnormal, the third switch tube Q3 is disconnected , the second switching tube Q2 and the fourth switching tube Q4 are quickly turned on, so as to release the energy stored in the inductor L1 through the first resistor R1 and short-circuit the device under test DUT. Preferably, the inductor L1 is a variable inductor, and the first resistor R1 is a variable resistor.

It should be noted that the first switching tube Q1, the second switching tube Q2, the third switching tube Q3 and the fourth switching tube Q4 can all be power switching tubes or mechanical switching tubes, such as IGBT (Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor, polar transistors), relays, etc. The diode D1 can be a freewheeling diode D1, or can be replaced by a power switch tube or a mechanical switch tube. Both the second resistor R2 and the third resistor R3 may be sampling resistors, or may be replaced by shunts.

In some embodiments, still referring to FIG. 2, the avalanche withstand test circuit described above includes a control circuit in addition to the power supply VCC, the bus capacitor C1 and the test circuit. The control circuit is connected to the first switching tube Q1, the second The switching tube Q2, the third switching tube Q3 and the fourth switching tube Q4 are used to control the conduction of the first switching tube Q1, the second switching tube Q2, the third switching tube Q3 and the fourth switching tube Q4 through the control circuit with disconnect. Wherein, the control circuit can control the conduction and disconnection of the first switching tube Q1, the second switching tube Q2, the third switching tube Q3 and the fourth switching tube Q4 through the driver (U1, U2, U3, U4 in FIG. 2 Corresponding to the drivers of the first switching tube Q1, the second switching tube Q2, the third switching tube Q3 and the fourth switching tube Q4), that is, outputting the drive signal to the corresponding driver to drive the corresponding switching tube, thereby realizing the corresponding switching tube on and off.

Further, the control circuit is also connected to the second resistor R2, the third resistor R3 and the device under test DUT. In this case, the control circuit is used to: collect the voltage of the second resistor R2, and when the voltage of the second resistor R2 is greater than or equal to the preset first voltage threshold, control the first switching tube Q1 and the fourth switching tube Q4 to disconnect; collect the voltage of the third resistor R3, and when the voltage of the third resistor R3 is greater than or equal to the preset second When the voltage threshold is reached, the first switching tube Q1 and the third switching tube Q3 are controlled to be disconnected, and the second switching tube Q2 and the fourth switching tube Q4 are turned on; such setting can control the inductor current more quickly and accurately. Among them, the control circuit can control the opening and closing of the device under test DUT through the driver (U5 in Figure 2 corresponds to the driver of the DUT under test), that is, output the driving signal to the driver of the DUT under test to drive the device under test DUT , so as to realize the opening and closing of the device under test DUT.

As one of the implementation manners, still referring to FIG. 2, the control circuit includes a control chip XP and a first comparator COMP1, wherein the non-inverting input terminal of the first comparator COMP1 is connected to the second resistor R2, and the first comparator COMP1 The inverting input terminal and the output terminal are connected to the control chip XP, and the control chip XP is connected to the first switch tube Q1 , the second switch tube Q2 , the third switch tube Q3 and the fourth switch tube Q4 . Specifically, the first comparator COMP1 is used to collect the voltage of the second resistor R2, and compare the voltage of the second resistor R2 with the preset first voltage threshold; the control chip XP is used for comparison in the first comparator COMP1 As a result, when the voltage of the second resistor R2 is greater than or equal to the preset first voltage threshold, the first switching tube Q1 and the fourth switching tube Q4 are controlled to be disconnected.

In this embodiment, the control chip XP can output the first voltage threshold to the first comparator COMP1 according to the setting of the user, and then the first comparator COMP1 collects the voltage on the second resistor R2 (it can also be sampled after voltage division), When the current flowing through the second resistor R2 reaches the preset target value, the sampling voltage of the second resistor R2 is just greater than the first voltage threshold, so that the level of the first comparator COMP1 is reversed (that is, the level of the first comparator COMP1 The result of the comparison is that the voltage of the second resistor R2 is greater than or equal to the first voltage threshold), and a level inversion signal is generated to the control chip XP, and the control chip XP outputs a driving signal to the first switch tube Q1 after receiving the level inversion signal and the fourth switching tube Q4 to control the disconnection of the first switching tube Q1 and the fourth switching tube Q4.

As another implementation mode, still referring to FIG. 2, the control circuit includes a second comparator COMP2 in addition to the control chip XP and the first comparator COMP1, and the non-inverting input terminal of the second comparator COMP2 is connected to the third The resistor R3, the inverting input terminal and the output terminal of the second comparator COMP2 are connected to the control chip XP, and the control chip XP is connected to the device under test DUT. Specifically, the second comparator COMP2 is used to collect the voltage of the third resistor R3, and compare the voltage of the third resistor R3 with the preset second voltage threshold; the control chip XP is used for comparison in the second comparator COMP2 As a result, when the voltage of the third resistor R3 is greater than or equal to the preset second voltage threshold, the first switch Q1 and the third switch Q3 are controlled to be disconnected, and the second switch Q2 and the fourth switch Q4 are turned on.

In this embodiment, the control chip XP can output the second voltage threshold to the second comparator COMP2 according to the setting of the user, and then the second comparator COMP2 collects the voltage on the third resistor R3 (it can also be sampled after voltage division), When the current flowing through the third resistor R3 reaches the preset target value, the sampling voltage of the third resistor R3 is just greater than the second voltage threshold, so that the level of the second comparator COMP2 is reversed (that is, the voltage of the second comparator COMP2 The comparison result is that the voltage of the third resistor R3 is greater than or equal to the second voltage threshold), and generates a level inversion signal to the control chip XP, and the control chip XP outputs a driving signal to the first switch tube Q1 after receiving the level inversion signal , the second switching tube Q2, the third switching tube Q3 and the fourth switching tube Q4, so as to control the disconnection of the first switching tube Q1 and the third switching tube Q3, and the conduction of the second switching tube Q2 and the fourth switching tube Q4.

It should be noted that the above-mentioned implementation mode is only a preferred implementation of the embodiment of the application, and it is not the only limitation on the specific circuit structure and control logic of the test circuit and the control circuit; in this regard, those skilled in the art can implement On the basis of examples, it can be flexibly set according to actual application scenarios.

To sum up, the embodiment of the present application provides an avalanche endurance test circuit, the avalanche endurance test circuit realizes the failure protection of the device under test DUT, so that the device under test DUT performing the avalanche endurance test can be effectively recovered after failure. The protection is beneficial to the analysis after the failure of the device under test (DUT), and at the same time, it can realize faster and more accurate control of the inductor current, which meets the requirements of avalanche tolerance measurement accuracy. The timing diagram of the avalanche withstand test circuit can be referred to FIG. 4. In FIG. 4, Q4_PWM represents the drive signal output from the control chip XP to the fourth switching tube Q4, IL represents the current of the inductor L1, and I_R3 represents the current of the third resistor R3. V_DUT represents the voltage of the device under test DUT. In addition, if the measurement accuracy of the avalanche energy is not considered, or the driving of the device under test DUT is not considered, then the circuit structure of the avalanche withstand test circuit can be simplified as shown in FIG. 5 .

Fig. 6 is a schematic flow chart of the avalanche endurance test method provided in the embodiment of the present application. The embodiment of the present application also provides an avalanche endurance test method, which is implemented based on the aforementioned avalanche endurance test circuit, and the avalanche endurance test method includes the following steps 601 to 603 .

Step 601, the power supply charges the bus capacitor in the capacitor charging stage.

In the embodiment of this application, the test of the DUT avalanche tolerance of the device under test is divided into three stages, namely the capacitor charging stage, the inductor charging stage and the avalanche test stage, and the capacitor charging stage, the inductor charging stage and the avalanche test stage It is carried out sequentially in sequence, so the capacitor charging stage needs to be carried out first, that is, the bus capacitor C1 is charged through the power supply VCC.

Step 602, the bus capacitor charges the inductor during the charging phase of the inductor.

In the embodiment of this application, after the capacitor charging phase is over, the inductor charging phase is required, that is, the inductor L1 is charged through the bus capacitor C1, and when the energy storage of the inductor L1 reaches the preset target energy storage, the test circuit The connection between the device under test DUT and the power supply VCC and bus capacitor C1 will be disconnected, which means that the device under test DUT is about to enter an avalanche state.

Step 603, the test circuit is in the inductance charging stage and when the energy storage of the inductance reaches the preset target energy storage, disconnect the connection between the device under test and the power supply and the bus capacitor, and make the device under test in the avalanche test stage. In the avalanche state, until the current flowing through the device under test is reduced to 0A, and during the process, when the device under test is broken down and short-circuited or the avalanche voltage is abnormal, short-circuit the device under test and connect the discharge resistor to release the energy stored in the inductor.

In the embodiment of this application, after the inductance charging stage is over, the avalanche test stage is required, that is, the device under test DUT officially enters the avalanche state through the test circuit until the current flowing through the device under test DUT is reduced to 0A. And during this process, when the device under test DUT is broken down and short-circuited or the avalanche voltage is abnormal, the test circuit will short-circuit the device under test DUT and connect the discharge resistor to release the energy stored in the inductor L1.

It can be seen from the above that during the avalanche withstand test of the device under test DUT, when the device under test DUT is broken down and short-circuited or the avalanche voltage is abnormal (that is, when the device under test DUT fails), the avalanche withstand test method can realize the short circuit The device under test DUT is connected to the discharge resistor to release the energy stored in the inductor L1, which realizes the failure protection of the device under test DUT, so that the DUT under test for the avalanche withstand test can be effectively protected after failure, which is beneficial to the tested device. Analysis after device DUT failure.

It should be noted that each embodiment in the content of this application is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment refer to each other That's it. As for the product embodiment, since it is similar to the method embodiment, the description is relatively simple, and for the related parts, please refer to the description of the method embodiment.

It should also be noted that in the content of this application, relative terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations, any such actual relationship or order exists. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

The above description of the disclosed embodiments enables those skilled in the art to implement or use the contents of the application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined in the content of the application can be used in other embodiments without departing from the spirit or scope of the content of the application. accomplish. Therefore, the content of the application will not be limited to the embodiments shown in the content of the application, but will conform to the broadest scope consistent with the principles and novel features disclosed in the content of the application.

Claims (10)

1. An avalanche withstand test circuit, characterized in that, comprises a power supply, a bus capacitor and a test circuit, the power supply is connected to the bus capacitor, the bus capacitor is connected to the test circuit, and the test circuit is used to connect The device under test, the test circuit includes an inductor, the gate drive voltage of the device under test is less than or equal to 0V, and the test of the device under test by the avalanche withstand test circuit includes a capacitor charging stage that is sequentially performed in sequence , inductance charging stage and avalanche test stage; where: The power supply is used to charge the bus capacitor during the capacitor charging phase; The bus capacitor is used to charge the inductor during the charging phase of the inductor; The test circuit is used to disconnect the device under test from the power supply and the bus capacitor when the energy storage of the inductance reaches a preset target energy storage during the charging phase of the inductance , and in the avalanche test stage, the device under test is in an avalanche state until the current flowing through the device under test is reduced to 0A, and during the process, when the device under test breaks down and short circuit or the avalanche voltage is abnormal When , short-circuit the device under test and connect a discharge resistor to release the energy stored in the inductance. 2. The avalanche withstand test circuit according to claim 1, wherein the test circuit also includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a first resistor, a second switch tube, and a second switch tube. resistor, a third resistor and a diode, one end of the bus capacitor is connected to the drain of the first switch tube, the other end is connected to the anode of the diode, the source of the first switch tube, the cathode of the diode connected to one end of the inductor, the other end of the inductor is connected to one end of the first resistor and the drain of the third switch tube, and the other end of the first resistor is connected to the drain of the second switch tube, The sources of the second switching tube and the third switching tube are connected to the drain of the fourth switching tube, the source of the fourth switching tube is connected to one end of the second resistor, and the second The other end of the resistor and the anode of the diode are used to connect the device under test through the third resistor, the sources of the second switching tube and the third switching tube, and the drain of the fourth switching tube Used to connect the device under test; where: During the charging phase of the inductor, the first switch tube, the third switch tube, and the fourth switch tube are turned on, the bus capacitor charges the inductor, and when the energy stored in the inductor When the preset target energy storage is reached, the first switching tube is turned off, the diode is turned on, and the device under test is disconnected from the bus capacitor and the power supply; During the avalanche test phase, the fourth switch tube is turned off, and the current flowing through the fourth switch tube is reduced and transferred to the device under test, so that the device under test is in an avalanche state until it flows through The current of the third resistor is reduced to 0A, and during the process, when the device under test is broken down and short-circuited or the avalanche voltage is abnormal, the third switch tube is turned off, and the second switch tube and the first switch tube are turned off. The four switches are turned on to release the energy stored in the inductor through the first resistor and short-circuit the device under test, wherein the first resistor is used as the discharge resistor. 3. The avalanche withstand test circuit according to claim 2, further comprising a control circuit, the control circuit is connected to the first switching tube, the second switching tube, the third switching tube and the For the fourth switch tube, the control circuit is used to control the conduction and disconnection of the first switch tube, the second switch tube, the third switch tube, and the fourth switch tube. 4. The avalanche withstand test circuit according to claim 3, wherein the control circuit is also connected to the second resistor, the third resistor and the device under test, and the control circuit is also used for : Collecting the voltage of the second resistor, and controlling the first switching tube to disconnect from the fourth switching tube when the voltage of the second resistor is greater than or equal to a preset first voltage threshold; Collect the voltage of the third resistor, and when the voltage of the third resistor is greater than or equal to a preset second voltage threshold, control the first switch tube to disconnect from the third switch tube, and the first switch tube to be disconnected from the third switch tube. The second switch tube is connected to the fourth switch tube. 5. The avalanche withstand test circuit according to claim 4, wherein the control circuit comprises a control chip and a first comparator, wherein the non-inverting input of the first comparator is connected to the second resistor , the inverting input terminal and the output terminal of the first comparator are connected to the control chip, and the control chip is connected to the first switch tube, the second switch tube, the third switch tube and the The fourth switching tube; wherein: The first comparator is used to collect the voltage of the second resistor, and compare the voltage of the second resistor with a preset first voltage threshold; The control chip is configured to control the fourth switching tube to turn off when the comparison result of the first comparator is that the voltage of the second resistor is greater than or equal to a preset first voltage threshold. 6. The avalanche withstand test circuit according to claim 5, wherein the control circuit further comprises a second comparator, the non-inverting input end of the second comparator is connected to the third resistor, and the first The inverting input and output ends of the two comparators are connected to the control chip, and the control chip is connected to the device under test; wherein: The second comparator is used to collect the voltage of the third resistor, and compare the voltage of the third resistor with a preset second voltage threshold; The control chip is configured to control the device under test to turn off when the comparison result of the second comparator is that the voltage of the third resistor is greater than or equal to a preset second voltage threshold. 7. The avalanche withstand test circuit according to claim 2, wherein the inductance is a variable inductance, and the first resistor is a variable resistor. 8. The avalanche withstand test circuit according to claim 2, wherein the second resistor and/or the third resistor is replaced by a shunt. 9. The avalanche withstand test circuit according to claim 2, wherein the diode is replaced by an IGBT. 10. An avalanche tolerance test method, applied to an avalanche tolerance test circuit, characterized in that the avalanche tolerance test circuit includes a power supply, a bus capacitor and a test circuit, the power supply is connected to the bus capacitor, wherein the bus The capacitor is connected to the test circuit, the test circuit is used to connect the device under test, the test circuit includes an inductor, the gate drive voltage of the device under test is less than or equal to 0V, and the avalanche withstand test circuit is for the The test of the device under test includes the capacitor charging stage, the inductor charging stage and the avalanche test stage in sequence; The avalanche endurance test method includes: The power supply charges the bus capacitor during the capacitor charging phase; The bus capacitor charges the inductor during the charging phase of the inductor; The test circuit disconnects the connection between the device under test and the power supply and the bus capacitor when the energy storage of the inductance reaches a preset target energy storage during the charging phase of the inductance, and In the avalanche test phase, the device under test is in an avalanche state until the current flowing through the device under test is reduced to 0A, and during the process, when the device under test breaks down or has an abnormal avalanche voltage, The device under test is short-circuited and a discharge resistor is connected to discharge the energy stored in the inductance.

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