CN115754654A - Power device driving circuit, semiconductor device testing circuit and system - Google Patents
Power device driving circuit, semiconductor device testing circuit and system Download PDFInfo
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- CN115754654A CN115754654A CN202211438243.4A CN202211438243A CN115754654A CN 115754654 A CN115754654 A CN 115754654A CN 202211438243 A CN202211438243 A CN 202211438243A CN 115754654 A CN115754654 A CN 115754654A
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- 238000012360 testing method Methods 0.000 title claims abstract description 95
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000012545 processing Methods 0.000 claims abstract description 12
- 239000003990 capacitor Substances 0.000 claims description 33
- 238000004804 winding Methods 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 17
- 238000007599 discharging Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 13
- 230000032683 aging Effects 0.000 description 5
- 229910002601 GaN Inorganic materials 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
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- 238000004146 energy storage Methods 0.000 description 1
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- 238000011056 performance test Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention relates to a power device driving circuit, a semiconductor device testing circuit and a system. Wherein the power device driving circuit includes: a signal source for generating an initial driving signal; and the buffer circuit is used for receiving the initial driving signal, carrying out time delay processing on the initial driving signal and outputting a time-delayed gate driving signal based on the testing working condition of the power device to be tested, wherein the gate driving signal is used for controlling the power device to be tested to be switched on when the drain-source voltage of the power device to be tested oscillates to the valley bottom. By the scheme of the invention, the drive signal of the power device to be tested can be subjected to time delay adjustment, so that the power device to be tested can be switched on when the drain-source voltage of the power device to be tested oscillates to the valley bottom, and the application requirement of the power device is met.
Description
Technical Field
The present invention relates generally to the field of semiconductor device technology. More particularly, the present invention relates to a power device driving circuit, a semiconductor device testing circuit, and a semiconductor device testing system.
Background
In recent years, the market demand of mobile phone fast charging adapters adopting power devices such as gallium nitride power transistors is increasing, and particularly, the gallium nitride adapters based on flyback circuits are widely applied. In order to ensure the reliability of the product, it is usually necessary to perform performance tests such as aging on the corresponding power devices used by the adapter. In the related art, a mode of simulating the working condition of a flyback circuit is adopted to test a power device. However, in practical application, due to the fact that a nonlinear device (such as a transformer leakage inductance and a switch tube parasitic capacitance) in the test circuit has deviation, the power device to be tested is turned on when the voltage of the drain-source electrode of the power device to be tested does not resonate to the valley bottom, the working condition of the analog circuit is separated from the actual working condition of the power device to be tested, and therefore the test result is inaccurate.
Disclosure of Invention
In order to solve the technical problems described in the background art, the invention provides a power device driving circuit, which can make a to-be-tested power device turn on when the drain-source voltage of the to-be-tested power device oscillates to the valley bottom by performing delay adjustment on an initial driving signal of the to-be-tested power device, so as to meet the application requirements on the power device.
In view of this, the present invention provides solutions in the following aspects.
A first aspect of the present invention provides a power device driving circuit, including: a signal source for generating an initial driving signal; and the buffer circuit is used for receiving the initial driving signal, carrying out time delay processing on the initial driving signal and outputting a gate driving signal subjected to time delay processing based on the testing working condition of the power device to be tested, wherein the gate driving signal is used for controlling the power device to be tested to be switched on when the drain-source voltage of the power device to be tested oscillates to the valley bottom.
The second aspect of the present invention provides a semiconductor device test circuit, including a primary circuit and a secondary circuit, where the primary circuit includes a primary winding and a primary power device to be tested, which are connected in series, two ends of the primary circuit are used to connect a test power supply to form a loop, the secondary circuit includes a secondary winding and a secondary transistor to be tested, which are connected in series, the primary winding and the secondary winding form a flyback transformer, the primary circuit and the secondary circuit are connected in parallel and are grounded, and the primary circuit further includes: the first power device driving circuit is connected to the primary side power device to be tested, and includes the power device driving circuit according to the first invention and the following embodiments, wherein a buffer circuit in the power device driving circuit is configured to process an initial driving signal according to a test condition of the primary side power device to be tested, and output a first gate driving signal for the primary side power device to be tested, so as to control the primary side power device to be tested to be turned on when a source-drain voltage of the primary side power device to be tested oscillates to a valley bottom based on the first gate driving signal.
The invention provides a semiconductor device test system, which comprises a plurality of primary circuits and secondary circuits, wherein each primary circuit comprises a primary winding and a primary power device to be tested which are connected in series, two ends of each primary circuit are used for being connected with a test power supply to form a loop, each secondary circuit comprises a secondary winding and a secondary transistor to be tested which are connected in series, each primary winding and each secondary winding form a flyback transformer, and each primary circuit and each secondary circuit are connected in parallel and grounded; each primary side circuit also comprises a first power device driving circuit which is connected to the primary side power device to be tested; and/or the secondary side transistor to be tested comprises a secondary side power device to be tested, and each secondary side circuit also comprises a second power device driving circuit connected to the secondary side power device to be tested; the first power device driving circuit and/or the second power device driving circuit comprise power device driving circuits according to a first aspect of the present invention and a plurality of embodiments described below, and a plurality of the power device driving circuits generate a same initial driving signal based on a signal source thereof, wherein each of the power device driving circuits is configured to process the initial driving signal according to a test condition of a primary power device to be tested or a secondary power device to be tested corresponding thereto to obtain a gate driving signal, and output a corresponding gate driving signal to the primary power device to be tested or the secondary power device to be tested corresponding thereto, so as to control the primary power device to be tested corresponding thereto to be turned on when a drain-source voltage of the primary power device to be tested oscillates to a valley bottom based on the corresponding gate driving signal, or control the secondary power device to be tested corresponding thereto to be turned on when a drain-source voltage of the secondary power device to be tested oscillates to the valley bottom based on the corresponding gate driving signal.
By utilizing the scheme provided by the invention, the initial driving signal of the power device to be tested is subjected to time delay processing based on the buffer circuit in the power device driving circuit, so that the power device to be tested can be switched on when the drain-source voltage of the power device to be tested oscillates to the valley bottom, and the application requirement of the power device is met. In some embodiments, the power device driving circuit can be applied to a semiconductor device test circuit to ensure that the working condition of a simulation circuit of a power device accords with the actual working condition, so that the test accuracy is improved. In addition, in still other embodiments, the power device driving circuit may be applied to a semiconductor device testing system to overcome the problem of inconsistent testing conditions and power consumption of the tested power devices in the batch testing process, thereby effectively ensuring consistent working conditions of each tested power device in the semiconductor device testing system.
Drawings
The above and other objects, features and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings. Several embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:
fig. 1 is a block diagram showing a power device driving circuit according to a first embodiment of the present invention;
fig. 2 is a block diagram showing a power device driving circuit according to a second embodiment of the present invention;
fig. 3 is a block diagram showing a power device driving circuit according to a third embodiment of the present invention;
fig. 4 is a structural diagram showing a power device driving circuit according to a fourth embodiment of the present invention;
fig. 5 is a structural diagram showing a power device driving circuit according to a fifth embodiment of the present invention;
FIG. 6 is a block diagram showing a semiconductor device test circuit according to an embodiment of the present invention; and
fig. 7 is a block diagram illustrating a semiconductor device test system according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making creative efforts based on the embodiments of the present invention, belong to the protection scope of the present invention.
It should be understood that the terms "first", "second", "third" and "fourth", etc. in the claims, the description and the drawings of the present invention are used for distinguishing different objects and are not used for describing a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification and claims of this application, the singular form of "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this specification refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.
The inventor finds that, for power devices such as a gallium nitride power transistor, a driving signal is usually used to directly trigger the power device to be turned on or off. However, with the wide application of power devices such as gan power transistors, the power devices are required to operate under corresponding working conditions. Particularly, for a batch test circuit system based on a flyback circuit and energy feedback, a power device to be tested in the system needs to work under the working condition of the flyback circuit, and at the moment, the power device to be tested needs to be turned on when the drain-source voltage of the power device meets the lowest resonance voltage (namely valley voltage). However, in practical applications, due to deviations (for example, transformer leakage inductance deviations and the like) of some non-linear devices in the flyback circuit, the source-drain voltage resonance periods of the power device to be tested may be different, so that the turn-on condition of the power device to be tested (for example, the drain-source voltage of the power device to be tested is not resonated to the valley, that is, turned on) does not meet the application requirements. For this reason, the inventor also finds that the application requirements of the power device can be met by adjusting the driving signal of the power device so that the driving signal can timely trigger the power device to be turned on.
The following detailed description of embodiments of the invention refers to the accompanying drawings.
Fig. 1 is a block diagram illustrating a power device driving circuit 100 according to an embodiment of the present invention. As shown in fig. 1, the power device driving circuit 100 may include a buffer circuit 101 and a signal source 102. Meanwhile, in order to more clearly illustrate the operation principle of the power device driving circuit 100, a power device 103 to be tested is also shown in fig. 1.
Wherein the aforementioned signal source may be used for generating the initial driving signal. In some embodiments, the signal source may specifically include a signal generator or a pulse generating circuit, etc. In particular, the initial driving signal may be generated by a signal generator or a pulse generation circuit, and in some implementation scenarios, the initial driving signal may include a high-low level at which a duty cycle may be set. It should be noted that the detailed description of the initial driving signal is only an exemplary description.
The buffer circuit 101 may receive the initial driving signal, and may perform a delay process on the initial driving signal and output a gate driving signal after the delay process based on a test condition of the power device to be tested. The grid driving signal can be used for controlling the power device to be tested to be switched on when the drain-source electrode voltage of the power device to be tested oscillates to the valley bottom. Therefore, the initial driving signal can be subjected to time delay processing through the buffer circuit based on the testing working condition of the power device to be tested, and the turn-on time point of the power device to be tested is adjusted, so that the adjusted driving signal can trigger the power device to be turned on in time to meet the application requirement of the power device. It should be noted that the aforementioned power device may include a gallium nitride power device, a silicon carbide power device, or other power devices, and the specific type of the power device is not limited herein.
In some embodiments, the aforementioned power device driving circuit may further include a driver. The driver may receive the gate driving signal output from the buffer circuit 101 and output the gate driving signal to the power device under test.
The foregoing buffer circuit 101 may be implemented in various ways in specific applications, which are further described below with reference to fig. 2 to 5.
Fig. 2 is a block diagram illustrating a power device driving circuit 200 according to another embodiment of the present invention. It is understood that fig. 2 is a specific implementation of the power device driving circuit 100 of fig. 1. The same applies, therefore, to fig. 2 as described above in connection with the relevant details in fig. 1. For example, the initial drive signal in fig. 2 may be generated by a signal generator or pulse generation circuit. In addition, the driver 104 is also shown in the power driving circuit 200, and the driver 104 can be deleted or reserved according to the actual application requirement.
Referring specifically to fig. 2, the power device driving circuit 200 may include a buffer circuit 101 and a signal source 102. The buffer circuit 101 may include a first RC buffer circuit, and the first RC buffer circuit may perform delay adjustment on the initial driving signal by using a charging and discharging process of a capacitor therein. Specifically, in some embodiments, the first RC snubber circuit may include a first resistor R1 and a first capacitance C1. One end of the first capacitor C1 is connected to the first resistor R1, and the other end of the first capacitor C1 is grounded. The initial driving signal charges the first capacitor C1 after passing through the first resistor R1. For the subsequent circuits of the first capacitor C1, the initial driving signal is adjusted by the charging and discharging time of the first capacitor C1 to obtain the gate driving signal. The gate driving signal may be directly output to the power device under test 103 or output to the power device under test 103 via the driver 104.
Further, in some embodiments, the first resistor may include a fixed resistor, and specifically, the required fixed resistor may be determined according to application requirements of the device to be driven, and the power device driving circuit 200 is adaptively adjusted by exchanging fixed resistors with different resistance values to meet the application requirements.
For another example, in other embodiments, the first resistor may further comprise an adjustable resistor. Under the scene, the resistance of the adjustable resistor can be directly adjusted according to application requirements, and complicated replacement operation of the resistor is not needed. For example, the drain-source voltage when the power device to be driven is switched on can be adjusted and controlled based on the resistance value of the adjustable resistor. In practical application, the resistance value can be adjusted by matching with an oscilloscope. Specifically, in the process of adjusting the resistance value of the adjustable resistor, the switching-on condition of the power device to be driven can be detected through the oscilloscope until the oscilloscope detects that the power device to be driven is switched on when the drain-source voltage of the power device to be driven is at the bottom of the valley, and at the moment, the adjustment of the resistance value is stopped. It should be noted that the description of the resistance value adjustment process of the adjustable resistor is only an exemplary description, and the scheme of the present invention is not limited thereto.
Fig. 3 is a block diagram illustrating a power device driving circuit 300 according to still another embodiment of the present invention. It will be appreciated that fig. 3 is another specific implementation of the power device driver circuit 100 of fig. 1. Fig. 3 may also be understood as a further addition to the functionality of the power device driver circuit 200 of fig. 2. The same applies, therefore, to fig. 3 as described above in connection with the relevant details in fig. 1 and 2. For example, the initial drive signal in fig. 3 may be generated by a signal generator or pulse generation circuit. In addition, the driver 104 is also shown in the power driving circuit 300, and the driver 104 can be deleted or reserved according to the actual application requirement. .
Referring specifically to fig. 3, the power device driving circuit 300 may include a buffer circuit 101 and a signal source 102. The buffer circuit comprises a second RC buffer circuit and a first logic gate adjusting circuit. The second RC snubber circuit includes a second resistor R2 and a second capacitor C2, and it is understood that the second RC snubber circuit may have the same circuit structure as the first RC snubber circuit in fig. 1. The initial driving signal charges the first capacitor C2 after passing through the first resistor R2. For the circuits subsequent to the first capacitor C2, the initial driving signal is adjusted by the charging and discharging time of the first capacitor C2 to obtain the first driving signal. The first driving signal is subjected to logic operation through a first logic gate adjusting circuit to obtain a gate driving signal. The gate driving signal may be directly output to the power device under test 103 or output to the power device under test 103 via the driver 104.
In some embodiments, the first logic gate adjusting circuit may specifically adjust a level flip speed of the first driving signal through a logic operation. The logic operation (such as negation or cut-through) of the first logic gate adjusting circuit is determined according to the specific circuit structure.
On the basis that the buffer circuit comprises a second RC buffer circuit, a first logic gate adjusting circuit can be further included. Therefore, for some scenes with requirements on the turn-off time of the power device to be driven, the application requirements can be met by further adjusting the driving signal through the first logic gate adjusting circuit in the buffer circuit. In practical applications, the first logic gate adjusting circuit can be implemented in various ways.
For example, in fig. 4, the first logic gate adjustment circuit may include an and gate 1011. The and gate 1011 may be connected to an RC buffer circuit (e.g. the first RC buffer circuit shown in fig. 2 or the second RC buffer circuit shown in fig. 3), wherein the driving signal after delay adjustment by the RC buffer circuit is output to the driver from the and gate 1011. In some embodiments, the RC snubber circuit includes a resistor R and a capacitor C, as shown in fig. 4, and gate 1011 may be connected to one end of resistor R. The resistor R may be a fixed resistor or an adjustable circuit, and in this embodiment, an adjustable resistor is preferably used.
Further, as shown in fig. 4, in some embodiments, the first logic gate adjustment circuit may further include a third resistor 1012. The third resistor 1012 may be connected to an RC buffer circuit, wherein the initial driving signal is output to the RC buffer circuit through the third resistor 1012 to adjust the load capacity of the driving signal by adding the third resistor. In some embodiments, the RC snubber circuit includes a resistor R and a capacitor C. As shown in fig. 4, the initial driving signal may be connected to one end of the third resistor 1012, the other end of the second resistor 1012 may be connected to one end of the resistor R, the other ends of the resistor R are respectively connected to the capacitor C and the and gate 1011, and the output end of the and gate 1011 is connected to the driver 104. Therefore, the power device to be tested can be switched on timely, and the switching-off time requirement of the power device to be tested can be met.
Fig. 5 is a block diagram illustrating a power device driving circuit 500 according to still another embodiment of the present invention. It is understood that fig. 5 is yet another specific implementation of the power device driving circuit 100 of fig. 1. Fig. 5 can also be understood as a further supplement to the function of the power device driving circuit 300 in fig. 3. The same applies, therefore, to fig. 5 as described above in connection with the relevant details in fig. 1 and 3. For example, the initial drive signal in fig. 5 may be generated by a signal generator or pulse generation circuit. While the drivers 104 may be reserved or eliminated according to application requirements. Also for example, the resistor in the snubber circuit 101 may be a fixed resistor, an adjustable varistor, or the like.
Referring specifically to fig. 5, the power device driving circuit 500 may include a buffer circuit 101 and a signal source 102. On the basis that the buffer circuit includes an RC buffer circuit, a first logic gate adjusting circuit and a driver 104 may be further included, and in particular, the first logic gate adjusting circuit may include a first nand gate 1013, a second nand gate 1014, and a diode 1015. The input end of the first nand gate 1013 is connected to the initial driving signal, and the output end thereof is connected to the input end of the RC buffer circuit. The input of the second nand gate 1014 is connected to the output of the RC buffer circuit, and its output is connected to the driver 102. And the anode of the diode 1015 is connected to the output of the first nand gate 1013, and the cathode thereof is connected to the input of the second nand gate 1014. Therefore, for some scenes with requirements on the turn-off time of the power device to be driven, the application requirements can be met by further adjusting the driving signal through the logic gate adjusting circuit in the buffer circuit.
In some embodiments, an RC snubber circuit (e.g., a first RC snubber circuit shown in fig. 2 or a second RC snubber circuit shown in fig. 3) includes a resistor R and a capacitor C. In the connection relationship between the devices in the power device driving circuit, as shown in fig. 5, the input end of the first nand gate may be connected to the initial driving signal, and the output end thereof may be connected to one end of the 5 resistor R and the anode of the diode 1015. A cathode of the diode 1015 may be connected to the other end of the 5-resistor R, one end of the capacitor C, and an input of the second nand gate 1014. The output of the second nand gate 1014 is connected to the input of the driver 104, and the output of the driver 104 is connected to the gate of the power device 103 to be driven. The source of the power device 103 to be driven and the other end of the capacitor C are commonly grounded. It should be noted that the description of the connection relationship of the devices in the power device driving circuit is only an exemplary description.
Further, the operation principle of the power device driving circuit will be described with reference to the circuit configuration shown in fig. 5. In this scenario, the initial signal may include high and low levels at which the duty cycle may be set. When a low-level signal is input, the high-level driving signal is inverted via the first nand gate 1013. Under the action of the high-level driving signal, the diode 1015 is turned on. At this time, the capacitor C is charged through the diode 1015, the voltage of the capacitor C is rapidly increased from a low level to a high level, and then is inverted through the second nand gate 1014 to obtain a low level signal, at this time, the driver 104 of the power device to be tested outputs the low level, and the power device to be tested is turned off. When a high level signal is input, the first nand gate 1013 is inverted to obtain a low level signal, at this time, the diode 1015 is turned off in the opposite direction, and the first nand gate 1013 discharges the capacitor C through the resistor R. After a certain discharge time, the voltage of the capacitor C is reduced from a high level to a low level, the second nand gate 1014 inverts the low level signal into a high level signal, at this time, the driver 104 of the power device to be tested outputs a high level, and the power device to be tested is turned on. In addition, after the resistance value of the resistor R in the power device driving circuit is adjusted in advance, the power device to be driven can be ensured to be switched on when the drain-source voltage of the power device to be driven resonates to the valley voltage without being adjusted again in use. The resistance value adjustment process of the resistor R can refer to the related description, and is not described herein again. It can be seen that in the whole adjustment process of the driving signal, the diode can ensure that the driving signal only adjusts the time delay of the power device at the turn-on moment through RC buffer without changing the turn-off moment, so that the adjusted driving signal can better meet the actual requirement.
The driving circuit adjusts the driving signal through the buffer circuit in the power device driving circuit to drive the power device to be switched on at the right time, the whole circuit structure is simple, the used device cost is low, and the realization cost of the whole circuit technology can be effectively reduced.
An application scenario of the power device driving circuit is described below with reference to fig. 6 and 7.
Fig. 6 is a block diagram illustrating a semiconductor device test circuit 500 according to an embodiment of the present invention. The semiconductor device test circuit 600 may include a primary circuit and a secondary circuit, wherein the primary circuit includes a primary winding and a primary power device to be tested connected in series, two ends of the primary circuit are used to connect a test power supply to form a loop, the secondary circuit includes a secondary winding and a secondary transistor to be tested connected in series, the primary winding and the secondary winding form a flyback transformer, the primary circuit and the secondary circuit are connected in parallel and grounded, the primary circuit further includes a first power device driving circuit connected to the primary power device to be tested, and the power device driving circuit includes a power device driving circuit as shown in fig. 1 to 5, wherein a buffer circuit in the power device driving circuit is used to process an initial driving signal according to a test condition of the primary power device to be tested, and outputs a first gate driving signal for the primary power device to be tested, so as to control the primary power device to be tested to be turned on when a drain-source voltage of the primary power device to be tested oscillates to a valley bottom based on the first gate driving signal.
Specifically, as shown in fig. 6, the semiconductor device test circuit 600 may include the power device driving circuit shown in fig. 5. Wherein the power device driving circuit in the semiconductor device test circuit 600 comprises a first NAND gate U bu-n Diode D bu-n A first resistor R bu-n Capacitor C bu-n A second NAND gate U bu-2n And a driver. In addition, fig. 6 also shows a primary side power device Q to be tested L-n Secondary side transistor D to be tested H-n And the primary winding and the secondary winding form a flyback transformer T n 。
By combining the flyback circuit and energy feedback, a secondary side circuit of the semiconductor device test circuit is connected to a primary side circuit and is equivalent to an energy storage + energy feedback double-pulse circuit, various switch tests such as stress and current are realized, and the power consumption of the test circuit can be effectively reduced. Meanwhile, the driving signal is adjusted by additionally arranging the power device driving circuit, the problem that the drain-source resonant voltage and the switching loss are greatly different when the device to be detected is switched on due to the difference of the leakage inductance of the transformer, the parasitic capacitance of the power device and the like can be solved, and the working condition of the practical flyback adapter can be simulated to the maximum extent.
Further, fig. 6 also shows an RCD snubber circuit and an AC snubber circuit (i.e., an active clamp snubber circuit). Therefore, the RCD absorption circuit can be used for reducing the turn-off voltage spike caused by the leakage inductance of the flyback transformer, and evaluation tests can be carried out on the indexes of the primary side power device to be tested in the RCD absorption circuit, such as the switching characteristic, the reliability and the like. In addition, the AC absorption circuit can reduce the turn-off voltage spike caused by the leakage inductance of the flyback transformer, and meanwhile, the evaluation test can be carried out on the indexes of the switching characteristic, the reliability and the like of the primary side power device to be tested in the AC absorption circuit.
Further, in some embodiments, the secondary side transistor under test may also include a secondary side power device under test (not shown in fig. 6). The secondary side circuit further comprises a second power device driving circuit connected to the secondary side power device to be tested, and the second power device driving circuit comprises the power device driving circuits shown in the figures 1 to 5. The buffer circuit in the power device driving circuit is used for processing the initial driving signal according to the testing working condition of the secondary side power device to be tested and outputting a second grid driving signal aiming at the secondary side power device to be tested so as to control the secondary side power device to be tested to be switched on when the drain-source voltage of the secondary side power device to be tested oscillates to the valley bottom based on the second grid driving signal. Therefore, the switching characteristic of the secondary side power device to be tested for synchronous rectification can be evaluated. During actual test, the adjusted driving signals can be respectively input to the primary side power device to be tested and the secondary side power device to be tested through the power device driving circuit, so that the primary side power device to be tested and the secondary side power device to be tested can be periodically switched on and off according to the driving signals. For example: the driving signals of the primary side power device to be tested and the secondary side power device to be tested can be complementary and added with certain dead time.
Fig. 7 is a block diagram illustrating a semiconductor device test system 700 according to an embodiment of the present invention. The aging test system is different from the traditional aging test system of the flyback adapter and has the defects and problems of more load equipment, large aging power consumption, complex and large batch test system, inconvenience for large-batch test and screening of devices and the like. The semiconductor device testing system 700 in this embodiment may include a plurality of primary circuits and secondary circuits, where each primary circuit includes a primary winding and a primary power device to be tested connected in series, two ends of each primary circuit are used to connect a test power supply to form a loop, each secondary circuit includes a secondary winding and a secondary transistor to be tested connected in series, each primary winding and each secondary winding form a flyback transformer, and each primary circuit and each secondary circuit are connected in parallel and grounded. Each primary side circuit also comprises a first power device driving circuit which is connected to the primary side power device to be tested; and/or the secondary side transistor to be tested comprises a secondary side power device to be tested, and each secondary side circuit further comprises a second power device driving circuit connected to the secondary side power device to be tested.
In some embodiments, the first power device driving circuit and/or the second power device driving circuit include power device driving circuits as shown in fig. 1 to 5, and the plurality of power device driving circuits generate the same initial driving signal based on one signal source, where each power device driving circuit is configured to process the initial driving signal according to a test condition of the corresponding primary power device to be tested or the corresponding secondary power device to be tested to obtain a gate driving signal, and output a corresponding gate driving signal to the corresponding primary power device to be tested or the corresponding secondary power device to be tested, so as to control the corresponding primary power device to be tested to be turned on when a drain-source voltage of the primary power device to be tested oscillates to a valley bottom based on the corresponding gate driving signal, or control the corresponding secondary power device to be tested to be turned on when a drain-source voltage of the secondary power device to be tested oscillates to the valley bottom based on the corresponding gate driving signal.
Therefore, the input of all semiconductor device test circuits shares the test power supply, and the devices to be tested share the initial drive signal to form a batch test system. The driving signal is introduced into the power device driving circuit, so that the problem that the leakage source voltage is inconsistent when the device to be tested is switched on due to the fact that the leakage inductance and parasitic parameters of a transformer in the actual system switching process are deviated is avoided, and the consistency and the accuracy of batch testing of the device to be tested based on the flyback working condition are guaranteed.
In some embodiments, as shown in fig. 6, a fuse is further connected in series between the positive electrode of the test power supply and the primary side circuit of each semiconductor device test circuit, so that the independence of each semiconductor device test circuit can be effectively improved, and the aging test of other semiconductor device test circuits is not affected when the primary side to-be-tested switching element of a certain semiconductor device test circuit fails.
In some embodiments, as shown in fig. 6, the test power supply is a dc bus, and the signal source is configured to input an initial driving signal to the power device driving circuit in each of the semiconductor device test circuits. In actual connection, the first semiconductor device test circuit includes a fuse F in-1 Capacitor C in-1 Flyback transformer T 1 Diode D H-1 And a power device Q to be tested L-1 And a power device driving circuit 1 (including the first and second transistors)NOT gate U bu-1 Diode D bu-1 A first resistor R bu-1 Capacitor C bu-1 A second NAND gate U bu-21 And a driver) including a fuse F in the second semiconductor device test circuit in-2 Capacitor C in-2 Flyback transformer T 2 Diode D H-2 And a power device Q to be tested L-2 And a power device driving circuit 2 (including a first nand gate U) bu-2 Diode D bu-2 A first resistor R bu-2 Capacitor C bu-2 A second NAND gate U bu-22 And a driver including a fuse F in an n-th semiconductor device test circuit in-n Capacitor C in-n Flyback transformer T n Diode D H-n And a power device Q to be tested L-n And a power device driving circuit n (including a first NAND gate U) bu-n Diode D bu-n A first resistor R bu-n Capacitor C bu-n A second NAND gate U bu-2n And a driver) which connects both ends of the primary side circuit of each semiconductor device test circuit to the direct current bus respectively to form a loop, and connects the power device driving circuit of each semiconductor device test circuit to the signal source. It should be understood that each semiconductor device test circuit is independent of the others due to the arrangement of the fuses.
Therefore, the overall power consumption of the test system can be effectively reduced, and the problem that the tested devices are inconsistent in test conditions and loss in the batch test process can be effectively solved, so that the working condition of the actual flyback adapter is simulated to the maximum extent. And the test temperature, the test voltage, the test current, the test frequency, the test duty cycle and the number of test devices related to the test system can be adjusted according to the acceleration condition so as to meet the multi-dimensional acceleration test requirement.
While various embodiments of the present invention have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous modifications, changes, and substitutions will occur to those skilled in the art without departing from the spirit and scope of the present invention. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. It is intended that the following claims define the scope of the invention and that the module compositions, equivalents, or alternatives falling within the scope of these claims be covered thereby.
Claims (10)
1. A power device driving circuit, comprising:
a signal source for generating an initial driving signal; and
and the buffer circuit is used for receiving the initial driving signal, carrying out time delay processing on the initial driving signal and outputting a gate driving signal subjected to time delay processing based on the testing working condition of the power device to be tested, wherein the gate driving signal is used for controlling the power device to be tested to be switched on when the drain-source voltage of the power device to be tested oscillates to the valley bottom.
2. The power device driving circuit according to claim 1, wherein the buffer circuit comprises:
and the first RC buffer circuit comprises a first resistor and a first capacitor, and is used for carrying out time delay processing on the initial driving signal by utilizing the charging and discharging process of the first capacitor to obtain the grid driving signal.
3. The power device driving circuit according to claim 1, wherein the snubber circuit further comprises:
the second RC buffer circuit comprises a second resistor and a second capacitor, and is used for carrying out time delay processing on the initial driving signal by utilizing the charge-discharge process of the second capacitor to obtain a first driving signal;
and the first logic gate adjusting circuit is connected to the second RC buffer circuit and carries out logic operation on the first driving signal output by the second RC buffer circuit to obtain the gate driving signal.
4. The power device driving circuit according to claim 3,
the first logic gate adjusting circuit is a first NAND gate circuit;
wherein the buffer circuit further comprises:
and the second NAND gate circuit comprises a first input end and a first output end, the first input end is used for receiving the initial driving signal, and the first output end is used for being connected with the second RC buffer circuit.
5. The power device driving circuit according to claim 4, wherein the snubber circuit further includes:
a diode having an anode connected to the first output of the second NAND gate and a cathode connected to the input of the first NAND gate.
6. The power device driver circuit of claim 3, wherein the first logic gate adjustment circuit further comprises:
and the input end of the AND gate is respectively connected with one end of the second resistor and one end of the second capacitor, and the other end of the second capacitor is grounded.
7. The power device driving circuit according to claim 2 or 3, wherein the first resistor or the second resistor comprises an adjustable resistor, and the adjustable resistor is used for adjusting a resistance value in the first RC buffer circuit or the second RC buffer circuit so as to delay the initial driving signal to a time when a drain-source voltage of the power device to be tested oscillates to a valley bottom.
8. The utility model provides a semiconductor device test circuit, its characterized in that includes primary circuit and secondary circuit, wherein the primary circuit includes the primary winding and the primary power device that awaits measuring of establishing ties, the both ends of primary circuit are used for connecting test power supply in order to form the return circuit, secondary circuit includes the secondary winding and the secondary transistor that awaits measuring of establishing ties, the primary winding with secondary winding forms flyback transformer, the primary circuit with secondary circuit connects in parallel and ground connection, wherein the primary circuit still includes:
the first power device driving circuit is connected to the primary side power device to be tested, and comprises the power device driving circuit as claimed in any one of claims 1 to 7, wherein a buffer circuit in the power device driving circuit is used for processing an initial driving signal according to a test condition of the primary side power device to be tested, and outputting a first gate driving signal for the primary side power device to be tested, so as to control the primary side power device to be tested to be turned on when a drain-source voltage of the primary side power device to be tested oscillates to a valley bottom based on the first gate driving signal.
9. The semiconductor device test circuit of claim 8, wherein the secondary side transistor-under-test comprises a secondary side power-under-test device, the secondary side circuit further comprising:
the second power device driving circuit is connected to the secondary side power device to be tested, and comprises the power device driving circuit as claimed in any one of claims 1 to 7, wherein a buffer circuit in the power device driving circuit is used for processing an initial driving signal according to a test condition of the secondary side power device to be tested, and outputting a second gate driving signal for the secondary side power device to be tested, so as to control the secondary side power device to be tested to be turned on when a drain-source voltage of the secondary side power device to be tested oscillates to a valley bottom based on the second gate driving signal.
10. A semiconductor device test system, comprising:
the primary side circuit comprises a primary winding and a primary side power device to be tested which are connected in series, two ends of each primary side circuit are used for being connected with a test power supply to form a loop, each secondary side circuit comprises a secondary winding and a secondary side transistor to be tested which are connected in series, each primary winding and each secondary side winding form a flyback transformer, and each primary side circuit and each secondary side circuit are connected in parallel and are grounded;
each primary side circuit further comprises a first power device driving circuit which is connected to the primary side power device to be tested; and/or the secondary side transistor to be tested comprises a secondary side power device to be tested, and each secondary side circuit also comprises a second power device driving circuit connected to the secondary side power device to be tested;
the first power device driving circuit and/or the second power device driving circuit comprise the power device driving circuits as claimed in any one of claims 1 to 7, and a plurality of the power device driving circuits generate the same initial driving signal based on the signal source thereof, wherein each of the power device driving circuits is configured to process the initial driving signal according to the test condition of the corresponding primary power device to be tested or the corresponding secondary power device to be tested to obtain a gate driving signal, and output the corresponding gate driving signal to the corresponding primary power device to be tested or the corresponding secondary power device to be tested, so as to control the corresponding primary power device to be tested to be turned on when the drain-source voltage of the power device to be tested oscillates to the valley bottom based on the corresponding gate driving signal, or control the corresponding secondary power device to be tested to be turned on when the drain-source voltage of the secondary power device to be tested oscillates to the valley bottom based on the corresponding gate driving signal.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211438243.4A CN115754654A (en) | 2022-11-16 | 2022-11-16 | Power device driving circuit, semiconductor device testing circuit and system |
| PCT/CN2023/111159 WO2024103853A1 (en) | 2022-11-16 | 2023-08-04 | Power device driving circuit, and semiconductor device testing circuit and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211438243.4A CN115754654A (en) | 2022-11-16 | 2022-11-16 | Power device driving circuit, semiconductor device testing circuit and system |
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| CN115754654A true CN115754654A (en) | 2023-03-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211438243.4A Pending CN115754654A (en) | 2022-11-16 | 2022-11-16 | Power device driving circuit, semiconductor device testing circuit and system |
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| CN (1) | CN115754654A (en) |
| WO (1) | WO2024103853A1 (en) |
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| WO2024103853A1 (en) * | 2022-11-16 | 2024-05-23 | 湖南三安半导体有限责任公司 | Power device driving circuit, and semiconductor device testing circuit and system |
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| WO2024103853A1 (en) | 2024-05-23 |
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