CN115754654A - Power device drive circuit, semiconductor device test circuit and system - Google Patents

Abstract

The invention relates to a power device driving circuit, a semiconductor device testing circuit and a system. Wherein the power device driving circuit includes: a signal source for generating an initial driving signal; and the buffer circuit is used for receiving the initial driving signal, carrying out time delay processing on the initial driving signal and outputting a time-delayed gate driving signal based on the testing working condition of the power device to be tested, wherein the gate driving signal is used for controlling the power device to be tested to be switched on when the drain-source voltage of the power device to be tested oscillates to the valley bottom. By the scheme of the invention, the drive signal of the power device to be tested can be subjected to time delay adjustment, so that the power device to be tested can be switched on when the drain-source voltage of the power device to be tested oscillates to the valley bottom, and the application requirement of the power device is met.

Description

Power device drive circuit, semiconductor device test circuit and system

technical field

The present invention generally relates to the field of semiconductor device technology. More specifically, the present invention relates to a power device driving circuit, a semiconductor device testing circuit and a semiconductor device testing system.

Background technique

In recent years, the market demand for mobile phone fast charging adapters using GaN power transistors and other power devices has increased, especially GaN adapters based on flyback circuits have been widely used. In order to ensure the reliability of the product, performance tests such as aging are generally required for the corresponding power devices used in the adapter. In the related art, the power device is tested by simulating the working condition of the flyback circuit. However, in practical applications, due to the deviation of nonlinear devices (such as transformer leakage inductance and switch tube parasitic capacitance, etc.) in the test circuit, the power device under test is not turned on when its drain-source voltage resonates to the bottom, making the analog circuit work The conditions are far from the actual working conditions of the power device under test, resulting in inaccurate test results.

Contents of the invention

In order to at least solve the technical problems described in the above background technology section, the present invention proposes a power device drive circuit, which can adjust the delay of the initial drive signal of the power device to be tested, so that the dynamic power device under test can It turns on when the drain-source voltage oscillates to the bottom to meet the application requirements for power devices.

In view of this, the present invention provides solutions in the following aspects.

The first aspect of the present invention provides a power device drive circuit, including: a signal source, used to generate an initial drive signal; and a buffer circuit, used to receive the initial drive signal, based on the test conditions of the power device under test, Delaying the initial drive signal and outputting a delayed gate drive signal, wherein the gate drive signal is used to control the power device under test at the drain-source of the power device under test Turns on when the voltage oscillates to the bottom.

The second aspect of the present invention provides a semiconductor device test circuit, including a primary circuit and a secondary circuit, wherein the primary circuit includes a primary winding in series and a primary power device to be tested, and the primary circuit The two ends are used to connect the test power supply to form a loop. The secondary circuit includes a secondary winding in series and a secondary transistor to be tested. The primary winding and the secondary winding form a flyback transformer. The primary circuit It is connected in parallel with the secondary side circuit and grounded, wherein the primary side circuit further includes: a first power device drive circuit connected to the primary side power device under test, including the first invention of the present invention and the following embodiments The power device driving circuit described above, wherein the buffer circuit in the power device driving circuit is used to process the initial driving signal according to the test working condition of the power device under test on the primary side, and output the power for the power device under test on the primary side The first gate driving signal of the device is used to control the primary power device under test to turn on when the source-drain voltage of the primary power device under test oscillates to the bottom based on the first gate driving signal.

A third aspect of the present invention provides a semiconductor device testing system, including a plurality of primary circuits and secondary circuits, wherein each of the primary circuits includes a primary winding and a primary power device to be tested in series, and each The two ends of the primary side circuit are used to connect the test power supply to form a loop, each of the secondary side circuits includes a secondary side winding and a secondary side transistor to be tested in series, each of the primary side windings and each of the secondary side The side winding forms a flyback transformer, each of the primary side circuits and each of the secondary side circuits are connected in parallel and grounded; wherein each of the primary side circuits also includes a first power device drive circuit connected to the primary side to be A power device to be measured; and/or the secondary side transistor under test includes a secondary side power device under test, and each of the secondary side circuits further includes a second power device drive circuit connected to the secondary side power device under test; wherein The first power device driving circuit and/or the second power device driving circuit includes the power device driving circuit described in the first aspect of the present invention and the following multiple embodiments, and the multiple power device driving circuits are based on their signals The source generates the same initial drive signal, wherein each of the power device drive circuits is used to process the initial drive signal according to the test conditions of its corresponding primary side power device under test or secondary side power device under test to obtain a gate pole drive signal, and output the corresponding gate drive signal to its corresponding primary side power device under test or secondary side power device under test, so as to control its corresponding primary side power device under test based on the corresponding gate drive signal. Turn on when the drain-source voltage of the primary power device under test oscillates to the bottom, or control the corresponding secondary power device under test to turn on when the drain-source voltage of the secondary power device under test oscillates to the bottom.

Utilizing the scheme provided by the present invention, based on the buffer circuit in the power device drive circuit, the initial drive signal of the power device under test is delayed, so that the dynamic power device under test can oscillate at the drain-source voltage of the power device under test Turn on when it reaches the bottom, so as to meet the application requirements of power devices. In some embodiments, the power device driving circuit can be applied to a semiconductor device test circuit, so as to ensure that the simulated circuit working conditions for the power devices conform to the actual working conditions, thereby improving test accuracy. In addition, in some other embodiments, the power device drive circuit can also be applied to a semiconductor device test system to overcome the problem of inconsistent test conditions and power consumption of the power device under test in the batch test process, thereby effectively ensuring that the semiconductor device The working conditions of each power device under test in the test system are consistent.

Description of drawings

The above and other objects, features and advantages of exemplary embodiments of the present invention will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the present invention are shown by way of illustration and not limitation, and the same or corresponding reference numerals indicate the same or corresponding parts, wherein:

FIG. 1 is a structural diagram showing a power device driving circuit according to a first embodiment of the present invention;

2 is a structural diagram showing a power device driving circuit according to a second embodiment of the present invention;

3 is a structural diagram showing a power device driving circuit according to a third embodiment of the present invention;

4 is a structural diagram showing a power device driving circuit according to a fourth embodiment of the present invention;

5 is a structural diagram showing a power device driving circuit according to a fifth embodiment of the present invention;

6 is a structural diagram illustrating a semiconductor device test circuit according to an embodiment of the present invention; and

FIG. 7 is a configuration diagram showing a semiconductor device testing system according to an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of them. Based on the implementation manners in the present invention, all other implementation manners obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

It should be understood that the terms "first", "second", "third" and "fourth" in the claims, description and drawings of the present invention are used to distinguish different objects, rather than to describe a specific order . The terms "comprising" and "comprising" used in the description and claims of the present invention indicate the presence of described features, integers, steps, operations, elements and/or components, but do not exclude one or more other features, integers , steps, operations, elements, components, and/or the presence or addition of collections thereof.

It should also be understood that the terms used in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used in the specification and claims herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly dictates otherwise. It should be further understood that the term "and/or" used in the description and claims of the present invention refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

The inventors have found through research that for power devices such as gallium nitride power transistors, a driving signal is usually used to directly trigger the power device to be turned on or off. However, with the wide application of power devices such as gallium nitride power transistors, the power devices need to work under corresponding working conditions. In particular, for the batch test circuit system based on the flyback circuit and energy feedback, the power device under test in the system needs to work in the flyback circuit condition. At this time, the power device under test needs to meet the minimum resonance at its drain-source Voltage (that is, the valley voltage) is turned on. However, in practical applications, due to the deviation of some nonlinear devices in the flyback circuit (such as transformer leakage inductance deviation, etc.), the source-drain voltage resonance period of the power device under test may be different, resulting in the turn-on condition of the power device under test ( For example, the drain-source voltage of the power device under test does not resonate to the bottom and then turns on) does not meet the application requirements. For this reason, the inventors also found that the driving signal of the power device can be adjusted so that the driving signal can trigger the power device to be turned on in good time, so as to meet the application requirements of the power device.

The specific implementation manner of the present invention will be described in detail below in conjunction with the accompanying drawings.

FIG. 1 is a structural diagram illustrating a power device driving circuit 100 according to an embodiment of the present invention. As shown in FIG. 1 , the power device driving circuit 100 may include a buffer circuit 101 and a signal source 102 . Meanwhile, in order to illustrate the working principle of the power device driving circuit 100 more clearly, a power device 103 under test is also shown in FIG. 1 .

Wherein, the aforementioned signal source can be used to generate the initial driving signal. In some embodiments, the signal source may specifically include a signal generator or a pulse generating circuit or the like. Specifically, the initial driving signal may be generated by a signal generator or a pulse generating circuit, and in some implementation scenarios, the initial driving signal may include high and low levels with a duty cycle that can be set. It should be noted that the detailed description of the initial driving signal here is only an exemplary description.

The aforementioned buffer circuit 101 can receive the initial driving signal, and can delay the initial driving signal and output the delayed gate driving signal based on the test condition of the power device under test. Wherein, the gate drive signal can be used to control the power device under test to turn on when the drain-source voltage of the power device under test oscillates to the bottom. Therefore, based on the test conditions of the power device under test, the initial drive signal can be adaptively delayed through the buffer circuit, and the turn-on time point of the power device under test can be adjusted, so that the adjusted drive signal can trigger the power device in time turned on to meet the application requirements of power devices. It should be noted that the foregoing power device may include a gallium nitride power device, a silicon carbide power device or other power devices, and the specific type of the power device is not limited here.

In some embodiments, the aforementioned power device driving circuit may further include a driver. The driver can receive the gate drive signal output from the buffer circuit 101 and output the gate drive signal to the power device under test.

The foregoing buffer circuit 101 may have various implementation forms in specific applications, which will be further described below in conjunction with FIG. 2 to FIG. 5 .

FIG. 2 is a structural diagram illustrating a power device driving circuit 200 according to another embodiment of the present invention. It can be understood that FIG. 2 is a specific implementation of the power device driving circuit 100 in FIG. 1 . Therefore, the foregoing detailed descriptions in conjunction with FIG. 1 also apply to FIG. 2 . For example, the initial driving signal in FIG. 2 can be generated by a signal generator or a pulse generating circuit. In addition, the driver 104 is shown in the power driving circuit 200 at the same time, and the driver 104 can be deleted or reserved according to actual application requirements.

Specifically referring to FIG. 2 , the power device driving circuit 200 may include a buffer circuit 101 and a signal source 102 . Wherein, the aforementioned buffer circuit 101 may include a first RC buffer circuit, and the first RC buffer circuit may use the charging and discharging process of the capacitor therein to perform delay adjustment on the aforementioned initial driving signal. Specifically, in some embodiments, the first RC snubber circuit may include a first resistor R1 and a first capacitor C1. One end of the first capacitor C1 is connected to the first resistor R1, and the other end of the first capacitor C1 is grounded. The initial driving signal will charge the first capacitor C1 after passing through the first resistor R1. For the circuits following the first capacitor C1, the gate drive signal is obtained after the initial drive signal is adjusted by the charging and discharging time of the first capacitor C1. The gate drive signal can be directly output to the power device 103 under test, or output to the power device 103 under test through the driver 104 .

Further, in some embodiments, the aforesaid first resistor may include a fixed resistor, specifically, the required fixed resistor may be determined according to the application requirements of the device to be driven, and the fixed resistors with different resistance values may be exchanged to adapt to The power device driving circuit 200 can be permanently adjusted to meet application requirements.

For another example, in some other embodiments, the aforementioned first resistor may also include an adjustable resistor. In this scenario, the resistance of the adjustable resistor can be directly adjusted according to the application requirements, without cumbersome resistor replacement operations. For example, the drain-source voltage when the power device to be driven is turned on can be adjusted based on the resistance value of the adjustable resistor. In practical applications, the resistance value can be adjusted with an oscilloscope. Specifically, in the process of adjusting the resistance value of the adjustable resistor, an oscilloscope can be used to detect the turn-on of the power device to be driven until it is detected by the oscilloscope that the power device to be driven is turned on when its drain-source voltage is at the bottom. stop the adjustment of the resistance value. It should be noted that the description of the process of adjusting the resistance of the adjustable resistor here is only an example, and the solution of the present invention is not limited thereto.

FIG. 3 is a structural diagram showing a power device driving circuit 300 according to yet another embodiment of the present invention. It can be understood that FIG. 3 is another specific implementation of the power device driving circuit 100 in FIG. 1 . In addition, FIG. 3 can also be understood as a further supplement to the function of the power device driving circuit 200 in FIG. 2 . Therefore, the foregoing detailed descriptions in conjunction with FIGS. 1 and 2 also apply to FIG. 3 . For example, the initial driving signal in FIG. 3 can be generated by a signal generator or a pulse generating circuit. In addition, the driver 104 is also shown in the power driving circuit 300, and the driver 104 can be deleted or reserved according to actual application requirements. .

Referring specifically to FIG. 3 , the power device driving circuit 300 may include a buffer circuit 101 and a signal source 102 . Wherein, the buffer circuit includes a second RC buffer circuit and a first logic gate adjustment circuit. The second RC snubber circuit includes a second resistor R2 and a second capacitor C2. It can be understood that the second RC snubber circuit may have the same circuit structure as the first RC snubber circuit in FIG. 1 . The initial driving signal will charge the first capacitor C2 after passing through the first resistor R2. For the circuits following the first capacitor C2, the initial drive signal is adjusted to obtain the first drive signal after the charging and discharging time of the first capacitor C2 is adjusted. The first drive signal is subjected to a logic operation by the first logic gate adjustment circuit to obtain a gate drive signal. The gate drive signal can be directly output to the power device 103 under test, or output to the power device 103 under test through the driver 104 .

In some embodiments, the first logic gate adjustment circuit can specifically adjust the level inversion speed of the first driving signal through logic operations. Wherein, the logic operations (such as operations such as inversion or switching) in the first logic gate adjustment circuit need to be determined according to its specific circuit structure.

On the basis that the buffer circuit includes the second RC buffer circuit, it may further include a first logic gate adjustment circuit. Therefore, for some scenarios that require the turn-off time of the power device to be driven, the driving signal can be further adjusted by the first logic gate adjustment circuit in the buffer circuit to meet the application requirements. In practical applications, the first logic gate adjustment circuit may be implemented in various manners.

For example, in FIG. 4 , the first logic gate adjustment circuit may include an AND gate 1011 . The AND gate 1011 can be connected to an RC snubber circuit (such as the first RC snubber circuit shown in FIG. 2 or the second RC snubber circuit shown in FIG. 3 ), wherein the drive signal after delay adjustment by the RC snubber circuit is obtained by AND Gate 1011 outputs to the driver. In some embodiments, the RC snubber circuit includes a resistor R and a capacitor C, as shown in FIG. 4 , and the AND gate 1011 can be connected to one end of the resistor R at this time. Wherein, the resistor R may be a fixed resistor or an adjustable circuit, and in this embodiment, an adjustable resistor is preferably used.

Further, as shown in FIG. 4 , in some embodiments, the first logic gate adjustment circuit may further include a third resistor 1012 . The third resistor 1012 can be connected to the RC snubber circuit, wherein the initial driving signal is output to the RC snubber circuit through the third resistor 1012, so as to adjust the load capacity of the driving signal by adding the third resistor. In some embodiments, the RC snubber circuit includes a resistor R and a capacitor C. As shown in FIG. 4 , the initial drive signal can be connected to one end of the third resistor 1012 at this time, the other end of the second resistor 1012 can be connected to one end of the resistor R, and the other end of the resistor R is respectively connected to the capacitor C and the AND gate 1011 , the output end of the AND gate 1011 is connected to the driver 104 . Thus, not only can it be ensured that the power device under test can be turned on in good time, but also the off time requirement of the power device under test can be met.

FIG. 5 is a structural diagram showing a power device driving circuit 500 according to yet another embodiment of the present invention. It can be understood that FIG. 5 is another specific implementation of the power device driving circuit 100 in FIG. 1 . In addition, FIG. 5 can also be understood as a further supplement to the function of the power device driving circuit 300 in FIG. 3 . Therefore, the foregoing detailed descriptions in conjunction with FIGS. 1 and 3 also apply to FIG. 5 . For example, the initial driving signal in FIG. 5 can be generated by a signal generator or a pulse generating circuit. The driver 104 can be reserved or deleted according to application requirements. Also for example, the resistors in the snubber circuit 101 may be fixed resistors or adjustable rheostats.

Referring specifically to FIG. 5 , the power device driving circuit 500 may include a buffer circuit 101 and a signal source 102 . Wherein, on the basis that the buffer circuit includes an RC buffer circuit, it may also include a first logic gate adjustment circuit and a driver 104. Specifically, the first logic gate adjustment circuit may include a first NAND gate 1013 and a second NAND gate 1014. and diode 1015. Wherein, the input end of the first NAND gate 1013 is connected to the initial driving signal, and the output end is connected to the input end of the RC buffer circuit. The input terminal of the second NAND gate 1014 is connected to the output terminal of the RC snubber circuit, and the output terminal thereof is connected to the driver 102 . The anode of the diode 1015 is connected to the output terminal of the first NAND gate 1013 , and its cathode is connected to the input terminal of the second NAND gate 1014 . Therefore, for some scenarios that require the turn-off time of the power device to be driven, the logic gate adjustment circuit in the buffer circuit can further adjust the driving signal to meet the application requirements.

In some embodiments, the RC snubber circuit (such as the first RC snubber circuit shown in FIG. 2 or the second RC snubber circuit shown in FIG. 3 ) includes a resistor R and a capacitor C. At this time, the connection relationship between each device in the power device driving circuit is as shown in Figure 5. The input end of the first NAND gate can be connected to the initial drive signal, and its output end can be connected to one end of the 5 resistor R and the diode 1015. anode. The cathode of the diode 1015 can be connected to the other end of the resistor R, one end of the capacitor C and the input end of the second NAND gate 1014 . The output terminal of the second NAND gate 1014 is connected to the input terminal of the driver 104 , and the output terminal of the driver 104 is connected to the gate of the power device 103 to be driven. The source of the power device 103 to be driven and the other end of the capacitor C share a common ground. It should be noted that, the description here of the connection relationship of the devices in the power device driving circuit is only an exemplary description.

Further, the working principle of the power device driving circuit will be described in conjunction with the circuit structure shown in FIG. 5 . In this scenario, the initial signal may include high and low levels with a duty cycle that can be set. When a low-level signal is input, the high-level drive signal is obtained through inversion through the first NAND gate 1013 . Under the action of the high-level driving signal, the diode 1015 is turned on. At this time, the capacitor C is charged through the diode 1015, and the voltage of the capacitor C rises rapidly from a low level to a high level, and then reverses through the second NAND gate 1014 to obtain a low level signal. At this time, the voltage of the power device under test The driver 104 outputs a low level, and the power device under test is turned off. When the input is a high-level signal, the first NAND gate 1013 inverts to obtain a low-level signal. At this time, the diode 1015 is turned off in reverse, and the first NAND gate 1013 discharges the capacitor C through the resistor R. After a certain discharge time, the voltage of the capacitor C drops from a high level to a low level, and the second NAND gate 1014 inverts the low level signal into a high level signal, at this time, the driver 104 of the power device under test outputs a high level Ping, the power device under test is turned on. In addition, the resistance value of the resistor R in the power device driving circuit is pre-adjusted, and there is no need to adjust it during use to ensure that the power device to be driven is turned on when its drain-source voltage resonates to the valley voltage. For the adjustment process of the resistance value of the resistor R, reference may be made to the relevant description above, which will not be repeated here. It can be seen that during the entire adjustment process of the drive signal, the diode can ensure that the drive signal only adjusts the delay of the turn-on time of the power device through the RC buffer, without changing the turn-off time, so that the adjusted drive signal can better meet the actual needs.

It can be seen that the present invention adjusts the drive signal through the buffer circuit in the drive circuit of the power device to drive the power device to be turned on in a timely manner. The entire circuit structure is simplified and the cost of the used devices is low, which can effectively reduce the implementation cost of the entire circuit technology.

The application scenarios of the power device driving circuit described above will be described below with reference to FIG. 6 and FIG. 7 .

FIG. 6 is a structural diagram showing a semiconductor device testing circuit 500 according to an embodiment of the present invention. The semiconductor device testing circuit 600 may include a primary circuit and a secondary circuit, wherein the primary circuit includes a primary winding in series and a primary power device to be tested, the two ends of the primary circuit are used to connect a test power supply to form a loop, and the secondary The side circuit includes a secondary winding in series and a secondary transistor to be tested, the primary winding and the secondary winding form a flyback transformer, the primary circuit and the secondary circuit are connected in parallel and grounded, wherein the primary circuit also includes a first power device The drive circuit is connected to the power device under test on the primary side, including a power device drive circuit as shown in Figures 1 to 5, wherein the buffer circuit in the power device drive circuit is used for testing the power device under test according to the primary side The working condition processes the initial drive signal, and outputs the first gate drive signal for the primary side power device under test, so as to control the primary side power device under test based on the first gate drive signal. Turns on when the source voltage oscillates to the bottom.

Specifically, as shown in FIG. 6 , the semiconductor device testing circuit 600 may include the power device driving circuit shown in FIG. 5 . Wherein, the power device driving circuit in the semiconductor device testing circuit 600 includes a first NAND gate U _bu-n , a diode D _bu-n , a first resistor R _bu-n , a capacitor C _bu-n , a second NAND gate U _bu-2n along with the drive. In addition, FIG. 6 also shows the power device Q _Ln to be tested on the primary side to be tested, the transistor to be tested on the secondary side D _Hn , and the flyback transformer _Tn formed by the primary winding and the secondary winding.

By combining the flyback circuit and energy feedback, the secondary side circuit of the semiconductor device test circuit is connected to the primary side circuit, which is equivalent to a double pulse circuit of energy storage + energy feedback, and realizes various switch tests such as stress and current, which can effectively reduce Test circuit power consumption. At the same time, by adding a power device drive circuit to adjust the drive signal, it can solve the problem of large differences in drain-source resonant voltage and switching loss when the device under test is turned on due to differences in transformer leakage inductance and power device parasitic capacitance. Simulate the working conditions of the actual flyback adapter to the greatest extent.

Further, FIG. 6 also shows an RCD snubber circuit and an AC snubber circuit (that is, an active clamp snubber circuit). Therefore, the RCD snubber circuit can be used to reduce the turn-off voltage spike caused by the leakage inductance of the flyback transformer, and the switching characteristics and reliability of the primary power device under test in the RCD snubber circuit can be evaluated and tested. In addition, using the AC absorption circuit can reduce the turn-off voltage spike caused by the leakage inductance of the flyback transformer, and at the same time, it can evaluate and test the switching characteristics and reliability of the primary power device under test in the AC absorption circuit.

Further, in some embodiments, the secondary-side transistor under test may further include a secondary-side power device under test (not shown in FIG. 6 ). The secondary circuit further includes a second power device driving circuit connected to the secondary power device under test, including the power device driving circuits shown in FIGS. 1 to 5 . The buffer circuit in the power device drive circuit is used to process the initial drive signal according to the test condition of the power device under test on the secondary side, and output the second gate drive signal for the power device under test on the secondary side, based on the second The gate driving signal controls the power device under test on the secondary side to turn on when the drain-source voltage of the power device under test on the secondary side oscillates to a valley bottom. In this way, the switching characteristics of the secondary power device under test for synchronous rectification can be evaluated. In the actual test, the adjusted driving signal can be input to the primary side power device under test and the secondary side power device under test respectively through the power device drive circuit, so that both the primary side power device under test and the secondary side power device under test can be tested according to The driving signal is turned on and off periodically. For example, the driving signals of the power device under test on the primary side and the power device under test on the secondary side may be complementary and a certain dead time may be added.

FIG. 7 is a structural diagram showing a semiconductor device testing system 700 according to an embodiment of the present invention. Different from the traditional flyback adapter aging test system, there are many shortcomings and problems such as many load devices, high aging power consumption, complex and huge batch test system, and it is not conducive to mass test screening of devices. The semiconductor device testing system 700 in this embodiment may include a plurality of primary circuits and secondary circuits, wherein each primary circuit includes a primary winding and a primary power device to be tested in series, and the two ends of each primary circuit It is used to connect the test power supply to form a loop. Each secondary circuit includes a series secondary winding and a secondary transistor to be tested. Each primary winding and each secondary winding form a flyback transformer. Each primary circuit and each The secondary circuits are connected in parallel and grounded. Wherein each primary side circuit also includes a first power device drive circuit connected to the primary side power device under test; and/or the secondary side transistor under test includes a secondary side power device under test, and each secondary side circuit also includes A second power device drive circuit of the power device to be tested.

In some embodiments, the first power device driving circuit and/or the second power device driving circuit include the power device driving circuits shown in Figures 1 to 5, and multiple power device driving circuits generate the same initial Drive signal, wherein each power device drive circuit is used to process the initial drive signal according to the test condition of its corresponding primary side power device under test or secondary side power device under test to obtain a gate drive signal, and send it to the corresponding The primary side power device under test or the secondary side power device under test outputs the corresponding gate drive signal, so as to control the corresponding primary side power device under test on the drain source of the primary side power device under test based on the corresponding gate drive signal Turn on when the voltage oscillates to the bottom, or control its corresponding secondary power device under test to turn on when the drain-source voltage of the secondary power device under test oscillates to the bottom.

Therefore, the inputs of all semiconductor device test circuits share the test power supply, and the devices under test share the initial drive signal to form a batch test system. The drive signal is introduced into the power device drive circuit to avoid the problem of inconsistent drain-source voltage when the device under test is turned on due to the deviation of transformer leakage inductance and parasitic parameters in the actual system switching process, so as to ensure the batch test of the device under test based on the flyback working condition consistency and accuracy.

In some embodiments, as shown in Figure 6, a fuse is also connected in series between the positive pole of the test power supply and the primary side circuit of each semiconductor device test circuit, thereby effectively improving the independence of each semiconductor device test circuit, When the switching element to be tested on the primary side of a certain semiconductor device test circuit fails, it does not affect the aging test of other semiconductor device test circuits.

In some implementations, as shown in FIG. 6 , the test power supply is a DC bus, and the signal source is used to input an initial drive signal to the power device drive circuit in each semiconductor device test circuit. In the actual connection, the first semiconductor device test circuit includes fuse F _in-1 , capacitor C _in-1 , flyback transformer T ₁ , diode D _H-1 , power device Q _L-1 under test and power device Drive circuit 1 (including first NAND gate U _bu-1 , diode D _bu-1 , first resistor R _bu-1 , capacitor C _bu-1 , second NAND gate U _bu-21 and driver), the first The two semiconductor device test circuits include fuse F _in-2 , capacitor C _in-2 , flyback transformer T ₂ , diode D _H-2 , power device Q _L-2 to be tested and power device drive circuit 2 (including the first A NAND gate U _bu-2 , a diode D _bu-2 , a first resistor R _bu-2 , a capacitor C _bu-2 , a second NAND gate U _bu-22 and a driver)... nth A semiconductor device test circuit includes a fuse F _in-n , a capacitor C _in-n , a flyback transformer T _n , a diode D _Hn , a power device to be tested Q _Ln and a power device drive circuit n (including the first NAND gate U _bu-n , diode D _bu-n , first resistor R _bu-n , capacitor C _bu-n , second NAND gate U _bu-2n and driver), the primary side circuit of each semiconductor device test circuit The two ends are respectively connected to the DC bus to form a loop, and at the same time, the power device driving circuit of each semiconductor device test circuit is connected to the signal source. It should be understood that due to the setting of the fuses, each semiconductor device testing circuit is independent.

Therefore, it can not only effectively reduce the overall power consumption of the test system, but also effectively solve the problem of inconsistent test conditions and losses of the tested devices during the batch test, thereby simulating the working conditions of the actual flyback adapter to the greatest extent. Moreover, the test temperature, test voltage, test current, test frequency, test duty cycle, and the number of test devices involved in the test system can be adjusted according to the acceleration conditions to meet the multi-dimensional acceleration test requirements.

While various embodiments of the invention have been illustrated and described, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Many modifications, changes and substitutions will occur to those skilled in the art without departing from the idea and spirit of the present invention. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. It is intended that the appended claims define the scope of the invention and therefore cover modular compositions, equivalents or alternatives within the scope of these claims.

Claims (10)

1. A power device driving circuit, comprising:

a signal source for generating an initial driving signal; and

and the buffer circuit is used for receiving the initial driving signal, carrying out time delay processing on the initial driving signal and outputting a gate driving signal subjected to time delay processing based on the testing working condition of the power device to be tested, wherein the gate driving signal is used for controlling the power device to be tested to be switched on when the drain-source voltage of the power device to be tested oscillates to the valley bottom.

2. The power device driving circuit according to claim 1, wherein the buffer circuit comprises:

and the first RC buffer circuit comprises a first resistor and a first capacitor, and is used for carrying out time delay processing on the initial driving signal by utilizing the charging and discharging process of the first capacitor to obtain the grid driving signal.

3. The power device driving circuit according to claim 1, wherein the snubber circuit further comprises:

the second RC buffer circuit comprises a second resistor and a second capacitor, and is used for carrying out time delay processing on the initial driving signal by utilizing the charge-discharge process of the second capacitor to obtain a first driving signal;

and the first logic gate adjusting circuit is connected to the second RC buffer circuit and carries out logic operation on the first driving signal output by the second RC buffer circuit to obtain the gate driving signal.

4. The power device driving circuit according to claim 3,

the first logic gate adjusting circuit is a first NAND gate circuit;

wherein the buffer circuit further comprises:

and the second NAND gate circuit comprises a first input end and a first output end, the first input end is used for receiving the initial driving signal, and the first output end is used for being connected with the second RC buffer circuit.

5. The power device driving circuit according to claim 4, wherein the snubber circuit further includes:

a diode having an anode connected to the first output of the second NAND gate and a cathode connected to the input of the first NAND gate.

6. The power device driver circuit of claim 3, wherein the first logic gate adjustment circuit further comprises:

and the input end of the AND gate is respectively connected with one end of the second resistor and one end of the second capacitor, and the other end of the second capacitor is grounded.

7. The power device driving circuit according to claim 2 or 3, wherein the first resistor or the second resistor comprises an adjustable resistor, and the adjustable resistor is used for adjusting a resistance value in the first RC buffer circuit or the second RC buffer circuit so as to delay the initial driving signal to a time when a drain-source voltage of the power device to be tested oscillates to a valley bottom.

8. The utility model provides a semiconductor device test circuit, its characterized in that includes primary circuit and secondary circuit, wherein the primary circuit includes the primary winding and the primary power device that awaits measuring of establishing ties, the both ends of primary circuit are used for connecting test power supply in order to form the return circuit, secondary circuit includes the secondary winding and the secondary transistor that awaits measuring of establishing ties, the primary winding with secondary winding forms flyback transformer, the primary circuit with secondary circuit connects in parallel and ground connection, wherein the primary circuit still includes:

the first power device driving circuit is connected to the primary side power device to be tested, and comprises the power device driving circuit as claimed in any one of claims 1 to 7, wherein a buffer circuit in the power device driving circuit is used for processing an initial driving signal according to a test condition of the primary side power device to be tested, and outputting a first gate driving signal for the primary side power device to be tested, so as to control the primary side power device to be tested to be turned on when a drain-source voltage of the primary side power device to be tested oscillates to a valley bottom based on the first gate driving signal.

9. The semiconductor device test circuit of claim 8, wherein the secondary side transistor-under-test comprises a secondary side power-under-test device, the secondary side circuit further comprising:

the second power device driving circuit is connected to the secondary side power device to be tested, and comprises the power device driving circuit as claimed in any one of claims 1 to 7, wherein a buffer circuit in the power device driving circuit is used for processing an initial driving signal according to a test condition of the secondary side power device to be tested, and outputting a second gate driving signal for the secondary side power device to be tested, so as to control the secondary side power device to be tested to be turned on when a drain-source voltage of the secondary side power device to be tested oscillates to a valley bottom based on the second gate driving signal.

10. A semiconductor device test system, comprising:

the primary side circuit comprises a primary winding and a primary side power device to be tested which are connected in series, two ends of each primary side circuit are used for being connected with a test power supply to form a loop, each secondary side circuit comprises a secondary winding and a secondary side transistor to be tested which are connected in series, each primary winding and each secondary side winding form a flyback transformer, and each primary side circuit and each secondary side circuit are connected in parallel and are grounded;

each primary side circuit further comprises a first power device driving circuit which is connected to the primary side power device to be tested; and/or the secondary side transistor to be tested comprises a secondary side power device to be tested, and each secondary side circuit also comprises a second power device driving circuit connected to the secondary side power device to be tested;

the first power device driving circuit and/or the second power device driving circuit comprise the power device driving circuits as claimed in any one of claims 1 to 7, and a plurality of the power device driving circuits generate the same initial driving signal based on the signal source thereof, wherein each of the power device driving circuits is configured to process the initial driving signal according to the test condition of the corresponding primary power device to be tested or the corresponding secondary power device to be tested to obtain a gate driving signal, and output the corresponding gate driving signal to the corresponding primary power device to be tested or the corresponding secondary power device to be tested, so as to control the corresponding primary power device to be tested to be turned on when the drain-source voltage of the power device to be tested oscillates to the valley bottom based on the corresponding gate driving signal, or control the corresponding secondary power device to be tested to be turned on when the drain-source voltage of the secondary power device to be tested oscillates to the valley bottom based on the corresponding gate driving signal.

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