CN115881711A

CN115881711A - MicroLED display device and preparation method thereof

Info

Publication number: CN115881711A
Application number: CN202211608392.0A
Authority: CN
Inventors: 胡双元
Original assignee: Laiyu Optoelectronic Technology Suzhou Co ltd
Current assignee: Laiyu Optoelectronic Technology Suzhou Co ltd
Priority date: 2022-12-14
Filing date: 2022-12-14
Publication date: 2023-03-31

Abstract

The application discloses a micro LED display device and a preparation method thereof, which belong to the technical field of micro display, the micro LED display device adopts a twice passivation process, and the side wall of an LED unit is protected by a first passivation layer, so that the increase of electric leakage caused by the generation of a surface state is avoided; then, the first passivation layer is directly used as a mask, a hole groove can be formed in the metal bonding layer without additionally arranging the mask, the process of removing the mask is not needed after the metal is etched, the influence of a photoresist removing process on the metal bonding layer is not needed to be considered, and therefore the selectable range of the bonding metal is wider; after the hole groove is formed, the second passivation layer is adopted to cover the side wall of the hole groove, so that the bonding metal exposed on the side wall can be covered, electrical isolation is formed, electric leakage is reduced, and the performance and reliability of the device are further guaranteed.

Description

MicroLED display device and preparation method thereof

Technical Field

The application belongs to the technical field of micro display, and particularly relates to a micro LED display device and a preparation method thereof.

Background

For a micro display LED (MicroLED) applied to the AR/VR field, the pixel density requirement is very high, and the general pixel size requirement is below 10um, even below 5 um. In order to obtain a micro led with such a pixel density, a monolithic integration method is generally adopted in a manufacturing process, that is, an entire epitaxial wafer is bonded with a CMOS driver by a bonding method (generally, metal bonding), and then a pixelation process is performed. The method carries out alignment of the LEDLED unit and the CMOS drive in a photoetching mode, so that the precision is extremely high. In order to utilize the high precision of the method to the maximum extent, the metal bonding is not patterned in advance, so in the subsequent pixelation process, the metal between the LED units needs to be etched to be electrically isolated, and the independent control of the single LED unit is realized.

In the conventional micro led process, after etching is completed, the mask is generally removed, and then a subsequent process is performed. In the process of removing the mask, the exposed sidewall of the bonding metal is inevitably affected, and the contact chemical substances, such as metal, react with the solution or gas, so that the overall structure is damaged, and the product performance and reliability are affected.

Disclosure of Invention

The purpose of the invention is as follows: the embodiment of the application provides a micro LED display device and a preparation method thereof, and aims to solve the technical problems that in the process of removing a mask in the existing micro LED process, the exposed bonding metal side wall is inevitably affected, the overall structure is damaged, and the product performance and reliability are affected.

The technical scheme is as follows: the preparation method of the MicroLED display device comprises the following steps:

providing a driving substrate, a metal bonding layer and LED units, wherein the metal bonding layer is arranged on the driving substrate, and a plurality of LED unit arrays are arranged on the metal bonding layer;

forming a first passivation layer covering the LED unit;

patterning the first passivation layer and forming a plurality of holes or grooves on the metal bonding layer by using the first passivation layer as a mask, wherein the holes or grooves are located between adjacent LED units, and the bottom of the holes or grooves exposes the driving substrate;

forming a second passivation layer covering the first passivation layer and filling the hole or groove;

etching the first passivation layer and the second passivation layer to expose at least the light emitting surface of the LED unit;

and forming a transparent electrode layer, wherein the transparent electrode layer covers the light-emitting surface and is electrically connected with the LED unit.

In some embodiments, the LED unit includes a step structure formed by etching an LED epitaxial layer, the step structure including a first doped semiconductor layer, a second doped semiconductor layer, and an active layer therebetween; the step structure at least makes the second doping type semiconductor layers of the adjacent LED units disconnected and electrically isolated from each other;

the light-emitting surface is positioned on the second doped semiconductor layer.

In some embodiments, the active layer may be a multiple quantum well structure, and is configured to confine electron and hole carriers to the quantum well region, and when the electron and the hole recombine, the carriers emit photons after radiative recombination, so as to convert electrical energy into light energy.

In some embodiments, the LED unit is a micro light emitting diode.

In some embodiments, the first and second doped semiconductor layers may include one or more layers based on II-VI materials such as ZnSe or ZnO or III-V materials such as GaN, alN, inN, inGaN, gaP, alInGaP, alGaAs, and alloys thereof.

In some embodiments, the LED units have a size of 0.1 to 5 microns and a pitch between adjacent LED units is 1 to 10 microns.

In some embodiments, the providing the driving substrate, the metal bonding layer and the LED unit includes:

providing an LED epitaxial layer, wherein the LED epitaxial layer is arranged on a substrate;

forming the metal bonding layer on the driving substrate and/or the LED epitaxial layer, and bonding the driving substrate and the LED epitaxial layer;

removing the substrate;

etching the LED epitaxial layer into the step structure;

the driving substrate includes a plurality of first contacts between adjacent ones of the LED units.

In some embodiments, when a plurality of holes or slots are formed on the metal bonding layer, leaving the bottom of the holes or slots exposing the first contacts;

etching the first passivation layer and the second passivation layer to expose the light emitting surface of the LED unit and the first contact;

the transparent electrode layer covers the light emitting surface and the hole or the groove to electrically connect the second doped semiconductor layer of the LED unit and the corresponding first contact, so that the LED unit is driven independently through the first contact.

removing the substrate;

etching the LED epitaxial layer into the step structure;

the driving substrate comprises a plurality of first contacts, the first contacts are located below the LED units, and the metal bonding layer is electrically connected with the first contacts and the first doped semiconductor layer.

In some embodiments, when a plurality of holes or grooves are formed on the metal bonding layer, the holes or grooves are spaced apart and electrically isolate the metal bonding layer under the adjacent LED units;

etching the first passivation layer and the second passivation layer to expose the light emitting surface of the LED unit;

the transparent electrode layer covers the light emitting surface of the adjacent LED unit to be electrically connected with the second doped semiconductor layer of the adjacent LED unit, so that the LED unit is driven independently through the first contact.

In some embodiments, forming the first passivation layer comprises:

and sequentially adopting atomic layer deposition and plasma chemical vapor deposition to deposit dielectric materials to form a laminated dielectric layer, wherein the laminated dielectric layer is the first passivation layer.

In some embodiments, the atomic layer deposition and the plasma chemical vapor deposition are alternated a plurality of times to form the stacked dielectric layers.

In some embodiments, the material of the first passivation layer may be selected to be an inorganic dielectric material and/or an organic dielectric material; and/or, the inorganic medium material is selected from SiO ₂ 、Si ₃ N ₄ 、Al ₂ O ₃ One or more of (a).

In some embodiments, the hole groove is formed by a metal etching process;

and when the hole groove is formed, the thickness of the first passivation layer is thinned to 20-300 nm.

Correspondingly, the micro LED display device of this application embodiment includes:

a drive substrate;

the metal bonding layer is arranged on the driving substrate, a plurality of holes or grooves are formed in the metal bonding layer in a penetrating mode, and the bottom of each hole or groove is exposed out of the driving substrate;

the LED units are arranged on the metal bonding layer in an array mode, and the holes or the grooves are located between the adjacent LED units;

a first passivation layer covering the LED unit and exposing the hole or groove;

a second passivation layer covering the first passivation layer and filling the hole or groove;

the first passivation layer and the second passivation layer at least expose the light emitting surface of the LED unit;

and the transparent electrode layer covers the light emergent surface and is electrically connected with the LED unit.

In some embodiments, the LED unit includes a step structure formed by etching an LED epitaxial layer, the step structure including a first doped semiconductor layer, a second doped semiconductor layer, and an active layer therebetween; the step structure at least disconnects and electrically isolates the second doped semiconductor layers of the adjacent LED units from each other;

the light emitting surface is located on the second doped semiconductor layer.

In some embodiments, the driving substrate includes a plurality of first contacts between adjacent ones of the LED units.

In some embodiments, the bottom of the hole or groove exposes the first contact, the first passivation layer and the second passivation layer also expose the first contact, and the transparent electrode layer covers the light emitting surface and the hole or groove to electrically connect the second doped semiconductor layer of the LED unit and the corresponding first contact, so that the LED unit is driven through the first contact alone.

In some embodiments, the driving substrate includes a plurality of first contacts under the LED unit, and the metal bonding layer electrically connects the first contacts and the first doping type semiconductor layer.

In some embodiments, the holes or slots space and electrically isolate metal bonding layers under adjacent of the LED units;

In some embodiments, the first passivation layer is: and the laminated dielectric layer is formed by adopting atomic layer deposition and plasma chemical vapor deposition in sequence.

In some embodiments, the first passivation layer is: and the laminated dielectric layer is formed by alternately carrying out atomic layer deposition and plasma chemical vapor deposition for multiple times.

In some embodiments, the material of the first passivation layer may be selected to be an inorganic dielectric material and/or an organic dielectric material; and/or, the inorganic medium material is selected from SiO ₂ 、Si ₃ N ₄ 、Al ₂ O ₃ One or more ofA variety of.

In some embodiments, the first passivation layer has a thickness of 20 to 300mm.

Has the beneficial effects that: compared with the prior art, the preparation method of the MicroLED display device comprises the following steps: providing a driving substrate, a metal bonding layer and LED units, wherein the metal bonding layer is arranged on the driving substrate, and a plurality of LED unit arrays are arranged on the metal bonding layer; forming a first passivation layer covering the LED unit; patterning the first passivation layer and forming a plurality of holes or grooves on the metal bonding layer by using the first passivation layer as a mask, wherein the holes or grooves are positioned between adjacent LED units, and the bottom of each hole or groove exposes the driving substrate; forming a second passivation layer covering the first passivation layer and filling the holes or the grooves; etching the first passivation layer and the second passivation layer to expose at least the light emitting surface of the LED unit; and forming a transparent electrode layer, wherein the transparent electrode layer covers the light emergent surface and is electrically connected with the LED unit. The method adopts a twice passivation process, and the side wall of the LED unit is protected by the first passivation layer, so that the increase of electric leakage caused by the generation of a surface state is avoided; then, the first passivation layer is directly used as a mask, a hole groove can be formed in the metal bonding layer without additionally arranging the mask, the process of removing the mask is not needed after the metal is etched, the influence of a photoresist removing process on the metal bonding layer is not needed to be considered, and therefore the selectable range of the bonding metal is wider; after the hole groove is formed, the side wall of the hole groove is covered by the second passivation layer, so that the bonding metal exposed on the side wall can be covered, electrical isolation is formed, electric leakage is reduced, and the performance and reliability of the device are guaranteed.

Compared with the prior art, the MicroLED display device of this application embodiment includes: a drive substrate; the metal bonding layer is arranged on the driving substrate, a plurality of holes or grooves are formed in the metal bonding layer in a penetrating mode, and the bottom of each hole or groove is exposed out of the driving substrate; the LED units are arranged on the metal bonding layer in an array mode, and the holes or the grooves are located between the adjacent LED units; the first passivation layer covers the LED unit and exposes the light-emitting surface and the hole or the groove of the LED unit; a second passivation layer covering the first passivation layer and filling the holes or the grooves; and the transparent electrode layer covers the light emergent surface and is electrically connected with the LED unit. The display device protects the side wall of the LED unit through the first passivation layer, and protects the bonding metal through the second passivation layer, so that the display device is not influenced by the process, the electric leakage is reduced, and the performance and the reliability of the display device are further guaranteed.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a top view of a MicroLED display device in a first embodiment of the present application;

FIG. 2 isbase:Sub>A schematic illustration ofbase:Sub>A MicroLED display device inbase:Sub>A first embodiment of the present application, taken along line A-A;

FIG. 3 is a schematic cross-sectional view of a driving substrate and an LED epitaxial layer in a first embodiment of the present application;

FIG. 4 is a schematic cross-sectional view of a first embodiment of the present application illustrating the formation of a metal bonding layer;

FIG. 5 is a schematic cross-sectional view of a bonding process in a first embodiment of the present application;

FIG. 6 is a schematic cross-sectional view of an LED unit formed in the first embodiment of the present application;

FIG. 7 is a schematic top view of a first embodiment of the present application forming an LED unit;

FIG. 8 is a schematic cross-sectional view of a first passivation layer formed in the first embodiment of the present application;

FIG. 9 is a schematic top view of a first passivation layer formed in the first embodiment of the present application;

FIG. 10 is a schematic cross-sectional view of a first embodiment of the present application illustrating a mask for patterning a first passivation layer;

FIG. 11 is a schematic top view of the state of FIG. 8 through the state of FIG. 10;

FIG. 12 is a schematic cross-sectional view of a hole groove formed in a metal bonding layer according to the first embodiment of the present application;

FIG. 13 is a schematic top view of the state of FIG. 10 through the state of FIG. 12;

FIG. 14 is a schematic cross-sectional view of a second passivation layer formed in the first embodiment of the present application;

FIG. 15 is a schematic top view of the state of FIG. 12 through the state of FIG. 14;

FIG. 16 is a schematic cross-sectional view of the first and second passivation layers after etching in the first embodiment of the present application;

FIG. 17 is a schematic top view of the state of FIG. 14 through the state of FIG. 16;

FIG. 18 is a schematic top view of the condition of FIG. 16 through the condition of FIG. 1;

fig. 19 is a schematic cross-sectional view of a MicroLED display device in a second embodiment of the present application;

FIG. 20 is a schematic cross-sectional view of a mask for patterning a first passivation layer in a second embodiment of the present application;

FIG. 21 is a schematic top view of a mask for patterning a first passivation layer according to a second embodiment of the present application;

FIG. 22 is a schematic cross-sectional view of a via hole formed in a metal bonding layer according to a second embodiment of the present application;

FIG. 23 is a schematic top view of the condition of FIG. 20 through the condition of FIG. 22;

FIG. 24 is a schematic cross-sectional view of a second passivation layer formed in a second embodiment of the present application;

FIG. 25 is a schematic cross-sectional view of the second embodiment of the present application after etching the first passivation layer and the second passivation layer;

fig. 26 is a schematic top view of the state of fig. 24 to the state of fig. 25;

reference numerals: 10-a drive substrate; 100-a first contact; 20-LED epitaxial layers; 200-an LED unit; 210-a first doped semiconductor layer; 220-an active layer; 230-a second doped semiconductor layer; 201-a light-emitting surface; 30-a substrate; 300-a metal bonding layer; 310-holes or slots; 400-a first passivation layer; 410-a first via; 500-a second passivation layer; 510-a second via; 520-a third via; 600-transparent electrode layer.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that, to be particularly noted, in the description of the present application, the meanings of the terms "on 8230, on" 8230, on "over" on "8230, should be interpreted in the broadest sense, meaning that the description containing these terms is interpreted to mean that" a component may be disposed on another component in direct contact, and that there may also be intermediate components or layers between the components ".

In addition, for the convenience of description, spatially relative terms such as "under 823030, below", "under 8230, below", "under 823030, below", "over" 8230, above "," over "at 8230, above", "over", "under", "upper", and the like, may also be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 or at other orientations) and the spatially relative descriptors used in this application interpreted accordingly as such.

The term "layer" as used in this application refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure or may extend over a localized area of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure or therebetween. The layers may extend horizontally, vertically, and/or along a tapered surface. A layer may comprise multiple layers. For example, the semiconductor layer may include one or more doped or undoped semiconductor layers, and may be of the same or different materials.

In the description of the present application, "micro" LED, "micro" devices are used to refer to descriptive dimensions of certain devices or structures according to embodiments of the present application. The term "micro" device or structure as used herein is intended to mean a scale of 100 nanometers to 100 micrometers. However, it should be understood that embodiments of the present invention are not necessarily limited thereto, and that certain aspects of the embodiments may be applicable to larger and possibly smaller size scales.

The applicant has noticed that in the conventional micro led process, a photoresist or a dielectric layer is generally used as a mask, and a Reactive Ion Etching (RIE), inductively Coupled Plasma (ICP) etching or Ion Beam Etching (IBE) is used to etch metal. Because bonding metals are generally composed of multiple layers, the preferred etch is performed using a method that does not significantly differ in the etch rate of the metal in each layer, with IBE being used more often. In these etching processes, the semiconductor material is generally etched first, then the metal isolation etching is completed, and then the mask is generally removed after the etching is completed, and then the dielectric layer deposition is performed, so that the semiconductor sidewall is passivated, and the etched metal sidewall is wrapped to form the electrical isolation. The common degumming solution reacts with certain metals, so that the metal bonding layer is influenced in the mask removing process, the selectable range of the bonding metals is narrowed, and the optimal performance is not obtained; the oxygen plasma photoresist removing method also causes the bond metal to react with oxygen, so that the performance of the bond metal is changed to a certain extent.

In view of the above, embodiments of the present application provide a micro led display device and a method for manufacturing the same, so as to overcome at least one of the above-mentioned drawbacks.

The embodiments of the present application describe a micro led display device and a method for making the device. The Micro-LED display device of the present application uses a Micro-LED (Micro light-emitting diode) structure, and the size of the Micro-LED is reduced to 100 nm to 100 μm. In Micro-LEDs, the array of Micro-LEDs is highly integrated, and the distance of the LED units of the Micro-LEDs in the array is further reduced to 5 microns. The Micro-LED is displayed in a mode that the Micro-LED with the size of 5 microns or even smaller is connected to a driving substrate, and the light emitting brightness of each Micro-LED is accurately controlled. The preparation method is suitable for the Micro-LED structure, and the Micro-LED display device with the Micro size can be prepared.

Specifically, referring to fig. 1, fig. 2 and fig. 19, the micro LED display device according to the embodiment of the present disclosure includes a driving substrate 10, a metal bonding layer 300, an LED unit 200, a first passivation layer 400, a second passivation layer 500 and a transparent electrode layer 600. The metal bonding layer 300 is disposed on the driving substrate 10, the metal bonding layer 300 has a plurality of holes or grooves penetrating therethrough, and the bottoms of the holes or grooves expose the driving substrate 10; the plurality of LED units 200 are arranged in an array on the metal bonding layer 300, and the holes or slots are located between adjacent LED units 200; the first passivation layer 400 covers the LED unit 200 and exposes the light emitting surface 201 and the hole or groove of the LED unit 200; the second passivation layer 500 covers the first passivation layer 400 and fills the holes or grooves; the transparent electrode layer 600 covers the light emitting surface 201 and is electrically connected to the LED unit 200.

It can be understood that the micro LED display device protects the sidewalls of the LED units 200 through the first passivation layer 400, and protects the metal bonding layer 300 through the second passivation layer 500, so that the metal bonding layer is not affected by the process, thereby reducing the leakage current, and further ensuring the performance and reliability of the device.

In some embodiments, the driving substrate 10 may include a semiconductor material such as silicon, silicon carbide, silicon nitride, germanium, gallium arsenide, cobalt phosphide. In some embodiments, the drive substrate 10 may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. In some embodiments, the driving substrate 10 may have a driving circuit formed therein, and the driving substrate 10 may be a CMOS (Complementary Metal Oxide Semiconductor) backplane or a TFT glass substrate. The driving circuit supplies an electrical signal to the LED unit 200 to control the brightness. In some embodiments, the driver circuit may comprise an active matrix driver circuit, wherein each individual LED unit 200 corresponds to a separate driver.

In some embodiments, the LED unit 200 includes a step structure formed by etching the LED epitaxial layer 20, the step structure including a first doped semiconductor layer 210, a second doped semiconductor layer 230, and an active layer 220 therebetween; the stepped structure at least disconnects and electrically isolates the second doping type semiconductor layers 230 of the adjacent LED units 200 from each other; the light emitting surface 201 is located on the second doped semiconductor layer 230, and the light emitting surface 201 may be located at the top of the step structure.

Referring to fig. 6 and 20, the first doped semiconductor layer 210 is disposed on the metal bonding layer 300, the active layer 220 is disposed on a side of the first doped semiconductor layer 210 away from the metal bonding layer 300, and the second doped semiconductor layer 230 is disposed on a side of the active layer 220 away from the first doped semiconductor layer 210.

In some embodiments, the driving substrate 10 includes a plurality of first contacts 100, the first contacts 100 being located between adjacent LED units 200.

In some embodiments, the hole or the groove is specifically a hole 310, the first contact 100 is exposed at the bottom of the hole 310, and the transparent electrode layer 600 covers the light emitting surface 201 and the hole 310 to electrically connect the second doped semiconductor layer 230 of the LED unit 200 and the corresponding first contact 100, so that the LED unit 200 is driven by the first contact 100 alone.

In some embodiments, the first doped semiconductor layers 210 of adjacent LED cells 200 are disconnected and electrically isolated from each other; the first contact 100 is positioned under the LED cell 200, and the metal bonding layer 300 electrically connects the first contact 100 and the first doped semiconductor layer 210.

In some embodiments, the holes or slots are embodied as slots 310, the slots 310 spacing and electrically isolating the metal bonding layer 300 under adjacent LED cells 200; the transparent electrode layer 600 covers the light emitting surface 201 of the adjacent LED unit 200 and the common contact of the driving substrate 10 to electrically connect the second doping type semiconductor layers 230 of the adjacent LED units 200, so that the LED units 200 are driven individually through the first contacts 100.

Specifically, referring to fig. 1 and fig. 2 again, in the first embodiment of the present application, the driving substrate 10 includes a plurality of first contacts 100, the plurality of first contacts 100 are arranged in an array, and the first contacts 100 are located between adjacent LED units 200.

The metal bonding layer 300 is disposed on the driving substrate 10, and is used for bonding the LED epitaxial layers 20 to the driving substrate 10 and electrically connecting the first doped semiconductor layers 210 of the LED units 200. The bonding metal of the metal bonding layer 300 includes Au, sn, in, cu, or Ti.

Referring to fig. 12 and 13, a plurality of holes 310 are penetratingly formed in the metal bonding layer 300, the plurality of holes 310 are arranged in an array, the holes 310 are disposed between the adjacent LED units 200 and are opposite to the first contacts 100, and the bottom of the holes 310 expose the driving substrate 10 and expose the corresponding first contacts 100. In the first embodiment, the hole 310 may be a circular hole, and the metal bonding layer 300 is penetrated at the hole 310 to expose the sidewall.

The plurality of LED units 200 are arranged in an array on the metal bonding layer 300 to be integrally connected with the driving substrate 10 through the metal bonding layer 300, and the first doped semiconductor layers 210 of the LED units 200 are electrically connected to each other through the metal bonding layer 300.

The first passivation layer 400 covers the LED unit 200, and the first passivation layer 400 exposes the light emitting surface 201 and the hole 310 of the LED unit 200, that is, the first passivation layer 400 covers at least the sidewall of the LED unit 200, so as to protect the sidewall of the LED unit 200 and prevent the sidewall from forming a surface state during the manufacturing process.

The second passivation layer 500 covers the sidewalls of the first passivation layer 400 and the hole 310 to protect the sidewalls formed by etching the metal bonding layer 300, so as to prevent the entire structure from being damaged, thereby ensuring the performance and stability of the product.

The transparent electrode layer 600 covers the light emitting surface 201 and the hole or groove to electrically connect the LED unit 200 and the corresponding first contact 100 of the driving substrate 10, so that the LED unit 200 is driven by the first contact 100 alone.

Specifically, referring to fig. 19, in the second embodiment of the present application, the driving substrate 10 includes a plurality of first contacts 100, the plurality of first contacts 100 are arranged in an array, and the first contacts 100 are located below the LED unit 200 and are opposite to the LED unit 200; in addition, the driving substrate 10 may further include a common contact (not shown in the drawings), which is disposed near an edge of the driving substrate 10.

The metal bonding layer 300 is disposed on the driving substrate 10, and is used to bond the LED epitaxial layer 20 to the driving substrate 10 and to electrically connect the first contact 100 and the first doped semiconductor layer 210 of the LED unit 200. The bonding metal of the metal bonding layer 300 includes Au, sn, in, cu, or Ti.

Referring to fig. 22 and 23, a plurality of grooves 310 are penetratingly formed in the metal bonding layer 300, the plurality of grooves 310 are arranged in an array and spaced between the adjacent LED units 200, the bottom of the groove 310 exposes the driving substrate 10, and the groove 310 may be a through groove. In the second embodiment, the groove 310 is a groove penetrating through the metal bonding layer 300 in the thickness direction, the groove 310 forms a gap on the metal bonding layer 300, the metal bonding layer 300 is divided into a plurality of metal bonding portions arranged in an array, the metal bonding portions are correspondingly arranged below the LED units 200 one by one, and the adjacent metal bonding portions are arranged at intervals through the groove 310.

In the second embodiment, a plurality of LED units 200 are arrayed on the metal bonding layer 300 to be integrally connected with the driving substrate 10 through the metal bonding layer 300, and the first doped semiconductor layer 210 of each LED unit 200 is electrically connected with the first contact 100 through a metal bonding portion separately formed by the metal bonding layer 300.

The first passivation layer 400 covers the LED unit 200, and the first passivation layer 400 exposes the light emitting surface 201 and the groove 310 of the LED unit 200, that is, the first passivation layer 400 covers at least the sidewall of the LED unit 200, so as to protect the sidewall of the LED unit 200 and prevent the sidewall from forming a surface state during the manufacturing process.

The second passivation layer 500 covers the sidewalls of the first passivation layer 400 and the trench 310 to protect the sidewalls formed by etching the metal bonding layer 300, so as to prevent the entire structure from being damaged, thereby ensuring the performance and stability of the product.

The transparent electrode layer 600 covers the light emitting surface 201 of each LED unit to electrically connect the second doping type semiconductor layers 230 of each LED unit 200, and may electrically connect the second doping type semiconductor layers 230 with the common contact of the driving substrate 10, so that the LED units 200 are individually driven through the first contacts 100.

In some embodiments, the first passivation layer 400 is: and the laminated dielectric layer is formed by adopting atomic layer deposition and plasma chemical vapor deposition in sequence.

Specifically, the material of the first passivation layer 400 may be selected to be SiO ₂ ，Si ₃ N ₄ ，Al ₂ O ₃ Etc., or other feasible organic dielectric materials. Since the dielectric material is also etched by the ion beam at the same time, the thickness of the dielectric material should be greater than the thickness etched away in the etching process. After the etching is completed, the thickness of the dielectric layer, i.e., the thickness of the first passivation layer 400, is preferably 20-300 nm. In this embodiment, the dielectric layer formed by Atomic Layer Deposition (ALD) has a very high compactness, is not easily etched, and can form a better passivation effect on the sidewall of the LED unit 200, and the dielectric layer can be thickened by Plasma Enhanced Chemical Vapor Deposition (PECVD), so that the formed laminated dielectric layer can enable the finally left dielectric layer to be etched on the ALD dielectric layer, thereby greatly improving the consistency of the product and meeting the thickness requirement of the first passivation layer 400.

Further, in some embodiments, the first passivation layer 400 is: and the laminated dielectric layer is formed by alternately carrying out atomic layer deposition and plasma chemical vapor deposition for multiple times. For example, ALD/PECVD/ALD/PECVD deposition processes may be alternately performed to form the first passivation layer 400 as desired.

Correspondingly, the embodiment of the application also provides a preparation method of the micro LED display device, which is characterized by comprising the following steps:

providing a driving substrate 10, a metal bonding layer 300 and LED units 200, wherein the metal bonding layer 300 is arranged on the driving substrate 10, and a plurality of LED units 200 are arrayed on the metal bonding layer 300;

forming a first passivation layer 400, the first passivation layer 400 covering the LED unit 200;

patterning the first passivation layer 400 and forming a plurality of holes or grooves on the metal bonding layer 300 with the first passivation layer 400 as a mask, the holes or grooves being located between the adjacent LED units 200, and the bottom of the holes or grooves exposing the driving substrate 10;

forming a second passivation layer 500, the second passivation layer 500 covering the first passivation layer 400 and the sidewalls of the hole or trench;

etching the first passivation layer 400 and the second passivation layer 500 to expose at least the light emitting surface 201 of the LED unit 200;

a transparent electrode layer 600 is formed, and the transparent electrode layer 600 covers the light emitting surface 201 and is electrically connected to the LED unit 200.

It can be understood that, the preparation method adopts a process of passivation twice, and the first passivation layer 400 protects the side wall of the LED unit 200 to prevent the surface state from generating and increasing the leakage current; then, the first passivation layer 400 is directly used as a mask, a hole or a groove can be formed in the metal bonding layer 300 without additionally arranging a mask, a mask removing process is not needed after metal etching, and the influence of a photoresist removing process on the metal bonding layer 300 is not needed to be considered, so that the selectable range of the bonding metal is wider; after the hole or the groove is formed, the sidewall of the hole or the groove is covered by the second passivation layer 500, so that the bonding metal exposed on the sidewall can be covered to form electrical isolation, reduce electric leakage, and further guarantee the performance and the reliability of the device.

Specifically, the LED unit 200 includes a step structure formed by etching the LED epitaxial layer 20, and the step structure includes a first doped semiconductor layer 210, a second doped semiconductor layer 230, and an active layer 220 therebetween; the stepped structure disconnects and electrically isolates at least the second doping type semiconductor layers 230 of the adjacent LED units 200 from each other; the light emitting surface 201 is located on the second doped semiconductor layer 230, and specifically, the light emitting surface 201 is located at the top of the step structure.

In a first embodiment, referring to fig. 3, a driving substrate 10, a metal bonding layer 300 and an LED unit 200 are provided, including: providing an LED epitaxial layer 20, wherein the LED epitaxial layer 20 is arranged on a substrate 30; wherein the substrate 30 is a semiconductor material such as silicon, gaN, siC, etc., or the substrate 30 is a non-conductive material such as sapphire or glass; the LED epitaxial layers generally include an N-doped layer, a P-doped layer, and a multiple quantum well layer.

Referring to fig. 4, a metal bonding layer 300 is formed on the driving substrate 10 and the LED epitaxial layer 20, respectively, and the driving substrate 10 and the LED epitaxial layer 20 are bonded to expose the substrate 30.

Referring to fig. 5, the substrate 30 of the bonded wafer may be removed by a dry method or a wet method.

Referring to fig. 6 and 7, the LED epitaxial layer 20 may be etched by a dry method or a wet method to form a step structure, i.e., a plurality of LED units 200 arranged in an array are etched, the LED units 200 are arranged in an array on the metal bonding layer 300, and thus the first doped semiconductor layers 210 of adjacent LED units 200 are electrically connected to each other through the metal bonding layer 300; wherein the first contact 100 of the driving substrate 10 is located between the adjacent LED units 200.

Further, as shown in fig. 8 and 9, an inorganic or organic dielectric material is used to passivate the sidewall of the LED unit 200 for the first time, so as to form a first passivation layer 400, where the thickness of the first passivation layer 400 is greater than the thickness of the first passivation layer 400 after the metal bonding layer 300 is etched, and the material and the thickness of the first passivation layer 400 may be designed to match the subsequent metal etching process.

Specifically, the material of the first passivation layer 400 may be selected to be SiO ₂ ，Si ₃ N ₄ ，Al ₂ O ₃ Etc., or other feasible organic dielectric materials, e.g., polyimide, SU-8 photoresist, or other photo-patternable polymers. The conventional dielectric layer deposition methods include Plasma Enhanced Chemical Vapor Deposition (PECVD), atomic Layer Deposition (ALD), and the like, and the dielectric layer deposited by the ALD method has very high compactness and is not easy to etch, so that the material for the first passivation can adopt a structure of multiple dielectric layers, for example, a dielectric layer is deposited by ALD (the dielectric layer deposited by ALD has a better passivation effect on the side wall of the semiconductor), and then a thickened dielectric layer is deposited by PECVD. Of course, several pairs of dielectric layers may be used as the first passivation layer, such as ALD/PECVD/ALD/PECVD, etc. Because the etching rate of the ALD medium layer is low, the finally remained medium layer can be stopped at the ALD medium layer through the design of the laminated medium layer, and the consistency of products is greatly improved.

Referring to fig. 10 and 11, the first passivation layer 400 is patterned to form a plurality of first through holes 410 penetrating the first passivation layer 400 and arranged in an array, wherein the first through holes 410 are disposed above the first contacts 100.

Referring to fig. 12 and 13, the metal bonding layer 300 is etched through the surface dielectric layer of the driving substrate 10 by using the first passivation layer 400 as a mask, so as to form holes 310 arranged in an array, wherein the first contacts 100 are exposed at the bottoms of the holes 310. The metal etching process can adopt conventional ion beam etching or inductively coupled plasma etching and reactive ion etching. In forming the hole 310, the thickness of the first passivation layer 400 is thinned to 20 to 300nm.

Referring to fig. 14 and 15, after the metal bonding layer 300 is etched, a second passivation is directly performed without a mask removal process, an inorganic or organic dielectric material is used to cover the bonding metal sidewall exposed by the hole 310 to form a second passivation layer 500, and the sidewall of the hole 310 is electrically isolated to prevent short circuit of the subsequent metal trace, and simultaneously protect the metal with high reactivity to improve the compatibility of the subsequent process.

Referring to fig. 16 and 17, the dielectric layer above the step structure and the first contact 100 of the driving substrate 10 is opened and etched to form a second through hole 510 and a third through hole 520, such that the second through hole 510 exposes the first contact 100 and the third through hole 520 exposes the light emitting surface 201 of the LED unit 200.

Referring to fig. 2 and 18, a transparent electrode layer 600 is deposited, and the transparent electrode layer 600 covers the light emitting surface 201 and the hole 310 to electrically connect the second doped semiconductor layer 230 of the LED unit 200 and the corresponding first contact 100, so that the LED unit 200 is driven independently through the first contact 100. The transparent electrode layer 600 is made of a transparent material, such as ITO.

Referring to fig. 19, unlike the first embodiment, in the second embodiment, the first contact 100 of the driving substrate 10 is provided below the LED unit 200, and the first contact 100 is electrically connected to the first doped semiconductor layer 210 of the LED unit 200 through the metal bonding layer 300.

The sidewalls of the LED unit 200 are passivated for the first time by using an inorganic or organic dielectric material to form a first passivation layer 400, where the thickness of the first passivation layer 400 is greater than the thickness of the first passivation layer 400 after the metal bonding layer 300 is etched, and the material and the thickness of the first passivation layer 400 may be designed to match a subsequent metal etching process.

Specifically, the material of the first passivation layer 400 may be selected to be SiO ₂ ，Si ₃ N ₄ ，Al ₂ O ₃ Etc., or other feasible organic dielectric materials, e.g., polyimide, SU-8 photoresist, or other photo-patternable polymers. The conventional dielectric layer deposition methods include Plasma Enhanced Chemical Vapor Deposition (PECVD), atomic Layer Deposition (ALD), and the like, and the dielectric layer deposited by the ALD method has very high compactness and is not easy to etch, so that the material for the first passivation can adopt a structure of multiple dielectric layers, for example, a dielectric layer is deposited by ALD (the dielectric layer deposited by ALD has a better passivation effect on the side wall of the semiconductor), and then a thickened dielectric layer is deposited by PECVD. Of course, several pairs of dielectric layers may be used as the first passivation layer, such as ALD/PECVD/ALD/PECVD, etc. Because the etching rate of the ALD dielectric layer is low, the finally remained dielectric layer can be stopped at the ALD dielectric layer through the design of the laminated dielectric layer, and the consistency of products is greatly improved.

Further, referring to fig. 20 and 21, the first passivation layer 400 is patterned to form a plurality of first through holes 410 penetrating the first passivation layer 400 and arranged in an array, in the second embodiment, the first through holes 410 are through-groove structures, and the through-groove structures are used for spacing the first passivation layer 400 covering the adjacent LED units 200.

Referring to fig. 22 and 23, the metal bonding layer 300 is etched through the surface dielectric layer of the driving substrate 10 by using the first passivation layer 400 as a mask, so as to form the grooves 310 arranged in an array. The metal etching process can adopt conventional ion beam etching or inductively coupled plasma etching and reactive ion etching. The grooves 310 are located between the adjacent LED units 200, and the bottom of the grooves 310 exposes the driving substrate 10. Specifically, the groove 310 is a groove penetrating through the metal bonding layer 300 in the thickness direction, the groove 310 forms a gap on the metal bonding layer 300, the metal bonding layer 300 is divided into a plurality of metal bonding portions arranged in an array, the metal bonding portions are arranged below the LED units 200 in a one-to-one correspondence manner, and adjacent metal bonding portions are arranged at intervals through the groove 310. The thickness of the first passivation layer 400 is thinned to 20 to 300nm during the formation of the trench 310.

As shown in fig. 24, after the metal bonding layer 300 is etched, a second passivation is directly performed without a mask removal process, and inorganic or organic dielectric materials are used to cover the exposed sidewall of the bonding metal in the trench 310 to form a second passivation layer 500, so as to electrically isolate the sidewall of the trench 310, thereby preventing the subsequent metal traces from short-circuiting and the like, and simultaneously protect the metal with high reactivity, thereby improving the compatibility of the subsequent process.

Referring to fig. 25 and 26, the dielectric layer above the step structure and the common contact of the driving substrate 10 is opened and etched, i.e., the first passivation layer 400 and the second passivation layer 500 are etched to form a third through hole 520, and the light emitting surface 201 of the LED unit 200 is exposed by the third through hole 520.

Referring to fig. 19 again, a transparent electrode layer 600 is deposited, the transparent electrode layer 600 covers the light emitting surface 201 of each LED unit 200 to electrically connect the second doped semiconductor layer 230 of each LED unit 200, and further connects the second doped semiconductor layer 230 with the common contact of the driving substrate 10, so that the LED units 200 are driven individually through the first contacts 100. The transparent electrode layer 600 is made of a transparent material, such as ITO.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The micro led display device and the manufacturing method thereof provided in the embodiments of the present application are described in detail above, and specific examples are applied to explain the principle and the embodiments of the present application, and the description of the embodiments above is only used to help understanding the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A preparation method of a MicroLED display device is characterized by comprising the following steps:

providing a driving substrate (10), a metal bonding layer (300) and LED units (200), wherein the metal bonding layer (300) is arranged on the driving substrate (10), and a plurality of LED units (200) are arranged on the metal bonding layer (300) in an array manner;

forming a first passivation layer (400), the first passivation layer (400) covering the LED unit (200);

patterning the first passivation layer (400) and forming a plurality of holes or grooves on the metal bonding layer (300) with the first passivation layer (400) as a mask, the holes or grooves being located between adjacent LED units (200), the bottom of the holes or grooves exposing the driving substrate (10);

forming a second passivation layer (500), the second passivation layer (500) covering the first passivation layer (400) and filling the holes or trenches;

etching the first passivation layer (400) and the second passivation layer (500) to expose at least a light exit surface (201) of the LED unit (200);

and forming a transparent electrode layer (600), wherein the transparent electrode layer (600) covers the light emitting surface (201) and is electrically connected with the LED unit (200).

2. The method of fabricating a MicroLED display device according to claim 1, wherein the LED unit (200) comprises a step structure formed by etching an LED epitaxial layer (20), the step structure comprising a first doped semiconductor layer (210), a second doped semiconductor layer (230) and an active layer (220) therebetween; the step structure at least disconnects and electrically isolates the second doped semiconductor layers (230) of the adjacent LED units (200) from each other;

the light-emitting surface (201) is located on the second doped semiconductor layer (230).

3. A method of manufacturing a micro LED display device according to claim 2, wherein the providing a driving substrate (10), a metal bonding layer (300) and an LED unit (200) comprises:

providing an LED epitaxial layer (20), the LED epitaxial layer (20) being arranged on a substrate (30);

forming the metal bonding layer (300) on the driving substrate (10) and/or the LED epitaxial layer (20), and bonding the driving substrate (10) and the LED epitaxial layer (20);

removing the substrate (30);

etching the LED epitaxial layer (20) into the step structure;

the driving substrate (10) comprises a plurality of first contacts (100), the first contacts (100) being located between adjacent LED units (200).

4. A method of making a micro led display device according to claim 3, wherein when forming a plurality of holes or trenches on said metal bonding layer (300), leaving the bottom of said holes or trenches exposed to said first contact (100);

etching the first passivation layer (400) and the second passivation layer (500) to expose the light exit surface (201) of the LED unit (200) and the first contact (100);

the transparent electrode layer (600) covers the light emitting surface (201) and the hole or the groove to electrically connect the second doped semiconductor layer (230) of the LED unit (200) with the corresponding first contact (100), so that the LED unit (200) is driven by the first contact (100) alone.

5. A method of manufacturing a micro LED display device according to claim 2, wherein the providing a driving substrate (10), a metal bonding layer (300) and an LED unit (200) comprises:

removing the substrate (30);

etching the LED epitaxial layer (20) into the step structure;

the driving substrate (10) comprises a plurality of first contacts (100), the first contacts (100) are positioned below the LED units (200), and the metal bonding layer (300) is electrically connected with the first contacts (100) and the first doping type semiconductor layer (210).

6. A method of fabricating a MicroLED display device according to claim 5, wherein when forming a plurality of holes or trenches in the metal bonding layer (300), the holes or trenches are spaced apart and electrically isolate the metal bonding layer (300) under adjacent LED cells (200);

etching the first passivation layer (400) and the second passivation layer (500) to expose the light exit surface (201) of the LED unit (200);

the transparent electrode layer (600) covers the light emitting surface (201) of the adjacent LED unit (200) to electrically connect the second doped semiconductor layers (230) of the adjacent LED units (200), so that the LED units (200) are driven independently through the first contact (100).

7. The method of fabricating a MicroLED display device according to claim 1, wherein forming the first passivation layer (400) comprises:

and sequentially adopting atomic layer deposition and plasma chemical vapor deposition to deposit dielectric materials to form a laminated dielectric layer, wherein the laminated dielectric layer is the first passivation layer (400).

8. A method of fabricating a MicroLED display device according to claim 7, wherein the atomic layer deposition and the plasma chemical vapor deposition are alternated a plurality of times to form the stacked dielectric layers.

9. A method of manufacturing a MicroLED display device according to claim 7, wherein the material of the first passivation layer (400) is selected from an inorganic dielectric material and/or an organic dielectric material; and/or, the inorganic medium material is selected from SiO ₂ 、Si ₃ N ₄ 、Al ₂ O ₃ One or more of (a).

10. A method of fabricating a micro led display device according to any one of claims 1 to 9, wherein the holes or trenches are formed by a metal etching process;

before the holes or the grooves are formed, the thickness of the first passivation layer (400) is reduced to 20-300 nm.

11. A MicroLED display device, comprising:

a drive substrate (10);

the metal bonding layer (300), the metal bonding layer (300) is arranged on the driving substrate (10), the metal bonding layer (300) is penetratingly provided with a plurality of holes or grooves, and the bottoms of the holes or grooves are exposed out of the driving substrate (10);

a plurality of LED units (200) arranged in an array on the metal bonding layer (300), wherein the holes or slots are positioned between the adjacent LED units (200);

a first passivation layer (400), the first passivation layer (400) covering the LED unit (200) and exposing the hole or groove;

a second passivation layer (500), the second passivation layer (500) covering the first passivation layer (400) and filling the holes or trenches;

the first passivation layer (400) and the second passivation layer (500) expose at least a light emitting surface of the LED unit (200);

the transparent electrode layer (600) covers the light emitting surface (201) and is electrically connected with the LED unit (200).

12. A micro LED display device according to claim 11, wherein the LED cell (200) comprises a stepped structure formed by etching an LED epitaxial layer (20), the stepped structure comprising a first doped semiconductor layer (210), a second doped semiconductor layer (230) and an active layer (220) therebetween; the step structure at least disconnects and electrically isolates the second doped semiconductor layers (230) of the adjacent LED units (200) from each other;

13. A micro LED display device according to claim 12, wherein the driving substrate (10) comprises a plurality of first contacts (100), the first contacts (100) being located between adjacent LED units (200).

14. A micro LED display device according to claim 13, wherein the bottom of the hole or trench exposes the first contact (100), the first passivation layer (400) and the second passivation layer (500) also expose the first contact (100), and the transparent electrode layer (600) covers the light exit surface (201) and the hole or trench to electrically connect the second doped semiconductor layer (230) of the LED unit (200) with the corresponding first contact (100), such that the LED unit (200) is driven individually through the first contact (100).

15. A micro LED display device according to claim 12, wherein the driving substrate (10) comprises a plurality of first contacts (100), the first contacts (100) being located below the LED cells (200), the metal bonding layer (300) electrically connecting the first contacts (100) and the first doped semiconductor layer (210).

16. A micro LED display device according to claim 15, wherein the holes or trenches space and electrically isolate the metal bonding layer (300) under adjacent LED cells (200);

the transparent electrode layer (600) covers the light emitting surface (201) of the adjacent LED unit (200) to electrically connect the second doped semiconductor layer (230) of the adjacent LED unit (200), so that the LED unit (200) is driven independently through the first contact (100).

17. A micro led display device according to claim 11, wherein the first passivation layer (400) is: and the laminated dielectric layers are formed by adopting atomic layer deposition and plasma chemical vapor deposition in sequence.

18. A micro led display device according to claim 17, wherein the first passivation layer (400) is: and the laminated dielectric layer is formed by alternately carrying out atomic layer deposition and plasma chemical vapor deposition for multiple times.

19. A micro led display device according to claim 17, wherein the material of the first passivation layer (400) is selected from an inorganic dielectric material and/or an organic dielectric material; and/or, the inorganic medium material is selected from SiO ₂ 、Si ₃ N ₄ 、Al ₂ O ₃ One or more of (a).

20. A micro led display device according to any of claims 11 to 19, wherein the first passivation layer (400) has a thickness of 20 to 300mm.