CN115878510A - Page table modifying method, page table verifying method, page table modifying device, page table verifying device and electronic equipment - Google Patents

Page table modifying method, page table verifying method, page table modifying device, page table verifying device and electronic equipment Download PDF

Info

Publication number
CN115878510A
CN115878510A CN202211634598.0A CN202211634598A CN115878510A CN 115878510 A CN115878510 A CN 115878510A CN 202211634598 A CN202211634598 A CN 202211634598A CN 115878510 A CN115878510 A CN 115878510A
Authority
CN
China
Prior art keywords
page table
level
virtual address
entry
base address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211634598.0A
Other languages
Chinese (zh)
Inventor
杨振
吴敌
陈玉龙
张攀勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu Haiguang Integrated Circuit Design Co Ltd
Original Assignee
Chengdu Haiguang Integrated Circuit Design Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chengdu Haiguang Integrated Circuit Design Co Ltd filed Critical Chengdu Haiguang Integrated Circuit Design Co Ltd
Priority to CN202211634598.0A priority Critical patent/CN115878510A/en
Publication of CN115878510A publication Critical patent/CN115878510A/en
Pending legal-status Critical Current

Links

Images

Abstract

The embodiment of the application discloses a page table modifying method, a page table verifying method, a page table modifying device, a page table verifying device and electronic equipment, relates to the technical field of processors, and aims to improve the efficiency of verifying the characteristics of the processors and/or the attributes of the page tables. The method comprises the following steps: applying for a first virtual address space and a second virtual address space; wherein the first virtual address space is mapped to a first physical address space by a first page table, and the second virtual address space is mapped to a second physical address space by a second page table; writing a base address of an m-level page table in the first page table into a page table entry of an n-level page table in the second page table to form a third page table; wherein m is an integer greater than or equal to 1 and less than or equal to the number of stages of the first page table; n is an integer greater than or equal to m and less than or equal to the number of stages of the second page table; modifying the first page table according to the third page table. The present application is applicable to validating a processor and/or a page table.

Description

Page table modifying method, page table verifying method, page table modifying device, page table verifying device and electronic equipment
Technical Field
The present application relates to the field of processor technologies, and in particular, to a page table modification method, a page table verification device, an electronic device, and a readable storage medium.
Background
Paging has an important role in modern processors and operating systems. Most processors already support a paging mechanism, the basic task of paging is to map virtual addresses in a process to physical addresses, the mapping is controlled by an operating system, a continuous virtual address space is provided for a user application program, and the functions of inter-process memory isolation and security can be achieved.
In the verification work of the processor characteristics or the page table attributes, problems of changing the page table and the like can be encountered, and the page table is stored in a physical memory and managed by an operating system, so that the modification process of the page table is complex in the verification work, and the verification efficiency is low.
Disclosure of Invention
In view of the above, embodiments of the present disclosure provide a method for modifying a page table, a method for verifying a page table, an apparatus, an electronic device, and a readable storage medium, which facilitate improving efficiency of verifying attributes of a page table and/or characteristics of a processor.
In a first aspect, an embodiment of the present application provides a method for modifying a page table, including: applying for a first virtual address space and a second virtual address space; wherein the first virtual address space is mapped to a first physical address space by a first page table, and the second virtual address space is mapped to a second physical address space by a second page table; writing a base address of an m-th level page table in the first page table into a page table entry of an n-th level page table of the second page table to form a third page table; wherein m is an integer greater than or equal to 1 and less than or equal to the number of stages of the first page table; n is an integer greater than or equal to m and less than or equal to the number of stages of the second page table; modifying the first page table according to the third page table.
According to a specific implementation manner of the embodiment of the present application, applying for the first virtual address space and the second virtual address space includes: and applying for the first virtual address space and the second virtual address space through a dynamic memory allocation function.
According to a specific implementation manner of the embodiment of the present application, the writing a base address of an m-th level page table in the first page table into a page table entry of an n-th level page table in the second page table to form the third page table includes: acquiring a base address of an m-level page table in a first page table; writing a base address of the m-th stage page table into a page table entry of an n-th stage page table of the second page table to form a third page table; the third page table sequentially comprises a first page table to an nth page table of the second page table, an mth page table of the first page table, and a t-level page table after the mth page table in the first page table; wherein t is a difference value obtained by subtracting n from the number of the second page table and subtracting 1 from the number of the second page table, wherein t is greater than or equal to 0; the modifying the first page table according to the third page table includes: writing data to a page table entry in an m + t +1 level page table of the first page table to modify the first page table, according to the third page table.
According to a specific implementation manner of the embodiment of the present application, the obtaining a base address of an mth-level page table in the first page table includes: acquiring a base address of the first page table through a kernel driving module; acquiring a base address of an m-level page table in the first page table according to the base address of the first page table; the writing the base address of the m-th stage page table into a page table entry of an n-th stage page table of the second page table includes: acquiring a base address of the second page table through the kernel driving module; acquiring the address of a page table entry of an nth-level page table in the second page table according to the base address of the second page table; and writing the base address of the m-level page table into the page table entry of the n-level page table of the second page table according to the address of the page table entry of the n-level page table.
According to a specific implementation manner of the embodiment of the present application, the number of stages of the first page table is 4, and the number of stages of the second page table is four; m and n are equal to three; the writing the base address of the m-th level page table into a page table entry of an n-th level page table of the second page table includes: and writing the base address of the third-stage page table of the first page table into a page table entry of the third-stage page table of the second page table.
According to a specific implementation manner of the embodiment of the present application, the writing, according to the third page table, data to a page table entry in an m + t + 1-th level page table of the first page table includes: determining a first virtual address range; wherein the first virtual address range corresponds to an m + t +1 th level page table of the first page table on the third page table; obtaining a page table entry of the m + t + 1-level page table according to the first virtual address range and the third page table; modifying the page table entry of the (m + t + 1) th level page table, and writing the modified page table entry of the (m + t + 1) th level page table into the corresponding position of the (m + t + 1) th level page table.
According to a specific implementation manner of the embodiment of the present application, the determining the first virtual address range includes: determining a target bit corresponding to the m + t + 1-level page table in a base address of the second virtual address space; determining a first value on a bit equal to the target bit in a base address of the first virtual address space; determining a base address of the first virtual address range according to the first value and a base address of the second virtual address space; determining a size of the first virtual address range; and determining the first virtual address range according to the base address of the first virtual address range and the size of the first virtual address range.
According to a specific implementation manner of the embodiment of the present application, the determining a size of the first virtual address range includes: and determining the size of the first virtual address range according to the number of entries of page table entries of the (m + t + 1) -th level page table and the size of each page table entry.
According to a specific implementation manner of the embodiment of the present application, before writing the base address of the mth level page table into the page table entry of the nth level page table of the second page table, the method further includes: judging whether the number of entries of the page table entry of the nth-level page table is 1; if 1, the step of writing the base address of the m-th level page table into the page table entry of the n-th level page table of the second page table is performed.
According to a specific implementation manner of the embodiment of the present application, before obtaining the base address of the mth level page table in the first page table, the method further includes: and traversing the first page table and the second page table, and determining that the first page table and the second page table have no missing pages.
According to a specific implementation manner of the embodiment of the present application, after determining that the first page table and the second page table are free of missing pages, the method further includes: saving a page table entry of an nth level page table of the second page table; and/or saving a page table entry in the m + t +1 level page table of the first page table.
According to a specific implementation manner of the embodiment of the application, a page table entry of an nth level page table of the second page table is saved; and/or after saving a page table entry in the m + t +1 th level page table of the first page table, the method further comprises: restoring a page table entry of an nth level page table of the second page table by using a saved page table entry of an nth level page table of the second page table; and/or restoring the page table entry in the m + t + 1-level page table of the first page table by using the page table entry in the m + t + 1-level page table of the first page table.
In a second aspect, an authentication method in an embodiment of the present application includes: the test code obtains target data through a page table; wherein the test code is to verify a characteristic of a processor and/or an attribute of the page table; the page table is created according to the modification method of the page table described in any of the above embodiments; the test code running on the processor; verifying a characteristic of the processor and/or an attribute of the page table based on the target data.
In a third aspect, an embodiment of the present application provides a modifying apparatus for a page table, including: the application module is used for applying for the first virtual address space and the second virtual address space; wherein the first virtual address space is mapped to a first physical address space by a first page table, and the second virtual address space is mapped to a second physical address space by a second page table; a writing module, configured to write a base address of an m-th level page table in the first page table into a page table entry of an n-th level page table in the second page table to form a third page table; wherein m is an integer greater than or equal to 1 and less than or equal to the number of stages of the first page table; n is an integer greater than or equal to m and less than or equal to the number of stages of the second page table; and the modifying module is used for modifying the first page table according to the third page table.
According to a specific implementation manner of the embodiment of the present application, the application module is specifically configured to: and applying for the first virtual address space and the second virtual address space through a dynamic memory allocation function.
According to a specific implementation manner of the embodiment of the present application, the write module includes: the obtaining submodule is used for obtaining a base address of an mth level page table in the first page table; a write submodule, configured to write a base address of the m-th level page table into a page table entry of an n-th level page table of the second page table to form the third page table; the third page table sequentially comprises a first page table to an nth page table of the second page table, an mth page table of the first page table, and a t-level page table after the mth page table in the first page table; t is a difference value obtained by subtracting n from the number of levels of the second page table and then subtracting 1 from the number of levels of the second page table, wherein t is greater than or equal to 0 and less than or equal to; the modification module includes: and the modification submodule is used for writing data into page table entries in the (m + t + 1) th level page table of the first page table according to the third page table so as to modify the first page table.
According to a specific implementation manner of the embodiment of the present application, the obtaining sub-module is specifically configured to: acquiring a base address of the first page table through a kernel driving module; acquiring a base address of an m-level page table in the first page table according to the base address of the first page table; the modification submodule is specifically configured to: acquiring a base address of the second page table through the kernel driving module; acquiring the address of a page table entry of an nth level page table in the second page table according to the base address of the second page table; and writing the base address of the m-level page table into a page table entry of an n-level page table of the second page table according to the address of the page table entry of the n-level page table.
According to a specific implementation manner of the embodiment of the present application, the number of stages of the first page table is 4, and the number of stages of the second page table is four; m and n are equal to three; the write submodule is specifically configured to: writing a base address of a third stage page table of the first page table into a page table entry of a third stage page table of the second page table.
According to a specific implementation manner of the embodiment of the present application, the modification sub-module is specifically configured to: determining a first virtual address range; wherein the first virtual address range corresponds to an m + t +1 th level page table of the first page table on the third page table; obtaining a page table entry of the m + t + 1-level page table according to the first virtual address range and the third page table; modifying the page table entry of the (m + t + 1) th level page table, and writing the modified page table entry of the (m + t + 1) th level page table into the corresponding position of the (m + t + 1) th level page table.
According to a specific implementation manner of the embodiment of the present application, the modification sub-module is specifically configured to: determining a target bit corresponding to the m + t +1 th level page table in a base address of the second virtual address space; determining a first value on a bit equal to the target bit in a base address of the first virtual address space; determining a base address of the first virtual address range according to the first value and a base address of the second virtual address space; determining a size of the first virtual address range; and determining the first virtual address range according to the base address of the first virtual address range and the size of the first virtual address range.
According to a specific implementation manner of the embodiment of the present application, the modification sub-module is specifically configured to: and determining the size of the first virtual address range according to the number of entries of page table entries of the (m + t + 1) -th level page table and the size of each page table entry.
According to a specific implementation manner of the embodiment of the present application, the apparatus further includes: a determining module, configured to determine whether the number of entries of the page table entry of the nth-level page table is 1 before the writing module writes the base address of the mth-level page table into the page table entry of the nth-level page table of the second page table; and if the address is 1, the execution module is used for writing the base address of the m-level page table into a page table entry of an n-level page table of the second page table.
According to a specific implementation manner of the embodiment of the present application, the apparatus further includes: and the traversing module is used for traversing the first page table and the second page table before the obtaining submodule obtains the base address of the mth page table in the first page table, and determining that the first page table and the second page table have no missing page.
According to a specific implementation manner of the embodiment of the present application, the apparatus further includes: a saving module, configured to save a page table entry of an nth level page table of the second page table after the traversal module determines that the first page table and the second page table are missing; and/or saving page table entries in the (m + t + 1) th level page table of the first page table.
According to a specific implementation manner of the embodiment of the present application, the apparatus further includes: a restoring module, configured to save a page table entry of an nth level page table of the second page table by the saving module; and/or after saving the page table entry in the (m + t + 1) th level page table of the first page table, restoring the page table entry of the nth level page table of the second page table by using the saved page table entry of the nth level page table of the second page table; and/or restoring the page table entry in the m + t +1 level page table of the first page table by using the page table entry in the m + t +1 level page table of the first page table.
In a fourth aspect, an embodiment of the present application provides an authentication apparatus, including: the acquisition module is used for acquiring target data by the test code through the page table; wherein the test code is to verify a characteristic of a processor and/or an attribute of the page table; the page table is created according to the modification method of the page table described in any of the previous embodiments; the test code running on the processor; a verification module to verify a characteristic of the processor and/or an attribute of the page table according to the target data.
In a fifth aspect, an embodiment of the present application provides an electronic device, where the electronic device includes: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor executes a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used for executing the page table modifying method and/or the verifying method in any one of the foregoing implementations.
In a sixth aspect, embodiments of the present application provide a computer-readable storage medium storing one or more programs, where the one or more programs are executable by one or more processors to implement the method for modifying a page table and/or the method for verifying in any of the foregoing implementations.
The method for modifying a page table, the method for verifying a processor, the device for verifying a processor, the electronic device and the readable storage medium of the embodiment apply for a first virtual address space and a second virtual address space; the first virtual address space is mapped to the first physical address space through the first page table, the second virtual address space is mapped to the second physical address space through the second page table, the base address of the mth level page table in the first page table is written into the page table entry of the nth level page table in the second page table to form a third page table, and then the first page table is modified according to the third page table, so that the efficiency of verifying the characteristics of the processor and/or the attributes of the page tables is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic flowchart of a page table modification method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a third page table according to an embodiment of the present application;
FIG. 3 is a flowchart illustrating a method for modifying a page table according to an embodiment of the present application;
fig. 4 is a schematic flowchart of a verification method according to an embodiment of the present application;
fig. 5 is a schematic flowchart of a verification method according to an embodiment of the present application;
FIG. 6 is a schematic structural diagram of an apparatus for modifying a page table according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of an authentication apparatus according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the application.
Detailed Description
The embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
In order to make those skilled in the art better understand the technical concepts, embodiments and advantages of the examples of the present application, the following detailed description is given by way of specific examples.
An embodiment of the present application provides a method for modifying a page table, which facilitates improving efficiency of verifying characteristics of a processor and/or attributes of the page table.
Fig. 1 is a schematic flow diagram of a method for modifying a page table according to an embodiment of the present application, and as shown in fig. 1, the method for modifying a page table according to the embodiment may include:
s101, applying for a first virtual address space and a second virtual address space.
And applying for a virtual address space from an operating system, and allocating a page table for the virtual address space to complete the mapping of the virtual address to the physical address.
In this embodiment, the first virtual address space is mapped to the first physical address space through the first page table, and the second virtual address space is mapped to the second physical address space through the second page table.
The first virtual address space and the second virtual address space of this embodiment may be the same in size or different in size.
The number of stages of the first page table may be equal to the number of stages of the second page table.
In some examples, the first virtual address space and the second virtual address space are applied for by a dynamic memory allocation function.
In this embodiment, the dynamic memory allocation function may be a malloc function.
S102, writing a base address of an m-level page table in the first page table into a page table entry of an n-level page table in the second page table to form a third page table.
In this embodiment, m is an integer greater than or equal to 1 and less than or equal to the number of stages of the first page table; n is an integer of m or more and the number of stages of the second page table or less.
If the first page table and the second page table are four-level page tables, and the mth-level page table in the first page table is a second-level page table, the nth-level page table of the second page table may be a second-level, a third-level, or a fourth-level.
The number of stages of the third page table may be equal to the number of stages of the first page table and the second page table.
In the page table, the page table entry in the previous page table points or indexes to the next page table, so that the base address of the mth page table in the first page table is written into the page table entry of the nth page table in the second page table, and the mth page table in the first page table can be indexed by the page table entry of the nth page table in the second page table.
S103, modifying the first page table according to the third page table.
In this embodiment, the first page table may be modified according to the formed third page table, and the modified first page table may be used for processor verification.
In this embodiment, a first virtual address space and a second virtual address space are applied for; the method comprises the steps of mapping a first virtual address space to a first physical address space through a first page table, mapping a second virtual address space to a second physical address space through a second page table, writing a base address of an m-level page table in the first page table into a page table entry of an n-level page table of the second page table to form a third page table, and modifying the first page table according to the third page table, so that the efficiency of verifying the characteristics of a processor and/or the attributes of the page tables is improved, and the problem of low verification efficiency caused by the fact that an operating system manages the page tables in the prior art is solved.
It will be appreciated that the above process may be performed by a user mode process, i.e. the first page table may be modified in the user mode.
Another embodiment of the present application is substantially the same as the above embodiments, except that the writing the base address of the mth level page table in the first page table into the page table entry of the nth level page table in the second page table to form a third page table (S102), may include:
s102a, obtaining a base address of an m-level page table in a first page table.
In some examples, obtaining the base address of the mth stage page table in the first page table (S102 a) may include:
a1, a kernel driving module acquires a base address of a first page table.
The kernel driver module may interact with the kernel mode or the operating system, so that the base address of the first page table stored in the kernel mode may be obtained by the kernel driver module, and in some examples, the base address of the first page table is stored in the CR3 register, that is, the value in the CR3 register is obtained by the kernel driver module.
The base address of the first page table may be a base address of a first stage page table in the first page table.
And A2, acquiring the base address of the mth level page table in the first page table according to the base address of the first page table.
By obtaining the base address of the first page table, that is, the value of the CR3 register, the page table translation process of each page in the first virtual address space can be obtained, that is, the base address of the mth page table in the first page table can be obtained.
S102b, writing the base address of the m-level page table into a page table entry of an n-level page table of the second page table to form a third page table.
The third page table in this embodiment includes, in sequence, a first page table to an nth page table of the second page table, an mth page table of the first page table, and a t-level page table following the mth page table in the first page table; wherein, t is a difference value obtained by subtracting n from the number of levels of the second page table and subtracting 1 from the number of levels of the second page table, i.e. the total number of page table levels from the first page table to the nth page table of the second page table, from the mth page table of the first page table to the t-level page table after the mth page table in the first page table is equal to the number of levels of the first page table or the second page table.
The base address of the mth stage page table is written into the page table entry of the nth stage page table of the second page table, so that the mth stage page table of the first page table can be indexed by the page table entry of the nth stage page table of the second page table in the third page table formed.
Referring to fig. 2, taking a four-level page table as an example, a base address of a first-level page table of a first page table may be written into a page table entry of a first-level page table, a second-level page table, a third-level page table, or a fourth-level page table of a second page table; the base address of the second stage page table of the first page table can be written into a page table entry of the second stage page table, the third stage page table or the fourth stage page table of the second page table; the base address of the third-level page table of the first page table can be written into a page table entry of the third-level page table or the fourth-level page table of the second page table; the base address of the fourth stage page table of the first page table may be written into a page table entry of the fourth stage page table of the second page table.
Referring to fig. 2, a base address of a third-level page table of the first page table is written into a page table entry of a third-level page table of the second page table, the third page table sequentially includes a first-level page table to the third-level page table of the second page table and the third-level page table of the second page table, and the fourth-level page table of the first page table is a physical address corresponding to the third page table.
It is to be understood that, in some examples, writing the base address of the mth stage page table into the page table entry of the nth stage page table of the second page table (S102 b) may include:
and B1, acquiring the base address of the second page table through a kernel driving module.
The kernel driver may interact with the kernel mode or the operating system, so that the base address of the second page table stored in the kernel mode may be obtained by the kernel driver, and in some examples, the base address of the second page table is stored in the CR3 register, that is, the value in the CR3 register is obtained by the kernel driver. In this embodiment, the base addresses of the first page table corresponding to the first virtual address space and the second page table corresponding to the second virtual address space are the same.
The base address of the second page table may be the base address of the first stage page table in the second page table.
B2, acquiring the address of the page table entry of the nth level page table in the second page table according to the base address of the second page table.
By obtaining the base address of the second page table, i.e. the value of the CR3 register, the page table translation process of each page in the second virtual address space can be obtained, i.e. the address of the page table entry of the nth level page table in the second page table can be obtained.
And B3, writing the base address of the m-level page table into the page table entry of the n-level page table of the second page table according to the address of the page table entry of the n-level page table.
And writing the base address of the mth stage page table into the page table entry of the nth stage page table of the second page table, so that the address in the page table entry of the nth stage page table of the second page table entry can be indexed to the mth stage page table of the first page table.
Modifying the first page table according to the third page table (S103) may include:
s103a, writing data into page table entries in the (m + t + 1) th level page table of the first page table according to the third page table to modify the first page table.
Writing a base address of an m-level page table into a page table entry of an n-level page table of a second page table to form a third page table, wherein a last level of the third page table is an m + t-level page table of a first page table, so that a page table entry in an m + t + 1-level page table of the first page table can be used as a physical address corresponding to the third page table, and thus, data can be written into the page table entry in the m + t + 1-level page table of the first page table through the third page table, so that the page table entry in the m + t + 1-level page table of the first page table is changed, and correspondingly, the first page table includes the m + t + 1-level page table entry of the changed page table, namely, the first page table is modified.
In this embodiment, the difference is that, according to the third page table, writing data to a page table entry in the n + t +1 th page table of the first page table (S103 a), which may include:
and C1, determining a first virtual address range.
In this embodiment, the first virtual address range corresponds to the m + t +1 th page table of the first page table on the third page table, and a page table entry in the m + t +1 th page table of the first page table may be a physical address corresponding to the third page table, so that the first virtual address range may be mapped to the m + t +1 th page table of the first page table through the third page table.
The first virtual address range may be determined by the base address and the size of the virtual address range, and in some examples, determining the first virtual address range may include:
and C11, determining a target bit corresponding to the m + t +1 th level page table in the base address of the second virtual address space.
The base address of the second virtual address space includes a plurality of bits including a target bit corresponding to the m + t +1 th level page table.
And C12, determining a first value on a bit equal to the target bit in the base address of the first virtual address space.
In the base address of the first virtual address space, a first value, which is a value on a bit equal to the target bit, is found.
And C13, determining the base address of the first virtual address range according to the first value and the base address of the second virtual address space.
The base address of the first virtual address range needs to be equal to the base address of the m + t +1 th level page table. If the value of the target bit corresponding to the (m + t + 1) th level page table in the base address of the second virtual address space is determined to be a, and the first value of the bit equal to the target bit in the base address of the first virtual address space is determined to be b, then the base address of the first virtual address range is the difference between b and a, 8 byte.
And C14, determining the size of the first virtual address range.
In some examples, the size of the first virtual address range is determined based on the number of entries of page table entries of the m + t +1 th level page table and the size of each page table entry.
The size of the first virtual address range may be the product of the number of entries of the page table entry of the m + t +1 th level page table and the size of each page table entry, e.g., the size of each page table entry is 8 bytes, then the size of the first virtual address range is the product of the number of entries of the page table entry of the m + t +1 th level page table and 8 bytes.
And C15, determining the first virtual address range according to the base address of the first virtual address range and the size of the first virtual address range.
And C2, acquiring a page table entry of the m + t + 1-level page table according to the first virtual address range and the third page table.
The first virtual address range can be mapped to the m + t +1 th page table of the first page table through the third page table, so that the page table entry of the m + t +1 th page table is obtained according to the first virtual address range and the third page table.
And C3, modifying the page table entry of the m + t + 1-level page table, and writing the modified page table entry of the m + t + 1-level page table into the corresponding position of the m + t + 1-level page table.
Modifying the obtained page table entry of the (m + t + 1) th level page table, and writing the modified page table entry of the (m + t + 1) th level page table into the corresponding position of the (m + t + 1) th level page table, namely, modifying the page table entry of the (m + t + 1) th level page table, so that the first page table comprises the (m + t + 1) th level page table of the changed page table entry, namely, the first page table is modified.
In yet another embodiment of the present application, basically the same as the above embodiment, except that before writing the base address of the mth level page table into the page table entry of the nth level page table of the second page table, the method of this embodiment may further include:
s104, judging whether the number of the entries of the page table entry of the nth-level page table is 1.
Since the base address of the m-th stage page table of the first page table is one address and the page table entry of the n-th stage page table of the second page table is a storage address, the page table entry of the n-th stage page table of the second page table is required to be one entry in order to correspond to the one address.
S105, if the address is 1, writing the base address of the m-level page table into the page table entry of the n-level page table of the second page table.
And writing the base address of the mth stage page table into the page table entry of the nth stage page table of the second page table when the number of entries of the page table entry of the nth stage page table is 1.
In another embodiment of the present application, which is basically the same as the foregoing embodiment, the difference is that before the base address of the mth page table in the first page table is obtained, the method of this embodiment may further include:
s106, traversing the first page table and the second page table, and determining that the first page table and the second page table have no missing pages.
The first page table and the second page table may be traversed according to the obtained value of the CR3 register, that is, the base addresses of the first page table and the second page table, and it may be determined that the first page table and the second page table are free of missing pages.
In some examples, after determining that the first page table and the second page table are free of missing pages, the method may further include:
and S107, saving a page table entry of the nth level page table of the second page table.
Before writing the base address of the mth stage page table of the first page table into the page table entry of the nth stage page table of the second page table, the page table entry of the nth stage page table of the second page table may be saved for subsequent recovery of the page table entry of the nth stage page table of the second page table.
In order not to affect the system operation and the system security, after the verifying, the original page table needs to be restored, and in some examples, after the page table entry of the nth level page table of the second page table is saved, the method may further include:
and S108, restoring the page table entry of the nth level page table of the second page table by using the saved page table entry of the nth level page table of the second page table.
In some examples, after determining that the first page table and the second page table are free of missing pages, the method may further include:
s109, saving page table entries in the (m + t + 1) th level page table of the first page table.
In some examples, the page table entry in the m + t +1 th level page table of the first page table may also be saved before the page table entry in the m + t +1 th level page table of the first page table is modified, so as to subsequently recover the page table entry in the m + t +1 th level page table of the first page table.
In order not to affect the system operation and the system security, after the verifying, the original page table needs to be restored, and in some examples, after saving the page table entry in the m + t +1 th page table of the first page table, the method may further include:
s110, restoring the page table entry in the m + t + 1-level page table of the first page table by using the page table entry in the m + t + 1-level page table of the first page table.
Referring to FIG. 3, a detailed description of the scheme of the present application is provided below using a four-level page table in an embodiment.
In a user mode program of an operating system, two sections of virtual address spaces V1_ space and V2_ space are applied, addresses of the two sections of virtual spaces are mapped to different physical address spaces through respective corresponding page tables, and the whole process of page table conversion of the two sections of virtual space addresses can be traversed by obtaining page table base addresses.
Because each Level of Page Table Entry has the same Bit meaning, the third Level Page Table Entry in the virtual address V2_ space can be written into the third Level Page Table Entry in the virtual address V1_ space, so as to form a new Page Table translation process, and accordingly, the physical space address to which the virtual address in V2_ space is mapped is the fourth Level Page Table Entry in V1_ space, and the fourth Level Page Table corresponding to the virtual address in V1_ space can be modified by the value of the virtual address in the user state V2_ space, and further the Page Table mapping relationship corresponding to the virtual address in V1_ space can be changed, wherein the fourth Level Page Table includes a first Level Page Table, a second Level Page Table, and a third Level Page Table, wherein the first Level Page Table is also called a 4-Level mapping Table, (PML 4E: page-Map Level-4 Entry), the second Level Table is also called a Pointer Directory Table (PDPE, page-Directory Table), and the third Level Page Table is also called a PDE-Directory Table (Page Table).
The specific steps of this example are as follows:
1. and applying for a virtual address space V1_ space and a virtual address space V2_ space in the user-level program.
In an operating system user level program, two sections of virtual address spaces V1_ space and V2_ space are applied, the page table of the V1_ space needs to be changed, and the address of the V2_ space is used for changing the page table of the V1_ space;
2. and traversing the page surfaces of the virtual address spaces V1_ space and V2_ space, and ensuring that page table translation at each level does not generate page change exception.
And the page table conversion at each level is ensured not to generate page conversion exception, namely all pages can be normally converted, and no missing page exception is generated.
Here the value of the page table base register CR3 needs to be obtained, which needs to be written by the kernel driver.
3. And filling the base address of the third-level page table of the corresponding virtual address in the V1_ space virtual space into the third-level page table entry of the corresponding virtual address in the V2_ space virtual space.
And filling the base address of the third-level page table of the corresponding virtual address in the V1_ space virtual space into the third-level page table entry of the corresponding virtual address in the V2_ space virtual space, so that the physical space address corresponding to the virtual address of the V2_ space is the fourth-level page table entry of the corresponding virtual address in the V1_ space.
4. And saving the original fourth-level page table entries in the V1_ space virtual space and the original third-level page table entries in the V2_ space virtual space.
5. The page table for the corresponding virtual address in the V1_ space is modified.
And modifying the page table mapping relation of the corresponding virtual address in the V1_ space by using the instruction according to the value of the corresponding virtual address in the V2_ space virtual space at the user level.
6. Before the user mode program exits, the original fourth level page table entry of the V1_ space virtual space and the original third level page table entry of the V2_ space virtual space are restored.
In this embodiment, the change of the page table mapping relationship of the specific virtual address space is realized in the user mode of the operating system, the last-stage page table is modified in all pages of the specific virtual address space in the user mode process, and the page table mapping relationship of the original virtual address space needs to be restored before the process exits, so that no influence is caused on the system operation, and no influence is caused on the system security.
In this embodiment, depending on a processor paging mechanism and an operating system page table management system, a page table mapping relationship of a virtual address space in a user mode program can be changed quickly through an instruction in the user mode, and hardware resources such as CR3 and TLB are not affected.
According to the verification method provided by the embodiment of the application, the efficiency of verifying the characteristics of the processor and/or the attributes of the page table can be improved.
Fig. 4 is a schematic flowchart of a verification method according to an embodiment of the present application, and as shown in fig. 4, the method for modifying a page table according to the embodiment may include:
s201, the test code obtains target data through the page table.
The test code in this embodiment runs on the processor.
The test code is used to verify a characteristic of the processor, where the target data is a physical address obtained through the page table, and/or an attribute of the page table, where the target data may be the attribute of the page table.
The page table in this embodiment is created according to the modification method of the page table in any of the above embodiments.
S202, according to the target data, the characteristics of the processor and/or the attributes of the page table are verified.
Based on the retrieved target data, the characteristics of the processor and/or attributes of the page table are verified.
In this embodiment, the test code obtains the target data through the page table, and verifies the characteristics of the processor and/or the attributes of the page table according to the target data, since in the verification process, the page table used is determined according to the modification method of the page table in any of the above embodiments, and the modification of the page table in any of the above embodiments is modified in the user mode, it is able to improve the efficiency of verifying the characteristics of the processor and/or the attributes of the page table.
Referring to fig. 5, an embodiment of modifying a page table mapping relationship through an instruction in a user mode of a Linux operating system is described below, where the embodiment is used to verify a page attribute of a processor, a page table of the embodiment is a four-level page table, and a specific execution flow is as follows:
1. and obtaining the base address of the page table of the current process through a kernel driver.
In the Linux operating system, a kernel driver needs to be written, and the base address of the current process page table, that is, the value of the CR3 register, can be obtained.
2. And applying for 4M virtual address space V1_ space and 16K virtual address space V2_ space through malloc function application.
The Linux operating system generally uses 4K pages, so a segment of virtual address space with the size of 1024 × 4K and a segment of virtual address space V2_ space with the size of 4 × 4K are applied through the malloc function.
3. 1024 pages in the V1_ space are traversed.
Through the obtained value of the CR3 register, the page table translation process of 1024 pages in the virtual address space V1_ space can be obtained, all page tables are traversed, and no missing page is ensured.
4. The third level page table of the V2_ space is saved and mapped to the third level page table of the corresponding address in the V1_ space.
And filling the base address of the third-level page table of the corresponding page table in the V1_ space into the third-level page table of the corresponding page table in the V2_ space, namely mapping the virtual address of the V2_ space onto the fourth-level page table of the corresponding page table in the V1_ space.
5. And determining that the four-level page tables of all the pages in the V1_ space correspond to the virtual address range of the V2_ space, and storing the four-level page table entries of all the pages in the V1_ space.
The base virtual address Vaddr of the V2_ space corresponding to the four-level page tables of 1024 pages in the V1_ space is obtained, and the virtual address range of the V2_ space corresponding to the four-level page tables of all the pages in the V1_ space is [ Vaddr-Vaddr +8K ]. And saving a fourth level page table entry of all the pages in the V1_ space. Wherein, 8K is obtained according to the product of the number 1024 of the fourth level page table entries of the page table corresponding to the V1_ space and the size of each entry 8 bytes.
6. The page table for the virtual address in V1_ space is modified.
A value is selected from a virtual address [ Vaddr-Vaddr +8K ] in the V2_ space, so that the corresponding physical address can be read, that is, the fourth-level page table entry of the page corresponding to the V1_ space can be obtained, the fourth-level page table entry is modified, and the modified page table entry is written into the corresponding position, so that the page table of the virtual address in the V1_ space is modified.
7. The test code is verified.
8. Before exiting the user mode program, the third level page table of the V2_ space and the fourth level page table of the V1_ space are restored.
In this embodiment, the page table conversion is changed by modifying the third-level page table entry in the virtual address space by using the consistency of the page table entries in the 4K paging mechanism of the processor, so as to affect the page table mapping in another virtual address space, and in addition, the page table is rapidly changed by the instruction in the user mode program without changing pages and affecting the TLB.
The page table modifying device provided by the embodiment of the application is convenient for improving the efficiency of verifying the characteristics of the processor and/or the attributes of the page table.
Fig. 6 is a schematic structural diagram of a modifying device of a page table according to an embodiment of the present application, and as shown in fig. 6, the modifying device of the page table according to the embodiment includes: an application module 11, configured to apply for a first virtual address space and a second virtual address space; the first virtual address space is mapped to a first physical address space through a first page table, and the second virtual address space is mapped to a second physical address space through a second page table; a writing module 12, configured to write a base address of an m-th level page table in the first page table into a page table entry of an n-th level page table of the second page table to form a third page table; wherein m is an integer greater than or equal to 1 and less than or equal to the number of stages of the first page table; n is an integer greater than or equal to m and less than or equal to the number of stages of the second page table; and a modifying module 13, configured to modify the first page table according to the third page table.
The apparatus of this embodiment may be used to implement the technical solution of the method embodiment shown in fig. 1, and the implementation principle and the technical effect are similar, which are not described herein again.
The device of the embodiment applies for a first virtual address space and a second virtual address space; the method comprises the steps of mapping a first virtual address space to a first physical address space through a first page table, mapping a second virtual address space to a second physical address space through a second page table, writing a base address of an m-level page table in the first page table into a page table entry of an n-level page table of the second page table to form a third page table, and modifying the first page table according to the third page table, so that the efficiency of verifying the characteristics of a processor and/or the attributes of the page tables is improved, and the problem of low verification efficiency caused by the fact that an operating system manages the page tables in the prior art is solved.
As an optional implementation manner, the application module is specifically configured to: and applying for a first virtual address space and a second virtual address space through a dynamic memory allocation function.
As an optional implementation, the writing module includes: the obtaining submodule is used for obtaining a base address of an mth level page table in the first page table; a writing submodule, configured to write a base address of the mth-level page table into a page table entry of an nth-level page table of a second page table to form a third page table; the third page table sequentially includes a first page table to an nth page table of the second page table, an mth page table of the first page table, and a t-level page table following the mth page table in the first page table; wherein t is a difference value obtained by subtracting n from the number of the second page table and subtracting 1 from the number of the second page table, wherein t is greater than or equal to 0; the modification module includes: and the modification submodule is used for writing data into page table entries in the m + t + 1-level page table of the first page table according to the third page table so as to modify the first page table.
As an optional implementation manner, the obtaining sub-module is specifically configured to: acquiring a base address of the first page table through a kernel driving module; acquiring a base address of an m-level page table in the first page table according to the base address of the first page table; the modification submodule is specifically configured to: acquiring a base address of the second page table through the kernel driving module; acquiring the address of a page table entry of an nth level page table in the second page table according to the base address of the second page table; and writing the base address of the m-level page table into a page table entry of an n-level page table of a second page table according to the address of the page table entry of the n-level page table.
As an optional implementation, the number of stages of the first page table is 4, and the number of stages of the second page table is four; m and n are equal to three; the write submodule is specifically configured to: and writing the base address of the third-stage page table of the first page table into a page table entry of the third-stage page table of the second page table.
As an optional implementation, the modification submodule is specifically configured to: determining a first virtual address range; wherein the first virtual address range corresponds to an m + t +1 th level page table of the first page table on the third page table; acquiring a page table entry of the m + t + 1-level page table according to the first virtual address range and the third page table; and modifying the page table entry of the (m + t + 1) th level page table, and writing the modified page table entry of the (m + t + 1) th level page table into the corresponding position of the (m + t + 1) th level page table.
As an optional implementation, the modification submodule is specifically configured to: determining a target bit corresponding to the m + t +1 th level page table in a base address of the second virtual address space; determining a first value on a bit equal to the target bit in a base address of the first virtual address space; determining a base address of the first virtual address range according to the first value and a base address of the second virtual address space; determining a size of the first virtual address range; and determining the first virtual address range according to the base address of the first virtual address range and the size of the first virtual address range.
As an optional implementation, the modification submodule is specifically configured to: and determining the size of the first virtual address range according to the number of the page table entries of the (m + t + 1) th level page table and the size of each page table entry.
As an optional embodiment, the apparatus further comprises: a determining module, configured to determine whether the number of entries of the page table entry of the nth-level page table is 1 before the writing module writes the base address of the mth-level page table into the page table entry of the nth-level page table of the second page table; and if the address is 1, the execution module is used for writing the base address of the m-level page table into a page table entry of an n-level page table of the second page table.
As an optional embodiment, the apparatus further comprises: and the traversing module is used for traversing the first page table and the second page table before the obtaining submodule obtains the base address of the mth page table in the first page table, and determining that the first page table and the second page table have no missing page.
As an optional embodiment, the apparatus further comprises: a saving module, configured to save a page table entry of an nth level page table of the second page table after the traversal module determines that the first page table and the second page table are missing; and/or saving page table entries in the (m + t + 1) th level page table of the first page table.
As an optional embodiment, the apparatus further comprises: a restoring module, configured to save, by the saving module, a page table entry of an nth-level page table of the second page table; and/or after saving the page table entry in the (m + t + 1) th level page table of the first page table, restoring the page table entry of the nth level page table of the second page table by using the saved page table entry of the nth level page table of the second page table; and/or restoring the page table entry in the m + t + 1-level page table of the first page table by using the page table entry in the m + t + 1-level page table of the first page table.
The apparatus in the foregoing embodiment may be configured to implement the technical solutions in the foregoing method embodiments, and the implementation principles and technical effects are similar, which are not described herein again.
The processor verification device provided by the embodiment of the application can improve the efficiency of verifying the characteristics of the processor and/or the attributes of the page table.
Fig. 7 is a schematic structural diagram of an authentication device according to an embodiment of the present application, and as shown in fig. 7, the authentication device according to the embodiment includes: an obtaining module 21, configured to obtain target data through a page table by a test code; wherein the test code is to verify a characteristic of the processor and/or an attribute of the page table; the page table is created according to the modification method of the page table of any one of the above embodiments; test code is run on the processor; a verification module 22 for verifying the characteristics of the processor and/or attributes of the page table based on the target data.
The apparatus of this embodiment may be used to implement the technical solution of the method embodiment shown in fig. 4, and the implementation principle and the technical effect are similar, which are not described herein again.
In the apparatus of this embodiment, the test code obtains the target data through the page table, and verifies the characteristics of the processor and/or the attributes of the page table according to the target data, since in the verification process, the page table used is determined according to the modification method of the page table in any of the above embodiments, and the modification of the page table in any of the above embodiments is modified in the user mode, it is able to improve the efficiency of verifying the characteristics of the processor and/or the attributes of the page table.
The apparatus of the foregoing embodiment may be configured to implement the technical solution of the foregoing method embodiment, and the implementation principle and the technical effect are similar, which are not described herein again.
Fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application, as shown in fig. 8, the electronic device may include: a housing 61, a processor 62, a memory 63, a circuit board 64, and a power circuit 65, wherein the circuit board 64 is disposed inside a space enclosed by the housing 61, and the processor 62 and the memory 63 are disposed on the circuit board 64; a power supply circuit 65 for supplying power to each circuit or device of the electronic apparatus; the memory 63 is used to store executable program code; the processor 62 reads the executable program code stored in the memory 63 to run a program corresponding to the executable program code, so as to execute any page table modifying method or verifying method provided in the foregoing embodiments, and thus corresponding advantageous technical effects can also be achieved.
The electronic devices described above exist in a variety of forms, including but not limited to:
(1) A mobile communication device: such devices are characterized by mobile communications capabilities and are primarily targeted at providing voice, data communications. Such terminals include: smart phones (e.g., iphones), multimedia phones, functional phones, and low-end phones, among others.
(2) Ultra mobile personal computer device: the equipment belongs to the category of personal computers, has calculation and processing functions and generally has the characteristic of mobile internet access. Such terminals include: PDA, MID, and UMPC devices, etc., such as ipads.
(3) A portable entertainment device: such devices may display and play multimedia content. This type of device comprises: audio, video players (e.g., ipods), handheld game consoles, electronic books, and smart toys and portable car navigation devices.
(4) A server: the device for providing the computing service comprises a processor, a hard disk, a memory, a system bus and the like, and the server is similar to a general computer architecture, but has higher requirements on processing capacity, stability, reliability, safety, expandability, manageability and the like because of the need of providing high-reliability service.
(5) And other electronic equipment with data interaction function.
Accordingly, embodiments of the present application further provide a computer-readable storage medium, where one or more programs are stored, and the one or more programs can be executed by one or more processors to implement any one of the page table modifying methods or verifying methods provided in the foregoing embodiments, so that corresponding technical effects can also be achieved, which have been described in detail above and are not described herein again.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.
In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
For convenience of description, the above devices are described as being respectively described in terms of functional division into various units/modules. Of course, the functionality of the units/modules may be implemented in one or more software and/or hardware implementations when the present application is implemented.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above may be implemented by a computer program, which may be stored in a computer readable storage medium and executed by a computer to implement the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (19)

1. A method for modifying a page table, comprising:
applying for a first virtual address space and a second virtual address space; wherein the first virtual address space is mapped to a first physical address space by a first page table, and the second virtual address space is mapped to a second physical address space by a second page table;
writing a base address of an m-th level page table in the first page table into a page table entry of an n-th level page table of the second page table to form a third page table; wherein m is an integer greater than or equal to 1 and less than or equal to the number of stages of the first page table; n is an integer greater than or equal to m and less than or equal to the number of stages of the second page table;
modifying the first page table according to the third page table.
2. The method of claim 1, wherein applying for the first virtual address space and the second virtual address space comprises:
and applying for the first virtual address space and the second virtual address space through a dynamic memory allocation function.
3. The method of claim 1, wherein writing a base address of an m-th stage page table in the first page table into a page table entry of an n-th stage page table in the second page table to form a third page table comprises:
acquiring a base address of an m-level page table in the first page table;
writing a base address of the m-th stage page table into a page table entry of an n-th stage page table of the second page table to form the third page table; the third page table sequentially comprises a first page table to an nth page table of the second page table, an mth page table of the first page table, and a t-level page table after the mth page table in the first page table; t is a difference value obtained by subtracting n from the number of levels of the second page table and then subtracting 1 from the number of levels of the second page table, wherein t is greater than or equal to 0 and less than or equal to;
modifying the first page table according to the third page table, including:
writing data to a page table entry in an m + t +1 level page table of the first page table to modify the first page table, according to the third page table.
4. The method of claim 3, wherein the obtaining a base address of an mth stage page table in the first page table comprises:
acquiring a base address of the first page table through a kernel driving module;
acquiring a base address of an m-level page table in the first page table according to the base address of the first page table;
the writing the base address of the m-th stage page table into a page table entry of an n-th stage page table of the second page table includes:
acquiring a base address of the second page table through the kernel driving module;
acquiring the address of a page table entry of an nth level page table in the second page table according to the base address of the second page table;
and writing the base address of the m-level page table into the page table entry of the n-level page table of the second page table according to the address of the page table entry of the n-level page table.
5. The method of claim 3, wherein said writing data to a page table entry in an m + t +1 th level page table of the first page table according to the third page table comprises:
determining a first virtual address range; wherein the first virtual address range corresponds to an m + t +1 th page table of the first page table on the third page table;
acquiring a page table entry of the m + t + 1-level page table according to the first virtual address range and the third page table;
modifying the page table entry of the (m + t + 1) th level page table, and writing the modified page table entry of the (m + t + 1) th level page table into the corresponding position of the (m + t + 1) th level page table.
6. The method of claim 5, wherein determining the first virtual address range comprises:
determining a target bit corresponding to the m + t +1 th level page table in a base address of the second virtual address space;
determining a first value on a bit equal to the target bit in a base address of the first virtual address space;
determining a base address of the first virtual address range according to the first value and a base address of the second virtual address space;
determining a size of the first virtual address range;
and determining the first virtual address range according to the base address of the first virtual address range and the size of the first virtual address range.
7. The method of claim 6, wherein determining the size of the first virtual address range comprises:
and determining the size of the first virtual address range according to the number of entries of page table entries of the (m + t + 1) -th level page table and the size of each page table entry.
8. The method of claim 3, wherein prior to writing the base address of the m-th stage page table into the page table entry of the n-th stage page table of the second page table, the method further comprises:
judging whether the number of entries of the page table entry of the nth-level page table is 1;
if so, the step of writing the base address of the m-th level page table into the page table entry of the n-th level page table of the second page table is performed.
9. The method of claim 3, wherein prior to obtaining the base address of the mth level page table of the first page tables, the method further comprises:
and traversing the first page table and the second page table, and determining that the first page table and the second page table have no missing pages.
10. The method of claim 9, wherein after determining that the first page table and the second page table are free of missing pages, the method further comprises:
saving a page table entry of an nth level page table of the second page table; and/or saving a page table entry in the m + t +1 level page table of the first page table.
11. The method of claim 10, wherein a page table entry of an nth level page table of the second page table is saved; and/or after saving a page table entry in the m + t +1 th level page table of the first page table, the method further comprises:
restoring a page table entry of an nth level page table of the second page table by using a saved page table entry of an nth level page table of the second page table; and/or restoring the page table entry in the m + t +1 level page table of the first page table by using the page table entry in the m + t +1 level page table of the first page table.
12. A method of authentication, comprising:
the test code obtains target data through a page table; wherein the test code is to verify a characteristic of a processor and/or an attribute of the page table; the page table is created according to the modification method of the page table of any one of claims 1 to 11 above; the test code running on the processor;
verifying a characteristic of the processor and/or an attribute of the page table based on the target data.
13. An apparatus for modifying a page table, comprising:
the application module is used for applying for a first virtual address space and a second virtual address space; the first virtual address space is mapped to a first physical address space through a first page table, and the second virtual address space is mapped to a second physical address space through a second page table;
a writing module, configured to write a base address of an m-th level page table in the first page table into a page table entry of an n-th level page table of the second page table to form a third page table; wherein m is an integer greater than or equal to 1 and less than or equal to the number of stages of the first page table; n is an integer greater than or equal to m and less than or equal to the number of stages of the second page table;
and the modifying module is used for modifying the first page table according to the third page table.
14. The apparatus of claim 13, wherein the write module comprises:
the obtaining submodule is used for obtaining a base address of an mth level page table in the first page table;
a write submodule, configured to write a base address of the m-th level page table into a page table entry of an n-th level page table of the second page table to form the third page table; the third page table sequentially includes a first page table to an nth page table of the second page table, an mth page table of the first page table, and a t-level page table following the mth page table in the first page table; t is a difference value obtained by subtracting n from the number of levels of the second page table and then subtracting 1 from the number of levels of the second page table, wherein t is greater than or equal to 0 and less than or equal to;
the modification module includes:
and the modification submodule is used for writing data into page table entries in the m + t + 1-level page table of the first page table according to the third page table so as to modify the first page table.
15. The apparatus of claim 14, wherein the obtaining submodule is specifically configured to:
acquiring a base address of the first page table through a kernel driving module;
acquiring a base address of an m-level page table in the first page table according to the base address of the first page table;
the modification submodule is specifically configured to:
acquiring a base address of the second page table through the kernel driving module;
acquiring the address of a page table entry of an nth level page table in the second page table according to the base address of the second page table;
and writing the base address of the m-level page table into the page table entry of the n-level page table of the second page table according to the address of the page table entry of the n-level page table.
16. The apparatus of claim 14, wherein the modification submodule is specifically configured to:
determining a first virtual address range; wherein the first virtual address range corresponds to an m + t +1 th level page table of the first page table on the third page table;
obtaining a page table entry of the m + t + 1-level page table according to the first virtual address range and the third page table;
modifying the page table entry of the (m + t + 1) th level page table, and writing the modified page table entry of the (m + t + 1) th level page table into the corresponding position of the (m + t + 1) th level page table.
17. An authentication apparatus, comprising:
the acquisition module is used for acquiring target data by the test code through the page table; wherein the test code is to verify a characteristic of a processor and/or an attribute of the page table; the page table is created according to the modification method of the page table of any one of the preceding claims 1 to 11; the test code running on the processor;
a verification module to verify a characteristic of the processor and/or an attribute of the page table based on the target data.
18. An electronic device, characterized in that the electronic device comprises: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor executes a program corresponding to the executable program code by reading the executable program code stored in the memory for performing the method of modifying the page table of any one of the preceding claims 1 to 11 and/or the method of verifying of the preceding claim 12.
19. A computer readable storage medium storing one or more programs, the one or more programs being executable by one or more processors to implement the method of modifying a page table of any preceding claim 1 to 11 and/or the method of verifying of any preceding claim 12.
CN202211634598.0A 2022-12-19 2022-12-19 Page table modifying method, page table verifying method, page table modifying device, page table verifying device and electronic equipment Pending CN115878510A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211634598.0A CN115878510A (en) 2022-12-19 2022-12-19 Page table modifying method, page table verifying method, page table modifying device, page table verifying device and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211634598.0A CN115878510A (en) 2022-12-19 2022-12-19 Page table modifying method, page table verifying method, page table modifying device, page table verifying device and electronic equipment

Publications (1)

Publication Number Publication Date
CN115878510A true CN115878510A (en) 2023-03-31

Family

ID=85754005

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211634598.0A Pending CN115878510A (en) 2022-12-19 2022-12-19 Page table modifying method, page table verifying method, page table modifying device, page table verifying device and electronic equipment

Country Status (1)

Country Link
CN (1) CN115878510A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116185902A (en) * 2023-04-13 2023-05-30 阿里云计算有限公司 Table segmentation method, system, electronic equipment and readable medium

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116185902A (en) * 2023-04-13 2023-05-30 阿里云计算有限公司 Table segmentation method, system, electronic equipment and readable medium

Similar Documents

Publication Publication Date Title
CN111090628B (en) Data processing method and device, storage medium and electronic equipment
US9977598B2 (en) Electronic device and a method for managing memory space thereof
CN107480074B (en) Caching method and device and electronic equipment
CN104268229A (en) Resource obtaining method and device based on multi-process browser
CN115878510A (en) Page table modifying method, page table verifying method, page table modifying device, page table verifying device and electronic equipment
CN113326094A (en) Host memory mapping method and device, electronic equipment and computer readable medium
CN112199039B (en) Virtual storage management method and processor
CN110652728A (en) Game resource management method and device, electronic equipment and storage medium
US8726101B2 (en) Apparatus and method for tracing memory access information
CN113965402A (en) Configuration method and device of firewall security policy and electronic equipment
CN114064524A (en) Server, method and device for improving performance of server and medium
CN111901453B (en) Identification generation method, device, computer equipment and storage medium
CN115878502A (en) Page table creating method, processor verification device and electronic equipment
CN113656330B (en) Method and device for determining access address
CN114721891A (en) Method and device for writing data in buffer area in memory management unit
TWI777268B (en) Virtual memory management method and processor
CN112269665B (en) Memory processing method and device, electronic equipment and storage medium
CN111228815B (en) Method, apparatus, storage medium and system for processing configuration table of game
CN113656331A (en) Method and device for determining access address based on high and low bits
CN113238821A (en) Data processing acceleration method and device, electronic equipment and storage medium
CN115982065A (en) Page table generation method and device for processor paging verification and electronic equipment
CN113111013A (en) Flash memory data block binding method, device and medium
CN112036133A (en) File saving method and device, electronic equipment and storage medium
CN114676071B (en) Data processing method and device, electronic equipment and storage medium
CN110659489B (en) Threat detection method, device and storage medium for character string splicing behavior

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination