CN115878502A - Page table creating method, processor verification device and electronic equipment - Google Patents
Page table creating method, processor verification device and electronic equipment Download PDFInfo
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Abstract
The embodiment of the application discloses a page table creating method, a processor verification method, a page table creating device, a processor verification device and electronic equipment, relates to the technical field of processor verification, and aims to improve the processor verification efficiency. The method comprises the following steps: determining a virtual address range to be converted according to a maximum access memory address required by a preset test code; applying for required address space for each level of page table according to the virtual address range; initializing each level of page tables to fill a base address of a next level of page tables into a page table entry of an upper level of page tables and fill a high order of a virtual address into a page table entry of a last level of page tables; wherein, the high order bits of the virtual address are the bits of the virtual address except the offset bit in the page. The application is applicable to verifying the processor.
Description
Technical Field
The present application relates to the field of processor verification technologies, and in particular, to a page table creation method, a processor verification method, an apparatus, an electronic device, and a readable storage medium.
Background
Paging mechanisms have an important role in processors. Before the processor opens the paging mechanism, the system is required to initialize the corresponding page table, typically by dynamically allocating a segment of memory space for storing the page table through which virtual addresses can be translated into physical addresses. A large number of page fault exceptions are generated during the process of verifying the processor, the verification is interrupted and the required page table needs to be allocated in the page fault exception handling service program, and the exception handling service programs greatly reduce the verification efficiency of the processor.
Disclosure of Invention
In view of this, embodiments of the present application provide a page table creating method, a processor verification method, a page table creating apparatus, an electronic device, and a readable storage medium, which are convenient for improving processor verification efficiency.
In a first aspect, an embodiment of the present application provides a page table creating method, including: determining a virtual address range to be converted according to a maximum access memory address required by a preset test code; applying for required address space for each level of page table according to the virtual address range; initializing each level of page tables to fill a base address of a next level of page tables into a page table entry of a previous level of page tables and to fill a high order of a virtual address into a page table entry of a last level of page tables; wherein, the high order bits of the virtual address are the bits of the virtual address except the offset bit in the page.
According to a specific implementation manner of the embodiment of the application, initialized page tables of each level are used for verifying a processor; before applying for the required address space for each level of page table, the method further comprises: selecting a paging mode and a page size; and determining the page table translation stage number according to the kernel operation mode, the paging mode and the page size of the processor to be verified and the mapping relation among the operation mode, the paging mode, the page size and the page table translation stage number which is established in advance.
According to a specific implementation manner of the embodiment of the present application, the selecting the paging mode includes: and selecting a paging mode according to the kernel operation mode.
According to a specific implementation manner of the embodiment of the present application, the selecting a page size includes: the page size was selected to be 4K,2M or 1G.
According to a specific implementation manner of the embodiment of the present application, the kernel operating mode includes: a classic mode of operation or a long mode of operation.
In a second aspect, an embodiment of the present application provides a processor verification method, which is applied to a processor verification system, where the verification method includes: determining the maximum access memory address of the verification system to determine the range of virtual addresses to be converted; applying for required address space for each level of page table according to the virtual address range; initializing each level of page tables to fill a base address of a next level of page tables into a page table entry of a previous level of page tables and to fill a high order of a virtual address into a page table entry of a last level of page tables; wherein, the high order bits of the virtual address are the bits of the virtual address except the offset bit in the page; updating the base address of the first-level page table to a CR3 control register, and enabling a paging mechanism; according to the base address of the first-stage page table in the CR3 control register and the initialized page tables of all stages, the test code acquires data on a target physical address and/or writes data into the target physical address so as to verify the processor according to the data.
According to a specific implementation manner of the embodiment of the present application, before applying for the required address space for each level of the page table, the method further includes: determining a paging mode and a page size to be opened by the verification system; and determining the page table conversion stage number according to the kernel operation mode, the paging mode and the page size started by the verification system and the mapping relation among the operation mode, the paging mode, the page size and the page table conversion stage number established in advance.
In a third aspect, an embodiment of the present application provides a page table creating apparatus, including: the first determining module is used for determining a virtual address range to be converted according to a maximum access memory address required by a preset test code; the first application module is used for applying for the required address space for each level of page table according to the virtual address range; the first initialization module is used for initializing each level of page tables, so that the base address of the next level of page tables is filled in the page table entry of the last level of page tables, and the high order of the virtual address is filled in the page table entry of the last level of page tables; wherein, the high order bits of the virtual address are the bits of the virtual address except the offset bit in the page.
According to a specific implementation manner of the embodiment of the present application, the apparatus further includes: the selection module is used for selecting a paging mode and a page size before the first application module applies for the address space required by each level of page table; and the second determining module is used for determining the page table translation stage number according to the kernel operation mode, the paging mode and the page size of the processor and the mapping relation among the pre-established operation mode, the paging mode, the page size and the page table translation stage number.
According to a specific implementation manner of the embodiment of the present application, the selection module is specifically configured to: and selecting a paging mode according to the kernel operation mode.
According to a specific implementation manner of the embodiment of the present application, the selection module is specifically configured to: the page size was selected to be 4K,2M or 1G.
According to a specific implementation manner of the embodiment of the present application, the kernel operating mode includes: a classic mode of operation or a long mode of operation.
In a fourth aspect, an embodiment of the present application provides a processor verification apparatus, which is applied to a processor verification system, where the verification apparatus includes: a third determining module, configured to determine a maximum access memory address of the verification system to determine a virtual address range to be converted; the second application module is used for applying for the required address space for each level of page table according to the virtual address range; the second initialization module is used for initializing each level of page tables, so that the base address of the next level of page tables is filled in the page table entry of the previous level of page tables, and the high order of the virtual address is filled in the page table entry of the last level of page tables; wherein, the high order bits of the virtual address are the bits of the virtual address except the offset bit in the page; the updating module is used for updating the base address of the first-level page table into a CR3 control register and enabling a paging mechanism; and the verification module is used for testing the code to acquire data on the target physical address and/or write data into the target physical address according to the base address of the first-stage page table in the CR3 control register and the initialized page tables of all stages so as to verify the processor according to the data.
According to a specific implementation manner of the embodiment of the present application, the apparatus further includes: a fourth determining module, configured to determine a paging mode and a page size to be opened by the verification system before the second applying module applies for the address space required by each level of the page table; and the fifth determining module is used for determining the page table translation stage number according to the kernel operation mode, the paging mode and the page size started and entered by the verification system and the mapping relation among the operation mode, the paging mode, the page size and the page table translation stage number established in advance.
In a fifth aspect, an embodiment of the present application provides an electronic device, including: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor executes a program corresponding to the executable program code by reading the executable program code stored in the memory, and is configured to perform the page table creating method or the processor verifying method according to any of the foregoing implementations.
In a sixth aspect, embodiments of the present application provide a computer-readable storage medium storing one or more programs, where the one or more programs are executable by one or more processors to implement the page table creation method or the processor verification method described in any of the foregoing implementation manners.
The page table creating method, the processor verification device, the electronic apparatus, and the readable storage medium of this embodiment determine a virtual address range to be translated according to a maximum access memory address required by a preset test code, determine the virtual address range to be translated, apply for a required address space for each level of page tables according to the virtual address range, initialize each level of page tables, fill a base address of a next level of page tables into a page table entry of an upper level of page tables, and fill high bits of a virtual address into a page table entry of a last level of page tables, where the high bits of the virtual address are bits of the virtual address except for an offset bit in a page.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic flowchart of a page table creating method according to an embodiment of the present application;
fig. 2 is a schematic flowchart of a page table creating method according to an embodiment of the present application;
FIG. 3 is a diagram illustrating a virtual address to physical address translation according to an embodiment of the present application;
FIG. 4 is a flow chart of a processor executing code;
FIG. 5 is a flowchart illustrating a processor verification method according to an embodiment of the present application;
FIG. 6 is a flowchart illustrating a processor verification method according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a page table creating apparatus according to an embodiment of the present application;
FIG. 8 is a block diagram of a processor verification device according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In order to make the technical idea, embodiments and advantageous effects of the examples of the present application better understood by those skilled in the art, the following detailed description is given by way of specific examples.
According to the page table creating method provided by the embodiment of the application, the verification efficiency of the processor is improved conveniently.
Fig. 1 is a schematic flow diagram of a page table creating method according to an embodiment of the present application, and as shown in fig. 1, the page table creating method according to the embodiment may include:
s101, determining a virtual address range to be converted according to a maximum access memory address required by a preset test code.
If the maximum address accessed by the kernel is 0xFFFFFFFF, the range of virtual addresses to be translated may be determined to be 0x0-0xFFFFFFFF, and page tables may be generated for all pages within the range of addresses.
And determining a virtual address range to be converted according to the maximum access memory address required by the preset test code, and initializing each level of page tables by utilizing the range.
And S102, applying for required address space for each level of page table according to the virtual address range.
According to the virtual address range, the memory address space required by each level of page table can be applied to the operating system. Since the page tables of each stage are stored in the physical memory, the operating system needs to be applied for the page tables of each stage, and enough memory space is reserved for the page tables of each stage.
S103, initializing each level of page tables to fill the base address of the next level of page table into the page table entry of the upper level of page table and fill the high order bits of the virtual address into the page table entry of the last level of page table.
In the process of applying for the address space required by each level of page table, the base address of each level of page table can be determined, so that in the process of initializing each level of page table, the base address of the next level of page table can be filled into the page table entry of the previous level of page table, for example, the base address of the second level of page table can be filled into the page table entry of the first level of page table.
In this embodiment, the high order bits of the virtual address are the bits of the virtual address except the offset bit in the page.
Since the page table entry of the last page table stores the base address of the physical address, and the base address is combined with the bit of the intra-page offset in the virtual address to obtain the physical address corresponding to the virtual address, while the last page table entry in this embodiment stores the bit of the virtual address except for the intra-page offset, so that the physical address can be determined according to the bit of the virtual address except for the intra-page offset and the intra-page offset, that is, the obtained physical address is equal to the virtual address.
In this embodiment, the virtual address range to be converted is determined according to the maximum access memory address required by the preset test code, according to the virtual address range, applying the required address space for each level of page table, initializing each level of page table, the base address of the next page table is filled in the page table item of the upper page table, the high order bit of the virtual address is filled in the page table item of the last page table, wherein the upper bits of the virtual address are the bits of the virtual address except the offset bit in the page, because the page table entry of the last stage page table stores the base address of the physical address, and the physical address corresponding to the virtual address can be obtained according to the base address and the bit of the offset in the page in the virtual address, while the last level page table entry in this embodiment stores bits of the virtual address other than the offset bits within the page, thus, the physical address can be determined based on the bits of the virtual address other than the in-page offset bits and the in-page offset bits, i.e., the resulting physical address is equal to the virtual address, and the virtual address range is determined based on the maximum access memory address required by the preset test code, so that, when the initialized page table is used for verifying the processor, page faults can not be generated, the verification efficiency of the processor is improved, the problem that the running efficiency of the processor is reduced due to the fact that a large number of page fault exceptions are generated in the running process of the test code and are interrupted to enter a page fault exception handling service program is solved, in addition, in the development and compiling process of the verification code of the processor by using the page table of the embodiment, the method can be carried out only by taking the physical address or the virtual address as a standard, so that the development and compilation complexity of the processor verification code can be reduced, and the development and compilation efficiency of the processor verification code can be improved.
In some examples, after initializing each stage of the page tables, the base address of the first stage page tables may be updated into control register CR3 to enable paging mode; attributes such as read/write attributes of page table entries of the page tables at various levels may also be configured.
In this embodiment, initialized page tables of each stage are used for verifying the processor; before applying for the required address space for each level of page table, the method further comprises:
and S104, selecting a paging mode and a page size.
The paging mode is a kernel paging mode, wherein the kernel is a kernel of the processor. The paging mode may include a Page table Address Extension mode (PAE) and a Non-Page table Address Extension mode (Non PAE), and in some examples, the paging mode is selected according to a kernel operating mode. The kernel mode may include a 32-bit classic mode or a 64-bit long mode, and in the classic mode, the paging mode may be Non PAE, and in the long mode, the paging mode may be PAE.
The page size includes 4k,2m or 1G, which affects the number of page table levels required for page table translation.
S105, determining the page table conversion stage number according to the kernel operation mode, the paging mode and the page size of the processor to be verified and the mapping relation among the operation mode, the paging mode, the page size and the page table conversion stage number which is established in advance.
In some examples, the kernel mode of operation may include a classic mode of operation (Legacy mode) or a Long mode of operation (Long mode).
The kernel operating mode, paging mode, and page size of this embodiment affect the number of page table levels.
The mapping relation among the operation mode, the paging mode, the page size and the page table conversion stage number is established in advance, and the page table conversion stage number can be determined according to the mapping relation under the condition of determining the kernel operation mode, the paging mode and the page size.
The following describes the embodiments of the present application in detail with reference to a specific example.
Referring to fig. 2, the page table creating method of the present embodiment may include:
s11, selecting a paging mode of a kernel and a page table size.
The paging mode of the selected kernel includes Non PAE or PAE, and the page table size is 4K,2M or 1G.
The page table entry used by the Non PAE mode is 32 bits, and the page table entry used by the PAE mode is 64 bits; the page table size determines the number of page table entries needed for page table translation.
And S12, determining the stage number of the page table according to the kernel operation mode, the paging mode and the page table size.
For example, if the kernel runs in 32Bit Legacy mode, selecting PAE paging and 4K page table size, a 3-level page table (PDPE, PDE, PTE) is required.
And S13, determining the maximum memory address accessed by the kernel to determine the virtual address range needing to be converted.
For example, the maximum address accessed by the kernel is 0 xfffffffff, and all pages with virtual addresses ranging from 0x0 to 0 xfffffffff need to generate corresponding page tables.
And S14, applying for memory address space required by each level of page table.
Since each page table is stored in physical memory, sufficient memory space needs to be reserved for each page table.
And S15, initializing page tables of all levels.
Here, the first-level page table entry needs to be filled in the base address of the second-level page table, the second-level page table entry needs to be filled in the base address of the third-level page table, and the third-level page table entry needs to be filled in the upper bits of the virtual address of the page. Finally, attribute configuration of each level of page table needs to be filled in.
S16, updating to a CR3 register, and enabling a paging mechanism.
The base address of the first level page table is updated to the CR3 register and the kernel may enable the paging mechanism.
Referring to FIG. 3, the kernel chooses to use a 4K paging mode as the PAE paging mechanism, and for a 32-Bit virtual address, only the 20-Bit high address needs to be translated according to the page table, and the 12-Bit low address needs to be used as the page offset, and no translation is performed. Virtual address 0x12345678 is mapped to physical address 0x12345678.
In this embodiment, before the paging mechanism is started by the processor system, the page table is initialized, and all pages included in the maximum virtual address accessed by the system can be replaced by the same physical address, so that it can be ensured that the verification case (case) is compiled and run by the physical address, and the paging mechanism of the processor can also be started. And the page fault exception can not be generated in the system operation process, and the execution efficiency of the processor is improved.
Referring to fig. 4, after the processor starts the paging mechanism, all the accessed memory addresses are virtual addresses, and are converted into physical addresses through the page table of the memory management unit, and instructions or data are obtained from the memory module and enter a program for verifying the processor.
An embodiment of the present application provides a processor verification method, which can improve processor verification efficiency.
Referring to fig. 5, a processor verification method provided in an embodiment of the present application is applied to a processor verification system, and the verification method of the embodiment may include:
s201, determining the maximum access memory address of the verification system to determine the virtual address range to be converted.
If the maximum address accessed by the kernel is 0xFFFFFFFF, the range of virtual addresses to be translated may be determined to be 0x0-0xFFFFFFFF, and page tables may be generated for all pages within the range of addresses.
The virtual address range to be converted is determined according to the maximum access memory address required by the preset test code, and the range is utilized to initialize each level of page table, so that the preset test code does not generate page fault abnormity in the running process, the execution efficiency is improved, and the problem that the running efficiency of a processor is reduced due to the fact that a large amount of page fault abnormity is generated in the running process of the test code and is interrupted to enter a page fault abnormity processing service program is solved.
S202, according to the virtual address range, the required address space is applied for each level of page table.
According to the virtual address range, the memory address space required by each level of page table can be applied to the operating system. Because each level of page table is stored in a physical memory, an application needs to be made to an operating system to reserve enough memory space for each level of page table.
S203, initializing each level of page table to fill the base address of the next level of page table into the page table entry of the previous level of page table, and filling the high order bits of the virtual address into the page table entry of the last level of page table.
In the process of applying for the address space required by each level of page table, the base address of each level of page table can be determined, so that in the process of initializing each level of page table, the base address of the next level of page table can be filled into the page table entry of the previous level of page table, for example, the base address of the second level of page table can be filled into the page table entry of the first level of page table.
In this embodiment, the high order bits of the virtual address are the bits of the virtual address except the offset bit in the page.
Since the page table entry of the last page table stores the base address of the physical address, and the base address is combined with the bit of the intra-page offset in the virtual address to obtain the physical address corresponding to the virtual address, while the last page table entry in this embodiment stores the bit of the virtual address except for the intra-page offset, so that the physical address can be determined according to the bit of the virtual address except for the intra-page offset and the intra-page offset, that is, the obtained physical address is equal to the virtual address.
S204, updating the base address of the first-level page table into a CR3 control register, and enabling a paging mechanism.
The first stage page table is a first stage page table of the initialization page table.
S205, according to the base address of the first-stage page table in the CR3 control register and the initialized page tables of all stages, the test code obtains data on a target physical address and/or writes data into the target physical address so as to verify the processor according to the data.
The value in the CR3 control register is the base address of the first stage page table.
In the process of running the test code, data can be read from the memory or written into the memory through the initialized page table, in this embodiment, when the test code runs, data can be written into the memory or read from the memory according to the base address of the first-stage page table in the CR3 control register and the initialized page tables of each stage, and the processor is verified according to the written and/or read data.
In this embodiment, the maximum access memory address of the verification system is determined to determine the virtual address range to be translated, the required address space is applied for each level of page table according to the virtual address range, each level of page table is initialized, the base address of the next level of page table is filled in the page table entry of the previous level of page table, the high bits of the virtual address are filled in the page table entry of the last level of page table, wherein the high bits of the virtual address are bits of the virtual address except for the offset bit in the page, since the base address of the physical address is stored in the page table entry of the last level of page table, and the physical address corresponding to the virtual address can be obtained according to the base address and the bit of the offset in the page in the virtual address, and in this embodiment, the bits of the virtual address except for the offset bit in the page are stored in the last level of page table entry, thus, the physical address can be determined according to the bit in the virtual address except the offset bit in the page and the offset bit in the page, that is, the obtained physical address is equal to the virtual address, and the virtual address range is determined according to the maximum access memory address required by the preset test code, so that, according to the base address of the first-stage page table in the CR3 control register and the initialized page tables of each stage, the test code obtains the data on the target physical address and/or writes the data into the target physical address, so as to verify the processor according to the data, no page fault is generated, the processor verification efficiency is improved, the problem that the running efficiency of the processor is reduced due to the fact that a large number of page fault exceptions are generated during the running process of the test code and are interrupted to enter the page fault exception handling service program is avoided, in addition, during the development and compilation process of the processor verification code by using the page table of this embodiment, the method can be performed only by taking the physical address or the virtual address as a standard, so that the development and compilation complexity of the processor verification code can be reduced, the development and compilation efficiency of the processor verification code can be improved, and further, the processor verification efficiency can be improved.
The present application further includes a third embodiment, which is substantially the same as the first embodiment, and is different in that before applying for the required address space for each level of the page table, the method of the present embodiment may further include:
s206, determining the page mode and the page size to be opened by the verification system.
The paging mode is a kernel paging mode, wherein the kernel is a kernel of the processor. The paging mode may include Non PAE or PAE, and in some examples, the Non PAE mode uses 32 bits of page table entries and the PAE mode uses 64 bits of page table entries.
The page size includes 4k,2m or 1G, which affects the number of page table levels required for page table translation.
S207, determining the page table conversion stage number according to the kernel operation mode, the paging mode and the page size started by the verification system, and the mapping relation among the operation mode, the paging mode, the page size and the page table conversion stage number established in advance.
In some examples, the kernel mode of operation may include Legacy mode or Long mode.
The kernel mode of operation, paging mode, and page size of this embodiment affect the number of page tables.
The mapping relation among the operation mode, the paging mode, the page size and the page table conversion stage number is established in advance, and the page table conversion stage number can be determined according to the mapping relation under the condition of determining the kernel operation mode, the paging mode and the page size.
Referring to fig. 6, an embodiment of a page table initialization method in a verification system is described below, which is implemented specifically as follows:
and S21, selecting a system kernel paging mode and a page size.
The X86 processor verifies that when the system is initialized in a starting mode, the paging mode and the page size to be opened by a system kernel are selected, and corresponding registers are configured.
And S22, determining the stage number of page table conversion.
The number of levels of page table translation is determined based on the operating mode, paging mode, and page size that the X86 processor verifies the system is booted into.
And S23, applying for physical address spaces required by the page tables of all levels.
Physical address spaces required by page tables at all levels are applied, and the physical address spaces are ensured to be unoccupied.
And S24, determining the maximum access memory address in the verification system, and determining the converted virtual address range.
And S25, initializing page tables of each level.
Initializing each page table entry value according to a specific rule, filling a base address of a lower page table in an upper page table, filling high bits of a virtual address in a last page table slowly, ensuring that the virtual address is equal to a physical address, configuring attributes of each page table, and finally generating the page table.
S26, updating the CR3 control register and enabling paging.
The page table base address, i.e., the CR3 control register, is updated. The paging mechanism is enabled.
S27, regression verification case.
The regression processor verifies the test case (case).
Under the conditions that the regression test cases are large in number and strong in randomness, the page table of the embodiment can still be used for ensuring that page missing abnormity cannot be generated in the whole regression test, and the verification efficiency is effectively improved.
The processor needs to perform regression testing on a large number of verification cases in the verification process, and after a paging mechanism of the processor is started, because memory locations where data and instructions in the verification cases are stored have certain randomness, in the prior art, a processor may generate a large number of page fault exceptions when executing a large number of verification cases, and a required page table needs to be allocated in a page fault exception handler, and a page fault exception service routine is not the content of the verification processor Case and belongs to an invalid verification code, and frequently enters a page fault exception service function, which may reduce the processor verification efficiency.
In the embodiment, the page table is initialized in the processor verification system, and all pages contained in the maximum virtual address accessed by the system are replaced by the same physical address, so that the verification Case can be guaranteed to be compiled and operated by the physical address, meanwhile, the page missing exception cannot be generated in the operation process of the system, and the verification efficiency of the processor is improved.
An embodiment of the present application provides a page table creating apparatus, which is convenient for improving processor verification efficiency.
Fig. 7 is a schematic structural diagram of a page table creating device according to an embodiment of the present application, and as shown in fig. 7, the page table creating device according to the embodiment may include: the first determining module 11 is configured to determine a virtual address range to be converted according to a maximum access memory address required by a preset test code; a first application module 12, configured to apply for a required address space for each level of page table according to the virtual address range; a first initialization module 13, configured to initialize each level of page table, so as to fill a base address of a next level of page table into a page table entry of an upper level of page table, and fill a high bit of a virtual address into a page table entry of a last level of page table; wherein, the high order bits of the virtual address are the bits of the virtual address except the offset bit in the page.
The apparatus of this embodiment may be used to implement the technical solution of the method embodiment shown in fig. 1, and the implementation principle and the technical effect are similar, which are not described herein again.
The apparatus of this embodiment determines the range of virtual addresses to be converted according to the maximum access memory address required by the preset test code, according to the virtual address range, applying the required address space for each level of page table, initializing each level of page table, the base address of the next page table is filled in the page table item of the upper page table, the high order bit of the virtual address is filled in the page table item of the last page table, wherein the upper bits of the virtual address are the bits of the virtual address except the offset bit in the page, because the page table entry of the last-level page table stores the base address of the physical address, and the physical address corresponding to the virtual address can be obtained according to the base address and the bit of the offset in the page in the virtual address, while the last level page table entry in this embodiment stores bits of the virtual address other than the offset bits within the page, thus, the physical address can be determined based on the bits of the virtual address other than the in-page offset bits and the in-page offset bits, i.e., the resulting physical address is equal to the virtual address, and the virtual address range is determined based on the maximum access memory address required by the preset test code, so that, when the initialized page table is used for verifying the processor, page faults can not be generated, the verification efficiency of the processor is improved, the problem that the running efficiency of the processor is reduced due to the fact that a large number of page fault exceptions are generated in the running process of the test code and are interrupted to enter a page fault exception handling service program is solved, in addition, in the development and compiling process of the verification code of the processor by using the page table of the embodiment, the method can be carried out only by taking the physical address or the virtual address as a standard, so that the development and compilation complexity of the processor verification code can be reduced, and the development and compilation efficiency of the processor verification code can be improved.
As an optional embodiment, the apparatus further comprises: the selection module is used for selecting a paging mode and page size before the first application module applies for the address space required by each level of page table; and the second determining module is used for determining the page table conversion stage number according to the kernel operating mode, the paging mode and the page size of the processor and the mapping relation among the operating mode, the paging mode, the page size and the page table conversion stage number which is established in advance.
As an optional implementation manner, the selection module is specifically configured to: selecting paging mode according to kernel operation mode。
As an optional implementation manner, the selection module is specifically configured to: the page size was selected to be 4K,2M or 1G.
As an optional embodiment, the kernel operating mode includes: a classic mode of operation or a long mode of operation.
The apparatus of the foregoing embodiment may be configured to implement the technical solution of the foregoing method embodiment, and the implementation principle and the technical effect are similar, which are not described herein again.
An embodiment of the application provides a processor verification device, which can improve processor verification efficiency.
Fig. 8 is a schematic structural diagram of a processor verification apparatus according to an embodiment of the present application, and as shown in fig. 8, the processor verification apparatus according to the embodiment is applied to a processor verification system, and the verification apparatus may include: a third determining module 21, configured to determine a maximum access memory address of the verification system to determine a virtual address range to be converted; a second application module 22, configured to apply for a required address space for each level of page table according to the virtual address range; a second initialization module 23, configured to initialize each level of page table, so as to fill a base address of a next level of page table into a page table entry of a previous level of page table, and fill a high bit of a virtual address into a page table entry of a last level of page table; wherein, the high order of the virtual address is the bit of the virtual address except the offset bit in the page; an updating module 24, configured to update the base address of the first-level page table into a CR3 control register, and enable a paging mechanism; and the verification module 25 is configured to, according to the base address of the first-stage page table in the CR3 control register and the initialized page tables of each stage, test the code to obtain data at the target physical address and/or write data into the target physical address, so as to verify the processor according to the data.
The apparatus of this embodiment may be used to implement the technical solution of the method embodiment shown in fig. 5, and the implementation principle and the technical effect are similar, which are not described herein again.
In this embodiment, the maximum access memory address of the verification system is determined to determine the virtual address range to be translated, the required address space is applied for each level of page table according to the virtual address range, each level of page table is initialized, the base address of the next level of page table is filled in the page table entry of the previous level of page table, the high bits of the virtual address are filled in the page table entry of the last level of page table, wherein the high bits of the virtual address are bits of the virtual address except for the offset bit in the page, since the base address of the physical address is stored in the page table entry of the last level of page table, and the physical address corresponding to the virtual address can be obtained according to the base address and the bit of the offset in the page in the virtual address, and in this embodiment, the bits of the virtual address except for the offset bit in the page are stored in the last level of page table entry, thus, the physical address can be determined according to the bit in the virtual address except the offset bit in the page and the offset bit in the page, that is, the obtained physical address is equal to the virtual address, and the virtual address range is determined according to the maximum access memory address required by the preset test code, so that, according to the base address of the first-stage page table in the CR3 control register and the initialized page tables of each stage, the test code obtains the data on the target physical address and/or writes the data into the target physical address, so as to verify the processor according to the data, no page fault is generated, the processor verification efficiency is improved, the problem that the running efficiency of the processor is reduced due to the fact that a large number of page fault exceptions are generated during the running process of the test code and are interrupted to enter the page fault exception handling service program is avoided, in addition, during the development and compilation process of the processor verification code by using the page table of this embodiment, the method can be performed only by taking the physical address or the virtual address as a standard, so that the development and compilation complexity of the processor verification code can be reduced, the development and compilation efficiency of the processor verification code can be improved, and further, the processor verification efficiency can be improved.
As an optional implementation, the apparatus further comprises: a fourth determining module, configured to determine a paging mode and a page size to be opened by the verification system before the second applying module applies for the address space required by each level of the page table; and the fifth determining module is used for determining the page table translation stage number according to the kernel operation mode, the paging mode and the page size started and entered by the verification system and the mapping relation among the operation mode, the paging mode, the page size and the page table translation stage number established in advance.
The apparatus of the foregoing embodiment may be configured to implement the technical solution of the foregoing method embodiment, and the implementation principle and the technical effect are similar, which are not described herein again.
Fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application, and as shown in fig. 9, the electronic device may include: the electronic device comprises a shell 61, a processor 62, a memory 63, a circuit board 64 and a power circuit 65, wherein the circuit board 64 is arranged inside a space enclosed by the shell 61, and the processor 62 and the memory 63 are arranged on the circuit board 64; a power supply circuit 65 for supplying power to each circuit or device of the electronic apparatus; the memory 63 is used to store executable program code; the processor 62 reads the executable program code stored in the memory 63 to run a program corresponding to the executable program code, so as to execute any page table creating method or processor verifying method provided in the foregoing embodiments, and thus corresponding advantageous technical effects can also be achieved.
The electronic devices described above exist in a variety of forms, including but not limited to:
(1) A mobile communication device: such devices are characterized by mobile communications capabilities and are primarily targeted at providing voice and data communications. Such terminals include: smart phones (e.g., iphones), multimedia phones, functional phones, and low-end phones, among others.
(2) Ultra mobile personal computer device: the equipment belongs to the category of personal computers, has calculation and processing functions and generally has the characteristic of mobile internet access. Such terminals include: PDA, MID, and UMPC devices, etc., such as ipads.
(3) A portable entertainment device: such devices may display and play multimedia content. This kind of equipment includes: audio, video players (e.g., ipods), handheld game consoles, electronic books, and smart toys and portable car navigation devices.
(4) A server: the device for providing the computing service comprises a processor, a hard disk, a memory, a system bus and the like, and the server is similar to a general computer architecture, but has higher requirements on processing capacity, stability, reliability, safety, expandability, manageability and the like because of the need of providing high-reliability service.
(5) And other electronic equipment with a data interaction function.
Accordingly, an embodiment of the present application further provides a computer-readable storage medium, where one or more programs are stored, and the one or more programs can be executed by one or more processors to implement any one of the page table creating methods or the processor verification methods provided in the foregoing embodiments, so that corresponding technical effects can also be achieved, which have been described in detail above and are not described herein again.
It should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on differences from other embodiments.
In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
For convenience of description, the above devices are described separately in terms of functional division into various units/modules. Of course, the functionality of the various units/modules may be implemented in the same one or more pieces of software and/or hardware when the application is implemented.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (12)
1. A page table creation method, comprising:
determining a virtual address range to be converted according to a maximum access memory address required by a preset test code;
applying for required address space for each level of page table according to the virtual address range;
initializing each level of page tables to fill a base address of a next level of page tables into a page table entry of an upper level of page tables and fill a high order of a virtual address into a page table entry of a last level of page tables; wherein, the high order bits of the virtual address are the bits of the virtual address except the offset bit in the page.
2. The method of claim 1, wherein initialized page tables of each stage are used to validate the processor; before applying for the required address space for each level of page table, the method further comprises:
selecting a paging mode and a page size;
and determining the page table translation stage number according to the kernel operation mode, the paging mode and the page size of the processor to be verified and the mapping relation among the operation mode, the paging mode, the page size and the page table translation stage number which is established in advance.
3. The method of claim 2, wherein selecting the paging mode comprises:
and selecting a paging mode according to the kernel operation mode.
4. The method of claim 2, wherein the kernel run mode comprises: a classic mode of operation or a long mode of operation.
5. A processor verification method applied to a processor verification system, the verification method comprising:
determining the maximum access memory address of the verification system to determine the virtual address range to be converted;
applying for required address space for each level of page table according to the virtual address range;
initializing each level of page tables to fill a base address of a next level of page tables into a page table entry of an upper level of page tables and fill a high order of a virtual address into a page table entry of a last level of page tables; wherein, the high order bits of the virtual address are the bits of the virtual address except the offset bit in the page;
updating the base address of the first-level page table to a CR3 control register, and enabling a paging mechanism;
according to the base address of the first-stage page table in the CR3 control register and the initialized page tables of all stages, the test code obtains data on a target physical address and/or writes data into the target physical address so as to verify the processor according to the data.
6. The method of claim 5, wherein prior to applying for the required address space for the stages of page tables, the method further comprises:
determining a paging mode and a page size to be opened by the verification system;
and determining the page table conversion stage number according to the kernel operation mode, the paging mode and the page size started by the verification system and the mapping relation among the operation mode, the paging mode, the page size and the page table conversion stage number established in advance.
7. A page table creation apparatus, comprising:
the first determining module is used for determining a virtual address range to be converted according to a maximum access memory address required by a preset test code;
the first application module is used for applying for the required address space for each level of page table according to the virtual address range;
the first initialization module is used for initializing each level of page tables, so that the base address of the next level of page tables is filled in the page table entry of the last level of page tables, and the high order of the virtual address is filled in the page table entry of the last level of page tables; wherein, the high order bits of the virtual address are the bits of the virtual address except the offset bit in the page.
8. The apparatus of claim 7, further comprising:
the selection module is used for selecting a paging mode and a page size before the first application module applies for the address space required by each level of page table;
and the second determining module is used for determining the page table conversion stage number according to the kernel operating mode, the paging mode and the page size of the processor and the mapping relation among the operating mode, the paging mode, the page size and the page table conversion stage number which is established in advance.
9. A processor authentication apparatus applied to a processor authentication system, the apparatus comprising:
a third determining module, configured to determine a maximum access memory address of the verification system to determine a virtual address range to be converted;
the second application module is used for applying for the required address space for each level of page table according to the virtual address range;
the second initialization module is used for initializing each level of page tables, so that the base address of the next level of page tables is filled in the page table entry of the previous level of page tables, and the high order of the virtual address is filled in the page table entry of the last level of page tables; wherein, the high order bits of the virtual address are the bits of the virtual address except the offset bit in the page;
the updating module is used for updating the base address of the first-level page table into a CR3 control register and enabling a paging mechanism;
and the verification module is used for testing the code to acquire data on the target physical address and/or write data into the target physical address according to the base address of the first-stage page table in the CR3 control register and the initialized page tables of all stages so as to verify the processor according to the data.
10. The apparatus of claim 9, further comprising:
a fourth determining module, configured to determine a paging mode and a page size to be opened by the verification system before the second applying module applies for the address space required by each level of the page table;
and a fifth determining module, configured to determine the page table translation stage number according to the kernel operation mode, the paging mode, and the page size that are started and entered by the verification system, and a mapping relationship among a pre-established operation mode, a pre-established paging mode, a pre-established page size, and a pre-established page table translation stage number.
11. An electronic device, characterized in that the electronic device comprises: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor executes a program corresponding to the executable program code by reading the executable program code stored in the memory for performing the page table creation method of any one of the preceding claims 1 to 4 or the processor verification method of any one of the preceding claims 5 to 6.
12. A computer readable storage medium storing one or more programs, the one or more programs being executable by one or more processors to implement the page table creation method of any preceding claim 1 to 4 or the processor verification method of any preceding claim 5 to 6.
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| CN117077589A (en) * | 2023-10-17 | 2023-11-17 | 中电科申泰信息科技有限公司 | Virtual and physical address conversion verification method and system based on UVM architecture |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117077589A (en) * | 2023-10-17 | 2023-11-17 | 中电科申泰信息科技有限公司 | Virtual and physical address conversion verification method and system based on UVM architecture |
| CN117077589B (en) * | 2023-10-17 | 2023-12-15 | 中电科申泰信息科技有限公司 | Virtual and physical address conversion verification method and system based on UVM architecture |
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