CN112269665B - Memory processing method and device, electronic equipment and storage medium - Google Patents

Memory processing method and device, electronic equipment and storage medium Download PDF

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CN112269665B
CN112269665B CN202011526583.3A CN202011526583A CN112269665B CN 112269665 B CN112269665 B CN 112269665B CN 202011526583 A CN202011526583 A CN 202011526583A CN 112269665 B CN112269665 B CN 112269665B
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memory
memory block
address
target
block
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CN112269665A (en
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邱海港
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Beijing Kingsoft Cloud Network Technology Co Ltd
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Beijing Kingsoft Cloud Network Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5022—Mechanisms to release resources

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  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)

Abstract

The application provides a memory processing method and device, an electronic device and a storage medium, wherein the method comprises the following steps: acquiring a first memory address of a released first memory block, wherein the first memory block is a memory block of a memory address to be stored in a target memory; performing hash calculation on the first memory address to obtain a target hash value corresponding to the first memory address; searching a target position corresponding to the target hash value in a target array, wherein the memory address of the released memory block in the target memory is stored in the position corresponding to the hash value of the memory address of the released memory block in the target array; and merging the first memory block and the second memory block into a third memory block under the condition that the memory address of the second memory block is found in the target position. By the method and the device, the problems of low memory reuse rate and memory resource waste in a memory allocation mode in the related technology are solved.

Description

Memory processing method and device, electronic equipment and storage medium
Technical Field
The present application relates to the field of data processing, and in particular, to a method and an apparatus for processing a memory, an electronic device, and a storage medium.
Background
In the related art, during the database transaction process, a memory data page (page) may be requested, and the requested memory size is about 16 k. The released (free) memory blocks are stored in a freelist linked list (a space table can be used), and the freelist linked list is stored according to the released sequence to form an idle memory linked list storing a plurality of memory blocks.
Adjacent memory blocks may not be adjacent in the freelist linked list, so that a plurality of memory fragments are formed by adjacent free memories in the freelist linked list. If a large memory block is applied, and the size of the applied memory block is larger than that of the memory block in freelist, then the memory block in freelist cannot be used, and only the memory block can be applied again from the memory, so that the memory reuse rate in freelist is low, and the memory resource waste is caused.
Therefore, the memory allocation method in the related art has the problems of low memory reuse rate and memory resource waste.
Disclosure of Invention
The application provides a memory processing method and device, electronic equipment and a storage medium, which are used for at least solving the problems of low memory reuse rate and memory resource waste in a memory allocation mode in the related technology.
According to an aspect of an embodiment of the present application, a method for processing a memory is provided, including: acquiring a first memory address of a released first memory block, wherein the first memory block is a memory block of a memory address to be stored in a target memory; performing hash calculation on the first memory address to obtain a target hash value of the first memory address; searching a target position corresponding to the target hash value in a target array, wherein the memory address of the released memory block in the target memory is stored in the position corresponding to the hash value of the memory address of the released memory block in the target array; and merging the first memory block and the second memory block into a third memory block under the condition that the memory address of the second memory block is found in the target position.
Optionally, the target hash value includes a first hash value of a start address of the first memory address and a second hash value of an end address of the first memory address, and the target location includes a first location corresponding to the first hash value and a second location corresponding to the second hash value; merging the first memory block and the second memory block into the third memory block includes: determining a start address of the second memory block as a start address of the third memory block and determining an end address of the first memory block as an end address of the third memory block under the condition that the memory address of the second memory block is found at the first position; determining the starting address of the first memory block as the starting address of the third memory block and determining the ending address of the second memory block as the ending address of the third memory block under the condition that the memory address of the second memory block is found at the second position; determining a start address of the first sub-memory block as a start address of the third memory block and determining an end address of the second sub-memory block as an end address of the third memory block under the condition that the memory address of the first sub-memory block is found at the first position and the memory address of the second sub-memory block is found at the second position, wherein the second memory block includes the first sub-memory block and the second sub-memory block.
Optionally, after the merging the first memory chunk and the second memory chunk into the third memory chunk, the method further includes: writing the memory address of the third memory block into a third position and a fourth position in the target array, where the third position is a position in the target array corresponding to the hash value of the start address of the third memory block, and the fourth position is a position in the target array corresponding to the hash value of the end address of the third memory block.
Optionally, after the merging the first memory chunk and the second memory chunk into the third memory chunk, the method further includes: removing the memory addresses of the second memory block stored at a fifth position and a sixth position in the target array, where the fifth position is a position in the target array corresponding to the hash value of the start address of the second memory block, and the sixth position is a position in the target array corresponding to the hash value of the end address of the second memory block.
Optionally, the method further comprises: obtaining a memory application instruction of a target transaction, wherein the memory application instruction is used for applying for a memory block with a target size; responding to the memory application instruction, and searching the target array according to the target size; and under the condition that a fourth memory block with the memory block size larger than or equal to the target size is found, allocating a fifth memory block to the target transaction, wherein the fifth memory block is a part of the fourth memory block and the memory size is the target size.
Optionally, searching for the target array according to the target size includes: sequentially searching each memory address stored in the target array, and determining whether a memory block with the size of the target memory block exists; and under the condition that the memory block with the size of the target size is not found, sequentially finding each memory address stored in the target array, and determining whether the memory block with the size larger than the target size exists.
Optionally, after allocating a fifth memory block for the target transaction, the method further includes: removing the memory address of the fourth memory block from the target array; and under the condition that the size of the fourth memory block is larger than the target size, writing the memory address of a sixth memory block into a position, corresponding to the hash value of the memory address of the sixth memory block, in the target array, where the sixth memory block is a memory block, except for the fifth memory block, in the fourth memory block.
According to another aspect of the embodiments of the present application, there is provided a memory processing apparatus, including: a first obtaining unit, configured to obtain a first memory address of a released first memory block, where the first memory block is a memory block to be stored with a memory address in a target memory; the computing unit is used for carrying out Hash computation on the first memory address to obtain a target Hash value corresponding to the first memory address; a first searching unit, configured to search a target position corresponding to the target hash value in a target array, where a memory address of a released memory block in the target memory is stored in a position corresponding to the hash value of the memory address of the released memory block in the target array; a merging unit, configured to merge the first memory block and the second memory block into a third memory block when the memory address of the second memory block is found in the target location.
Optionally, the target hash value includes a first hash value of a start address of the first memory address and a second hash value of an end address of the first memory address, and the target location includes a first location corresponding to the first hash value and a second location corresponding to the second hash value; the merging unit includes: a first determining module, configured to determine a start address of the second memory block as a start address of the third memory block and determine an end address of the first memory block as an end address of the third memory block when the memory address of the second memory block is found at the first location; a second determining module, configured to determine, when the memory address of the second memory block is found at the second location, a start address of the first memory block as a start address of the third memory block, and determine an end address of the second memory block as an end address of the third memory block; a third determining module, configured to determine a start address of the first sub-memory block as a start address of the third memory block and determine an end address of the second sub-memory block as an end address of the third memory block when the memory address of the first sub-memory block is found in the first location and the memory address of the second sub-memory block is found in the second location, where the second memory block includes the first sub-memory block and the second sub-memory block.
Optionally, the apparatus further comprises: a first writing unit, configured to write the memory address of the third memory block into a third location and a fourth location in the target array, where the third location is a location in the target array corresponding to a hash value of a start address of the third memory block, and the fourth location is a location in the target array corresponding to a hash value of an end address of the third memory block.
Optionally, the apparatus further comprises: a first removing unit, configured to remove the memory address of the second memory block stored at a fifth location and a sixth location in the target array, where the fifth location is a location in the target array corresponding to a hash value of a start address of the second memory block, and the sixth location is a location in the target array corresponding to a hash value of an end address of the second memory block.
Optionally, the apparatus further comprises: a second obtaining unit, configured to obtain a memory application instruction of a target transaction, where the memory application instruction is used to apply for a memory block of a target size; the second searching unit is used for responding to the memory application instruction and searching the target array according to the target size; an allocating unit, configured to allocate a fifth memory block to the target transaction when a fourth memory block with a memory block size that is greater than or equal to the target size is found, where the fifth memory block is a part of the fourth memory block and the memory size is the target size.
Optionally, the second lookup unit includes: the first searching module is used for sequentially searching each memory address stored in the target array and determining whether a memory block with the size of the target memory block exists or not; and a second searching module, configured to sequentially search each memory address stored in the target array when a memory block with a size equal to the target size is not found, and determine whether a memory block with a size larger than the target size exists.
Optionally, the apparatus further comprises: a second removing unit, configured to remove the memory address of the fourth memory block from the target array after the fifth memory block is allocated to the target transaction; a second writing unit, configured to, when the size of the fourth memory block is greater than the target size, write the memory address of a sixth memory block into a position, in the target array, corresponding to the hash value of the memory address of the sixth memory block, where the sixth memory block is a memory block, in the fourth memory block, other than the fifth memory block.
According to another aspect of the embodiments of the present application, there is also provided an electronic device, including a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory communicate with each other through the communication bus; wherein the memory is used for storing the computer program; a processor for performing the method steps in any of the above embodiments by running the computer program stored on the memory.
According to a further aspect of the embodiments of the present application, there is also provided a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to perform the method steps of any of the above embodiments when the computer program is executed.
In the embodiment of the present application, a method of storing a memory address of a released memory block in an array according to a hash value of the memory address is adopted, and a first memory address of a released first memory block is obtained, where the first memory block is a memory block to be stored with the memory address in a target memory; performing hash calculation on the first memory address to obtain a target hash value corresponding to the first memory address; searching a target position corresponding to the target hash value in the target array, wherein the memory address of the released memory block in the target memory is stored in the position corresponding to the hash value of the memory address of the released memory block in the target array; under the condition that the memory address of the second memory block is found at the target position, the first memory block and the second memory block are combined into a third memory block, the freelist is modified into an array from a linked list, the memory address of the released memory block is stored at the position, corresponding to the hash value of the memory address, in the array, when the memory block is released, data is searched according to the hash value of the memory address, whether the memory block adjacent to the released memory block exists in the released memory block can be conveniently and quickly determined (through the hash value search, the performance search with the complexity of O (1) can be realized), so that the purpose of quickly combining the adjacent memory blocks can be realized, the memory blocks in the freelist can be conveniently recycled when the subsequent memory application is carried out, the technical effects of reducing the waste of memory resources and improving the memory recycling rate are achieved, and the problem that the memory allocation mode in the related technology has low memory recycling rate, The waste of memory resources.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic diagram of a hardware environment of an alternative memory processing method according to an embodiment of the present invention;
fig. 2 is a schematic flowchart of an optional memory processing method according to an embodiment of the present application;
fig. 3 is a schematic flow chart illustrating another alternative memory processing method according to an embodiment of the present application;
fig. 4 is a block diagram of a processing apparatus with an optional memory according to an embodiment of the present application;
fig. 5 is a block diagram of an alternative electronic device according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
According to an aspect of an embodiment of the present application, a method for processing a memory is provided. Alternatively, in this embodiment, the processing method of the memory may be applied to a hardware environment formed by the terminal 102 and the server 104 (local host of the database) as shown in fig. 1. As shown in fig. 1, the server 104 is connected to the terminal 102 through a network, and may be configured to provide services (e.g., game services, application services, etc.) for the terminal or a client installed on the terminal, and may be configured with a database on the server or separately from the server, and configured to provide data storage services for the server 104.
The network 104 includes, but is not limited to, at least one of: a wired network, a wireless network, which may include, but is not limited to, at least one of: a wide area network, a metropolitan area network, or a local area network, which may include, but is not limited to, at least one of: bluetooth, WIFI (Wireless Fidelity), and other networks that enable Wireless communication. The terminal 102 may be a terminal for computing data, such as a mobile terminal (e.g., a mobile phone, a tablet computer), a notebook computer, a PC, and the like. The server may include, but is not limited to, any hardware device capable of performing computations.
The memory processing method in the embodiment of the present application may be executed by the server 104, or executed by the terminal 102, or executed by both the server 104 and the terminal 102. The terminal 102 may execute the memory processing method according to the embodiment of the present application by a client installed thereon.
Taking the server 104 to execute the memory processing method in this embodiment as an example, fig. 2 is a schematic flow chart of an optional memory processing method according to an embodiment of the present application, and as shown in fig. 2, the flow of the method may include the following steps:
step S202 is to acquire a first memory address of a released first memory block, where the first memory block is a memory block to be stored with a memory address in a target memory.
The memory processing method in this embodiment may be applied to a memory management scenario in a database. For other scenarios where memory blocks need to be allocated for the memory application, the memory processing method in this embodiment is also applicable.
The memory address of the memory block requested by the memory application can be represented by a start address and an end address, that is, by a memory block coordinate [ startaddr, endaddr ], where startaddr is the start address (start memory address) and endaddr is the end address (end memory address). When the memory block is released, the server can store the memory address of the memory block. For example, the currently released memory block is a first memory block, the server may obtain a first memory address of the first memory block, and the first memory address may include: a start address of the first memory block and an end address of the first memory block.
For example, the memory block coordinates [ start memory address, end address) of the memory application are as follows: [0,50),[50,70),[70,80),[80,100),[100,150),[150,350),[350,410),[410,450),[450,460). Part of the memory has been released, the memory locations and order of the release being: [70,80) - > [100,150) - > [450,460) - > [80,100) - > [0,50 ]. The currently released memory chunks are: [80,100), then the currently freed memory chunks include: [70,80),[100,150),[450,460).
Step S204, perform hash calculation on the first memory address to obtain a target hash value corresponding to the first memory address.
In order to improve the searching efficiency of the array and reduce the storage space occupied by the array, the memory address may be mapped, different memory addresses may be mapped to different identifiers (for example, subscripts of the array), and different identifiers may correspond to different positions of the target array, that is, the memory address of the memory block is stored in a position where the identifier mapped by the memory address is used as a subscript.
Optionally, in this embodiment, the hash value of the memory address may be calculated by a hash (hash) algorithm. The hash function used may be configured as required, and may be, for example: the value of the memory address is obtained by subtracting the size of the minimum memory block allocated during the memory application, and the obtained value is the hash value of the memory address.
After obtaining the first memory address of the first memory block, the server may perform hash calculation on the first memory address to obtain a target hash value corresponding to the first memory address, where the target hash value includes a first hash value obtained by performing hash calculation on a start address of the first memory address and a second hash value obtained by performing hash calculation on an end address of the first memory address.
For example, when releasing [80,100), hash values of 80 and 100 may be calculated, respectively, resulting in corresponding hash values of 3 and 10.
It should be noted that there may be multiple ways of determining the identifier to which the memory address is mapped, and hash calculation is only one way, and other ways that different memory addresses may be mapped to different identifiers may also be used in this embodiment.
In addition, based on the selected mapping manner and the characterization manner of the memory address, there is a possibility that the identifiers (e.g., hash values) mapped by different memory addresses are duplicated. At this time, other identifiers may be used to identify different memory addresses, which is not limited in this embodiment.
It should be further noted that different memory addresses may also be mapped to the same identifier, and thus, a memory address of one or more memory blocks may be stored in one position in the array. The memory addresses stored in the same position can be distinguished through a storage rule, a storage mode or other modes, and the control mode of the memory addresses in the array is compatible with other embodiments.
Step S206, a target position corresponding to the target hash value in the target array is searched, wherein the memory address of the released memory block in the target memory is stored in the position corresponding to the hash value of the memory address of the released memory block in the target array.
Optionally, in this embodiment, freelist may be modified from a linked list to an array, and the memory address of the released memory block in the target memory is stored by the array. The memory address of the released memory block in the target memory is stored in the target array at a location corresponding to the hash value of the memory address of the released memory block. Each location in the array has its location identifier, e.g., subscript, from which the corresponding location identifier can be determined from the hash value, and the location identifier determines the location sought. For example, the memory address of the released memory block is stored in the target array at a location that is indexed by the hash value of its memory address.
It should be noted that, in addition to the manner of storing the memory address by using the hash value as the subscript, the storage location of the memory address may also be determined by using other manners, for example, a value obtained by adding a fixed value to the hash value of the memory address is used as the subscript to determine the storage location of the memory address, or the storage location of the memory address is determined by using other manners of mapping the hash value and the subscript, which is not limited in this embodiment.
Since the memory address includes a start address and an end address, the memory address of one memory block stores two locations of the array, which are: one location corresponding to the hash value of its start address and another location corresponding to the hash value of its end address.
For example, the array created to hold the free memory block may be as shown in Table 1.
TABLE 1
Subscript
Memory block
Before releasing [80,100), the memory addresses of the released memory blocks stored in the target array are: [70,80),[100,150),[450,460).
The memory addresses of three blocks of memory are stored in the array [70,80), [100,150) and [450,460) in sequence. For [70,80 ], 70 corresponds to a hash value of 0, stored in the array at the location with index 0,80 corresponds to a hash value of 3, stored in the array at the location with index 3. For [100,150 ], 100 corresponds to a hash value of 10 and is stored in the array at the location indexed by 10, 150 corresponds to a hash value of 15 and is stored in the array at the location indexed by 15. Similarly, the hash values for 450 and 460 are 6 and 12, so [450,460) is stored in the two locations in the array with indices of 6 and 12, resulting in the array shown in Table 2.
TABLE 2
Subscript 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Memory block [70,80) [70,80) [450,460) [100,150) [450,460) [100,150)
After obtaining the target hash value, the server may search for a target location indexed by the hash value, and determine whether a memory address storing another memory block is used at the target location. The target hash value comprises a first hash value and a second hash value, and correspondingly, the target position comprises a first position taking the first hash value as a subscript and a second position taking the second hash value as the subscript.
For example, when releasing [80,100), a location in the array with index 3 and a location with index 10 may be found.
Step S208, merging the first memory block and the second memory block into a third memory block when the memory address of the second memory block is found in the target location.
If the memory address of the second memory block is found at the target position, according to the storage mode of the memory block, it can be determined that the hash value of the memory address of the second memory block is the same as the hash value of the memory address of the first memory block. Since one memory address is mapped to one hash value, the server may determine that the second memory block is a memory block adjacent to the first memory block, and may further determine that the first memory block and the second memory block may be merged into one large memory block. The merged memory block can be subjected to memory multiplexing when a memory application is made later.
The server may merge the first memory chunk and the second memory chunk into a third memory chunk. For merged chunks of memory, the server may handle them in a number of ways, such as removing them, again, for example, marking them as unusable, or spent, and so forth. This is not limited in this embodiment.
Optionally, if a location of the target array allows storage of memory addresses of the plurality of memory blocks, whether the first memory block is adjacent to the second memory block may be further determined according to the memory addresses. The server may search the memory address of the second memory block at the target location, and merge the first memory block and the second memory block into a third memory block when determining that the first memory block is adjacent to the second memory block according to the memory address.
For example, the currently released memory block is [80,100), if the memory addresses of the memory blocks are stored by using a linked list, [80,100) cannot be combined with [70,80) and [100,150) two memories to form a large memory block due to the release order. The memory address is stored in an array mode, and the server can search a target array according to the hash value of the memory address [80,100 ]; if two memory addresses [70,80) and [100,150) are found adjacent to [80,100), the three may be combined into one memory block [70,150).
Alternatively, if the memory address of any memory block is not found in the target location, the server may determine that there is no released memory block adjacent to the first memory block, and the server may write the memory address of the first memory block to the target location of the target array, that is, the first location and the second location.
In this embodiment, the array lookup uses a hash value of the memory address, lookup is performed according to the hash value (for example, the hash value is used as a subscript of the array), and performance lookup with complexity O (1) can be implemented through hash calculation. If the merging process is sequential search, the search complexity is O (N), so that the fast search of the array can be realized through Hash calculation.
Through the steps S202 to S208, a first memory address of a released first memory block is obtained, where the first memory block is a memory block to be stored with a memory address in a target memory; performing hash calculation on the first memory address to obtain a target hash value corresponding to the first memory address; searching a target position corresponding to the target hash value in the target array, wherein the memory address of the released memory block in the target memory is stored in the position corresponding to the hash value of the memory address of the released memory block in the target array; under the condition that the memory address of the second memory block is found in the target position, the first memory block and the second memory block are combined into the third memory block, so that the problems of low memory reuse rate and memory resource waste in a memory allocation mode in the related technology are solved, the memory resource waste is reduced, and the memory reuse rate is improved.
Optionally, in this embodiment, the target hash value includes a first hash value of a start address of the first memory address and a second hash value of an end address of the first memory address, and the target location includes a first location corresponding to the first hash value and a second location corresponding to the second hash value. Because the releasing process of the memory block has certain randomness, the position relationship between the memory block just released and the released memory block can be various: are not adjacent, are adjacent to one memory block, and are adjacent to two memory blocks. Different processing modes can be adopted for different position relations.
As an optional implementation manner, merging the first memory block and the second memory block into a third memory block includes:
s11, when the memory address of the second memory block is found in the first location, determine the start address of the second memory block as the start address of the third memory block, and determine the end address of the first memory block as the end address of the third memory block.
If the memory address of the second memory block is found only at the first position of the target array, the server may determine that the first memory block is adjacent to the second memory block, and the first memory block is a memory block located behind the second memory block. The server may determine the start address of the second memory block as a start address of the third memory block, and determine the end address of the first memory block as an end address of the third memory block.
In addition, the server may also delete the memory address of the second memory block stored in the first location, update the memory address stored in the target array at the location corresponding to the hash value of the start address of the second memory block to the memory address of the third memory block, and write the memory address of the third memory block into the target array at the location corresponding to the hash value of the end address of the third memory block.
As another optional implementation, the merging the first memory block and the second memory block into a third memory block includes:
s12, when the memory address of the second memory block is found in the second location, determine the start address of the first memory block as the start address of the third memory block, and determine the end address of the second memory block as the end address of the third memory block.
If the memory address of the second memory block is found only at the second position of the target array, the server may determine that the first memory block is adjacent to the second memory block, and the first memory block is a memory block located before the second memory block. The server may determine the start address of the first memory block as a start address of the third memory block, and determine the end address of the second memory block as an end address of the third memory block.
In addition, the server may further delete the memory address of the second memory block stored in the second location, update the memory address stored in the target array at the location corresponding to the hash value of the ending address of the second memory block to the memory address of the third memory block, and write the memory address of the third memory block into the target array at the location corresponding to the hash value of the starting address of the third memory block.
As another optional implementation, the merging the first memory block and the second memory block into a third memory block includes:
s13, when the memory address of the first sub-memory block is found in the first location and the memory address of the second sub-memory block is found in the second location, determining a start address of the first sub-memory block as a start address of a third memory block and determining an end address of the second sub-memory block as an end address of the third memory block, where the second memory block includes the first sub-memory block and the second sub-memory block.
If the memory addresses, that is, the memory address of the first sub memory block and the memory address of the second sub memory block, are found in the first position and the second position of the target array, the server may determine that the first memory block is adjacent to both the first sub memory block and the second sub memory block, and the first memory block is a memory block located after the first sub memory block and before the second sub memory block. The server may determine the start address of the first sub-memory block as a start address of the third memory block, and determine the end address of the second sub-memory block as an end address of the third memory block.
In addition, the server may also delete the memory address of the first sub-memory block stored in the first location and the memory address of the second sub-memory block stored in the second location, and update the memory address stored in the target array in the location corresponding to the hash value of the start address of the first sub-memory block and the memory address stored in the location corresponding to the hash value of the end address of the second sub-memory block to the memory address of the third memory block.
For example, when release [80,100), the position of subscript 3 as shown in FIG. 2 is looked up by the hash value of 80. According to table 2, the adjacent memory blocks 70,80) can be found, 80,100) and 70,80) are merged to form a new, large memory block 70, 100, and the memory blocks 70,80 (addresses of the memory blocks) stored in the array are deleted, as shown in table 3.
TABLE 3
Subscript 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Memory block [450,460) [100,150) [450,460) [100,150)
The newly combined memory block is searched again, and the position of the subscript 10 is found through the hash value of 100. According to table 3, the adjacent memory blocks [100,150) can be found, the [70, 100) and the [100,150) are merged to form a new, large memory block [70,150), and the memory blocks [100,150) stored in the array are deleted, as shown in table 4.
TABLE 4
Subscript 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Memory block [450,460) [450,460)
Because the newly released memory block is generally connected to at most two released memory blocks, after the location corresponding to the hash value of the start address and the location corresponding to the hash value of the end address of the newly released memory block have been searched, a new memory block [70,150 ] may be inserted. A hash value of 70 is 0, [70,150) may be stored at a location with a subscript of 0, a hash value of 150 is 15, [70,150) may be stored at a location with a subscript of 15, as shown in table 5.
TABLE 5
Subscript 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Memory block [70,150) [450,460) [450,460) [70,150）
According to the embodiment, the memory address is written in the array by adopting different processing modes according to the position relation between the newly released memory block and the released memory block, so that the accuracy of writing the memory address can be improved, and the memory occupation of the array is saved.
As an optional embodiment, after the merging the first memory block and the second memory block into the third memory block, the method further includes:
s21, writing the memory address of the third memory block into a third location and a fourth location in the target array, where the third location is a location in the target array corresponding to the hash value of the start address of the third memory block, and the fourth location is a location in the target array corresponding to the hash value of the end address of the third memory block.
After determining the merged memory address of the third memory block, the server may write the memory address of the third memory block into two locations in the target array, where the two locations are: a position (i.e., a third position) corresponding to the hash value of the start address of the third memory block and a position (i.e., a fourth position) corresponding to the hash value of the end address of the third memory block facilitate determining an adjacent memory block when the memory block is subsequently released.
Through the embodiment, the merged memory address is written into two positions in the array, so that the memory address can be conveniently searched, and the accuracy of searching the memory block is ensured.
As an optional embodiment, after the merging the first memory block and the second memory block into the third memory block, the method further includes:
s31, remove the memory addresses of the second memory block stored at a fifth position and a sixth position in the target array, where the fifth position is a position in the target array corresponding to the hash value of the start address of the second memory block, and the sixth position is a position in the target array corresponding to the hash value of the end address of the second memory block.
The memory address of the second memory block is stored in the following two locations of the target array: a location corresponding to the hash value of the start address of the second memory chunk (i.e., a fifth location), and a location corresponding to the hash value of the end address of the second memory chunk (i.e., a sixth location).
After the second memory block is found, no matter what the adjacent manner is, the server may first remove the memory address of the second memory block from the target array, that is, remove the memory addresses of the second memory block stored in the fifth position and the sixth position of the target array.
After removing the memory address of the second memory block, the server may determine a write-in position of the memory address of the third memory block, and write the memory address of the third memory block into the target array.
By the embodiment, the memory addresses of the combinable memory blocks are removed first, and then the memory addresses of the combinable memory blocks are written, so that the accuracy of writing the memory addresses can be ensured, and data reading and writing errors can be avoided.
As an alternative embodiment, the method further includes:
s41, obtaining a memory application instruction of a target transaction, wherein the memory application instruction is used for applying for a memory block with a target size;
s42, responding to the memory application instruction, and searching a target array according to the target size;
s43, when the fourth memory block with the memory block size greater than or equal to the target size is found, allocating a fifth memory block to the target transaction, where the fifth memory block is a portion of the fourth memory block with the memory size equal to the target size.
If there is a new memory application instruction (the memory application is acquired by the processor or other component of the server), the memory application instruction may be an instruction related to a target transaction, and is used to apply for a memory block of a target size (i.e., size, capacity size), and the server may search a target array according to the target size in response to the memory application instruction, and determine whether there is a memory block satisfying the memory application in the freelist.
If the size of the found memory block is larger than or equal to the target size of the fourth memory block, the server may allocate a fifth memory block for the target transaction, where the fifth memory block is a portion of the fourth memory block in which the size of the memory is the target size. If the size of the fourth memory block is the target size, the fourth memory block may be allocated directly for the target transaction. If the size of the fourth memory block is greater than the target size, a portion of the target size in the fourth memory block may be allocated for the target transaction.
If the memory block with the size larger than or equal to the target size is not found, the memory can be applied from the memory, and the application process may refer to the related art and is not described herein.
Through the embodiment, when a memory application exists, whether the memory block meeting the memory application exists in the freelist is determined by searching the array, and the memory block in the freelist can be guaranteed to be preferentially used, so that the reuse rate of the memory is improved, the number of memory fragments is reduced, and the memory waste is avoided.
As an alternative embodiment, searching the target array according to the target size includes:
s51, sequentially searching each memory address stored in the target array, and determining whether a memory block with the size of the target memory block exists;
s52, when the memory block with the size equal to the target size is not found, sequentially finding each memory address stored in the target array, and determining whether there is a memory block with a size larger than the target size.
It should be noted that the memory address of the memory block stored in the target array may be calculated according to the memory address, for example, the memory address is FF8E0000-FF8EFFFF, where FF8E0000 is the start address, and FF8EFFFF is the end address, and the memory size is: FF8EFFFF-FF8E0000= FFFF, equal to 65535, i.e. 64K.
It should be further noted that the memory size of the memory block may also be pre-calculated and stored in the array, for example, a memory address and a memory size may be stored in one position in the target array, for example, a memory address is stored in a position where the subscript of the target array is an even number, and a memory size is stored in a position where the subscript adjacent to the even number is an odd number, for example, another data storage memory size may be used, and a memory size of the same memory block is stored in a same subscript position as the target array, and the like, and a determination manner of the memory block size may be configured as needed, which is not limited in this embodiment.
When the target array is searched, the memory blocks with the target size can be searched first, and then the memory blocks with the size larger than the target size are searched, so that reasonable utilization of the memory fragments is ensured.
The server may sequentially search each memory address stored in the target array, and determine whether a memory block having a memory block size equal to the target size exists. If a memory block (fourth memory block) with the memory block size of the target size is found, the memory block can be directly allocated to the target transaction.
If the memory block with the size equal to the target size is not found, the server may sequentially find each memory address stored in the target array, and determine whether a memory block with a size larger than the target size exists. If the memory block with the size larger than the target size is found, the server may select a portion of the memory block with the target size and allocate the portion to the target transaction.
The selection manner of the fifth memory block may be: calculating the end address of the memory block with the target size by taking the start address of the target memory block as the start address, and determining the part from the start address of the target memory block to the calculated end address as a fifth memory block; the end address of the target memory block may be used as the end address, the start address of the memory block with the target size is calculated, and a part from the calculated start address to the end address of the target memory block is determined as the fifth memory block.
By the embodiment, the memory blocks with the target size are searched preferentially, and then the memory blocks with the size larger than the target size are searched, so that the number of memory fragments can be reduced, and the occupation of the array on the storage resources is reduced.
As an optional embodiment, after allocating the fifth memory block for the target transaction, the method further includes:
s61, removing the memory address of the fourth memory block from the target array;
s62, when the size of the fourth memory block is larger than the target size, writing the memory address of the sixth memory block into a position corresponding to the hash value of the memory address of the sixth memory block in the target array, where the sixth memory block is a memory block other than the fifth memory block in the fourth memory block.
After allocating the memory block of the target size in the fourth memory block for the target transaction, the server may remove the memory address of the fourth memory block from the target array. If the size of the fourth memory block is larger than the target size, the allocated memory block (fifth memory block) is part of the fourth memory block, and for the remaining memory blocks (sixth memory block), the server may store the memory address of the server to a position in the target array corresponding to the hash value of the memory address of the server.
By the embodiment, the accuracy of memory address storage can be ensured by removing the searched memory address of the memory block and adding the memory addresses of the remaining memory blocks.
The following explains a processing method of a memory in the embodiment of the present application with reference to an optional example. In this example, startaddr (start address) and endaddr (end address) of the released memory blocks are stored according to the Hash value, and when the freed memory blocks are not sorted in the freelist, the free memory blocks are merged, so that multiplexing of large memory applications is realized, the memory is saved, and the memory fragments are reduced.
In this example, startaddr and endaddr (memory addresses) of a memory block are stored in an array by hash calculation: startaddr is calculated through hash and used as subscript of the array, and the stored content is startaddr and endaddr; endaddr is calculated by hash and used as a subscript of the array, and the stored contents are startaddr and endaddr.
When there is free memory, the startaddr and endaddr can be searched in the array after hash value is obtained through hash calculation, if the hash value is not found, it is indicated that no adjacent memory exists, and the startaddr and endaddr are directly inserted into the array.
Optionally, as shown in fig. 3, the flow of the memory processing method in this optional example may include the following steps:
step S302, an array is searched through the hash value of startaddr, if endaddr of a certain memory block is found, the memory block is an adjacent memory, and two memories are combined to form a new memory.
Step S304, continue to search through the endaddr of the new memory block, and if found, merge the memory blocks.
Step S306, search again, if the new memory block can not be found, delete the original memory block mark, and insert the newly merged memory block into the array.
If the above determination process is performed when the memory addresses of the memory blocks are stored, the number of the memory blocks adjacent to a newly released memory block is at most two, and then step S306 may be an optional step.
By the memory block searching method and the memory block merging device, the memory blocks can be quickly searched and merged, and the number of fragments of the memory is reduced.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.
Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (e.g., a ROM (Read-Only Memory)/RAM (Random Access Memory), a magnetic disk, an optical disk) and includes several instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the methods according to the embodiments of the present application.
According to another aspect of the embodiments of the present application, there is also provided a memory processing apparatus for implementing the memory processing method. Fig. 4 is a block diagram of a processing apparatus of an optional memory according to an embodiment of the present application, and as shown in fig. 4, the apparatus may include:
a first obtaining unit 402, configured to obtain a first memory address of a released first memory block, where the first memory block is a memory block to be stored with a memory address in a target memory;
a calculating unit 404, connected to the first obtaining unit 402, configured to perform hash calculation on the first memory address to obtain a target hash value corresponding to the first memory address;
a first searching unit 406, connected to the calculating unit 404, configured to search a target position corresponding to the target hash value in the target array, where a memory address of a released memory block in the target memory is stored in a position corresponding to the hash value of the memory address of the released memory block in the target array;
the merging unit 408 is connected to the first searching unit 406, and configured to merge the first memory block and the second memory block into a third memory block when the memory address of the second memory block is found in the target location.
It should be noted that the first obtaining unit 402 in this embodiment may be configured to execute the step S202, the calculating unit 404 in this embodiment may be configured to execute the step S204, the first searching unit 406 in this embodiment may be configured to execute the step S206, and the combining unit 408 in this embodiment may be configured to execute the step S208.
Acquiring a first memory address of a released first memory block through the module, wherein the first memory block is a memory block to be stored with a memory address in a target memory; performing hash calculation on the first memory address to obtain a target hash value corresponding to the first memory address; searching a target position corresponding to the target hash value in the target array, wherein the memory address of the released memory block in the target memory is stored in the position corresponding to the hash value of the memory address of the released memory block in the target array; under the condition that the memory address of the second memory block is found in the target position, the first memory block and the second memory block are combined into the third memory block, so that the problems of low memory reuse rate and memory resource waste in a memory allocation mode in the related technology are solved, the memory resource waste is reduced, and the memory reuse rate is improved.
Optionally, the target hash value includes a first hash value of a start address of the first memory address and a second hash value of an end address of the first memory address, and the target location includes a first location corresponding to the first hash value and a second location corresponding to the second hash value.
As an alternative embodiment, the merging unit 408 includes:
a first determining module, configured to determine a start address of the second memory block as a start address of a third memory block and determine an end address of the first memory block as an end address of the third memory block when the memory address of the second memory block is found in the first location;
a second determining module, configured to determine a start address of the first memory block as a start address of a third memory block and determine an end address of the second memory block as an end address of the third memory block when the memory address of the second memory block is found at the second location;
a third determining module, configured to determine a start address of the first sub-memory block as a start address of a third memory block and determine an end address of the second sub-memory block as an end address of the third memory block when the memory address of the first sub-memory block is found in the first location and the memory address of the second sub-memory block is found in the second location, where the second memory block includes the first sub-memory block and the second sub-memory block.
As an alternative embodiment, the apparatus further comprises:
the first writing unit is configured to write the memory address of the third memory block into a third position and a fourth position in the target array, where the third position is a position in the target array corresponding to the hash value of the start address of the third memory block, and the fourth position is a position in the target array corresponding to the hash value of the end address of the third memory block.
As an alternative embodiment, the apparatus further comprises:
the first removing unit is configured to remove the memory address of the second memory block stored at a fifth position and a sixth position in the target array, where the fifth position is a position in the target array corresponding to the hash value of the start address of the second memory block, and the sixth position is a position in the target array corresponding to the hash value of the end address of the second memory block.
As an alternative embodiment, the apparatus further comprises:
a second obtaining unit, configured to obtain a memory application instruction of a target transaction, where the memory application instruction is used to apply for a memory block of a target size;
the second searching unit is used for responding to the memory application instruction and searching the target array according to the target size;
and the allocating unit is configured to allocate a fifth memory block to the target transaction when the size of the found fourth memory block is greater than or equal to the target size, where the fifth memory block is a part of the fourth memory block and the size of the memory is the target size.
As an alternative embodiment, the second lookup unit includes:
the first searching module is used for sequentially searching each memory address stored in the target array and determining whether a memory block with the size of the target size exists;
and the second searching module is used for sequentially searching each memory address stored in the target array under the condition that the memory block with the size being the target size is not searched, and determining whether the memory block with the size being larger than the target size exists.
As an alternative embodiment, the apparatus further comprises:
a second removing unit, configured to remove the memory address of the fourth memory block from the target array after the fifth memory block is allocated for the target transaction;
and a second writing unit, configured to, when the size of the fourth memory block is larger than the target size, write the memory address of the sixth memory block into a position, in the target array, corresponding to the hash value of the memory address of the sixth memory block, where the sixth memory block is a memory block, in the fourth memory block, other than the fifth memory block.
It should be noted here that the modules described above are the same as the examples and application scenarios implemented by the corresponding steps, but are not limited to the disclosure of the above embodiments. It should be noted that the modules described above as a part of the apparatus may be operated in a hardware environment as shown in fig. 1, and may be implemented by software, or may be implemented by hardware, where the hardware environment includes a network environment.
According to another aspect of the embodiments of the present application, there is also provided an electronic device for implementing the processing method of the memory, where the electronic device may be a server, a terminal, or a combination thereof.
Fig. 5 is a block diagram of an alternative electronic device according to an embodiment of the present application, as shown in fig. 5, including a processor 502, a communication interface 504, a memory 506, and a communication bus 508, where the processor 502, the communication interface 504, and the memory 506 are communicated with each other via the communication bus 508, and where,
a memory 506 for storing a computer program;
the processor 502, when executing the computer program stored in the memory 506, implements the following steps:
s1, acquiring a first memory address of a released first memory block, where the first memory block is a memory block to be stored with a memory address in a target memory;
s2, performing hash calculation on the first memory address to obtain a target hash value corresponding to the first memory address;
s3, searching a target position corresponding to the target hash value in the target array, wherein the memory address of the released memory block in the target memory is stored in the position corresponding to the hash value of the memory address of the released memory block in the target array;
s4, merging the first memory block and the second memory block into a third memory block when the memory address of the second memory block is found in the target location.
Alternatively, in this embodiment, the communication bus may be a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 5, but this is not intended to represent only one bus or type of bus.
The communication interface is used for communication between the electronic equipment and other equipment.
The memory may include RAM, and may also include non-volatile memory (non-volatile memory), such as at least one disk memory. Alternatively, the memory may be at least one memory device located remotely from the processor.
As an example, the storage 506 may include, but is not limited to, the first obtaining unit 402, the calculating unit 404, the first searching unit 406, and the merging unit 408 in the processing device including the memory. In addition, the processing apparatus may further include, but is not limited to, other module units in the processing apparatus of the memory, which is not described in this example again.
The processor may be a general-purpose processor, and may include but is not limited to: a CPU (Central Processing Unit), an NP (Network Processor), and the like; but also a DSP (Digital Signal Processing), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component.
Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments, and this embodiment is not described herein again.
It can be understood by those skilled in the art that the structure shown in fig. 5 is only an illustration, and the device implementing the memory processing method may be a terminal device, and the terminal device may be a terminal device such as a smart phone (e.g., an Android phone, an iOS phone, etc.), a tablet computer, a palm computer, a Mobile Internet Device (MID), a PAD, and the like. Fig. 5 is a diagram illustrating a structure of the electronic device. For example, the electronic device may also include more or fewer components (e.g., network interfaces, display devices, etc.) than shown in FIG. 5, or have a different configuration than shown in FIG. 5.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by a program instructing hardware associated with the terminal device, where the program may be stored in a computer-readable storage medium, and the storage medium may include: flash disk, ROM, RAM, magnetic or optical disk, and the like.
According to still another aspect of an embodiment of the present application, there is also provided a storage medium. Optionally, in this embodiment, the storage medium may be configured to execute a program code of a processing method of any one of the memories in this embodiment of the application.
Optionally, in this embodiment, the storage medium may be located on at least one of a plurality of network devices in a network shown in the above embodiment.
Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps:
s1, acquiring a first memory address of a released first memory block, where the first memory block is a memory block to be stored with a memory address in a target memory;
s2, performing hash calculation on the first memory address to obtain a target hash value corresponding to the first memory address;
s3, searching a target position corresponding to the target hash value in the target array, wherein the memory address of the released memory block in the target memory is stored in the position corresponding to the hash value of the memory address of the released memory block in the target array;
s4, merging the first memory block and the second memory block into a third memory block when the memory address of the second memory block is found in the target location.
Optionally, the specific example in this embodiment may refer to the example described in the above embodiment, which is not described again in this embodiment.
Optionally, in this embodiment, the storage medium may include, but is not limited to: various media capable of storing program codes, such as a U disk, a ROM, a RAM, a removable hard disk, a magnetic disk, or an optical disk.
According to yet another aspect of an embodiment of the present application, there is also provided a computer program product or a computer program comprising computer instructions stored in a computer readable storage medium; the processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to perform the method steps of any of the embodiments described above.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
The integrated unit in the above embodiments, if implemented in the form of a software functional unit and sold or used as a separate product, may be stored in the above computer-readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a storage medium, and including instructions for causing one or more computer devices (which may be personal computers, servers, network devices, or the like) to execute all or part of the steps of the method described in the embodiments of the present application.
In the above embodiments of the present application, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the several embodiments provided in the present application, it should be understood that the disclosed client may be implemented in other manners. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, and may also be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution provided in the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The foregoing is only a preferred embodiment of the present application and it should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.

Claims (10)

1. A method for processing a memory, comprising:
acquiring a first memory address of a released first memory block, wherein the first memory block is a memory block of a memory address to be stored in a target memory;
performing hash calculation on the first memory address to obtain a target hash value of the first memory address;
searching a target position in a target array by taking the target hash value as a subscript, wherein the memory address of the released memory block in the target memory is stored in the position in the target array by taking the hash value of the memory address of the released memory block as the subscript;
and merging the first memory block and the second memory block into a third memory block under the condition that the memory address of the second memory block adjacent to the first memory block is found in the target position.
2. The method according to claim 1, wherein the target hash value includes a first hash value of a start address of the first memory chunk and a second hash value of an end address of the first memory chunk, and the target location includes a first location that is indexed by the first hash value and a second location that is indexed by the second hash value;
merging the first memory block and the second memory block into the third memory block includes:
determining a start address of the second memory block as a start address of the third memory block and determining an end address of the first memory block as an end address of the third memory block under the condition that the memory address of the second memory block is found at the first position;
determining the starting address of the first memory block as the starting address of the third memory block and determining the ending address of the second memory block as the ending address of the third memory block under the condition that the memory address of the second memory block is found at the second position;
determining a start address of the first sub-memory block as a start address of the third memory block and determining an end address of the second sub-memory block as an end address of the third memory block under the condition that the memory address of the first sub-memory block is found at the first position and the memory address of the second sub-memory block is found at the second position, wherein the second memory block includes the first sub-memory block and the second sub-memory block.
3. The method according to claim 1, wherein after merging the first and second memory chunks into the third memory chunk, the method further includes:
and writing the memory address of the third memory block into a third position and a fourth position in the target array, wherein the third position is a position in the target array with the hash value of the start address of the third memory block as a subscript, and the fourth position is a position in the target array with the hash value of the end address of the third memory block as a subscript.
4. The method according to claim 1, wherein after merging the first and second memory chunks into the third memory chunk, the method further includes:
and removing the memory addresses of the second memory block stored at a fifth position and a sixth position in the target array, wherein the fifth position is a position in the target array with the hash value of the start address of the second memory block as a subscript, and the sixth position is a position in the target array with the hash value of the end address of the second memory block as a subscript.
5. The method according to any one of claims 1 to 4, further comprising:
obtaining a memory application instruction of a target transaction, wherein the memory application is used for applying for a memory block with a target size;
responding to the memory application instruction, and searching the target array according to the target size;
and under the condition that a fourth memory block with the memory block size larger than or equal to the target size is found, allocating a fifth memory block to the target transaction, wherein the fifth memory block is a part of the fourth memory block and the memory size is the target size.
6. The method of claim 5, wherein searching the target array by the target size comprises:
sequentially searching each memory address stored in the target array, and determining whether a memory block with the size of the target memory block exists;
and under the condition that the memory block with the size of the target size is not found, sequentially finding each memory address stored in the target array, and determining whether the memory block with the size larger than the target size exists.
7. The method according to claim 5, wherein after allocating the fifth memory block for the target transaction, the method further comprises:
removing the memory address of the fourth memory block from the target array;
and under the condition that the size of the fourth memory block is larger than the target size, writing the memory address of a sixth memory block into a position in the target array, where the hash value of the memory address of the sixth memory block is used as a subscript, where the sixth memory block is a memory block in the fourth memory block except for the fifth memory block.
8. A memory processing apparatus, comprising:
a first obtaining unit, configured to obtain a first memory address of a released first memory block, where the first memory block is a memory block to be stored with a memory address in a target memory;
the computing unit is used for carrying out Hash computation on the first memory address to obtain a target Hash value taking the first memory address as a subscript;
a first searching unit, configured to search a target position in a target array with the target hash value as a subscript, where a memory address of a released memory block in the target memory is stored in the target data at the position with the hash value of the memory address of the released memory block as the subscript;
a merging unit, configured to merge the first memory block and the second memory block into a third memory block when the memory address of the second memory block adjacent to the first memory block is found in the target location.
9. An electronic device comprising a processor, a communication interface, a memory and a communication bus, wherein said processor, said communication interface and said memory communicate with each other via said communication bus,
the memory for storing a computer program;
the processor for performing the method steps of any one of claims 1 to 7 by running the computer program stored on the memory.
10. A computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to carry out the method steps of any one of claims 1 to 7 when executed.
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