CN115863452A - Solar cell, preparation method thereof and photovoltaic module - Google Patents
Solar cell, preparation method thereof and photovoltaic module Download PDFInfo
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Abstract
The invention discloses a solar cell, a preparation method thereof and a photovoltaic module, wherein the solar cell comprises a silicon substrate; the silicon substrate is laminated with a first oxide layer, a semiconductor layer, a second oxide layer, a polysilicon layer and a first passivation layer, the first oxide layer and the second oxide layer are provided with through holes, and the density of the through holes in the first oxide layer is greater than that of the through holes in the second oxide layer; the first electrode penetrates through the first passivation layer and is electrically connected with the polycrystalline silicon layer, or the first electrode penetrates through the first passivation layer, the polycrystalline silicon layer and the second oxide layer in sequence and is electrically connected with the semiconductor layer; the silicon substrate comprises a base region and an emitter; a second passivation layer is arranged on one side of the emitter electrode, which is far away from the base region; the second electrode penetrates through the second passivation layer and is electrically connected with the emitter. The first oxide layer and the second oxide layer are used for forming resonance tunneling, on the basis, the first oxide layer forms high-density through holes, the high-density through holes are used for improving the electron transmission efficiency and reducing the series resistance, and the second oxide layer forms a complete passivation layer to ensure the passivation quality.
Description
Technical Field
The invention relates to the technical field of photovoltaics, in particular to a solar cell, a preparation method of the solar cell and a photovoltaic module.
Background
The TOPCon battery (Tunnel Oxide Passivated Contact) is prepared by adopting a tubular LPCVD (Low Pressure Chemical Vapor Deposition) device, the Tunnel Oxide layer and the doped polysilicon layer form a Passivated Contact structure together, and the Tunnel Oxide Passivated Contact structure can enable majority carriers to pass through the Oxide layer to block minority carriers, so that the selective permeability of the carriers is effectively realized, the recombination rate of the minority carriers is greatly reduced, and the efficiency of the battery is improved.
The existing TOPCon battery structure design has the following two problems: 1. from a technical point of view, when a cell absorbs light energy, generates photogenerated carriers, which are separated at a p-n junction, positive charges are collected by a front electrode, negative charges are collected by a back electrode, and when negative charges flow from the p-n junction to the back electrode, there are obstacles among which, more prominently, a tunneling oxide layer SiO is present therein X Electrons passing through the tunneling oxide layer SiO X According with the Schrodinger uncertainty principle, randomness and contingency exist, and the randomness and the contingency of the passing of electrons along with the SiO of the tunneling oxide layer X The thickness is increased and reduced, and macroscopic data is reflected by the size of the series resistance, so that the series resistance is reduced, and the method becomes an important mode for improving the TOPCon battery efficiency; 2. from the cost perspective, the TOPCon battery production generally deposits a polysilicon poly-si layer through lpcvd, the raw material silane is expensive, meanwhile, the thicker poly-si layer has stronger parasitic absorption influence, thinning the poly-si layer becomes the inevitable improvement of the cost reduction and efficiency improvement of the process, but when thinning the poly-si layer, the problem exists, on one hand, after thinning the poly-si layer, when performing subsequent phosphorus expansion, the conditions of poor temperature, pressure, time and the like are controlled, phosphorus can penetrate through a tunneling oxide layer to enter a silicon substrate, phosphorus atoms are in an inactivated state, an intermediate level can be formed, the Schopper-leder-Hall recombination (SRH recombination) is generated, the minority carrier lifetime is reduced, and the battery efficiency is reduced; on the other hand, after poly-si is thinned, the temperature changes during the subsequent metal sinteringAnd the limitation of the material of the metal slurry enables the metal to be burnt through to the substrate layer to form an intermediate energy level, SRH recombination is generated, the minority carrier lifetime is shortened, and the battery efficiency is reduced.
Therefore, it is desirable to provide a solar cell, a method for manufacturing the same, and a photovoltaic module, which can not only improve the electron transmission efficiency and reduce the series resistance, but also improve the passivation quality and prevent phosphorus from entering the silicon substrate.
Disclosure of Invention
In view of the above, the present invention provides a solar cell including a silicon substrate, a first electrode and a second electrode;
a first oxide layer, a semiconductor layer, a second oxide layer, a polysilicon layer and a first passivation layer are sequentially arranged on one surface of the silicon substrate in a stacking manner along the direction far away from the silicon substrate, the first oxide layer and the second oxide layer are provided with through holes, and the density of the through holes in the first oxide layer is greater than that of the through holes in the second oxide layer;
the first electrode penetrates through the first passivation layer and is electrically connected with the polycrystalline silicon layer, or the first electrode penetrates through the first passivation layer, the polycrystalline silicon layer and the second oxide layer in sequence and is electrically connected with the semiconductor layer;
the silicon substrate comprises a base region and an emitter, and the emitter is located on one side, far away from the first oxidation layer, of the base region; a second passivation layer is arranged on one side of the emitter, which is far away from the base region;
the second electrode penetrates through the second passivation layer and is electrically connected with the emitter.
Optionally, the first oxide layer has a first region and a second region, the first region at least partially overlaps the first electrode in a direction perpendicular to the silicon substrate, the second region does not overlap the second electrode, and the density of the through holes in the first region is greater than the density of the through holes in the second region.
Optionally, the density range of the through holes in the first oxide layer is 10 8 ～10 12 cm -2 。
Optionally, the diameter of the through hole in the first oxide layer ranges from 1nm to 100nm.
Optionally, the semiconductor layer is polysilicon, silicon carbide or a silicon germanium alloy.
Optionally, the thickness of the semiconductor layer along a direction perpendicular to the silicon substrate is in a range of 1 to 3nm.
Optionally, the thickness of the polysilicon layer is 30-200nm in a direction perpendicular to the silicon substrate.
Optionally, the thickness of the first oxide layer and the second oxide layer along a direction perpendicular to the silicon substrate is in a range of 0.5 to 2nm.
The invention also provides a preparation method of the solar cell, which comprises the following steps:
1) Cleaning the silicon substrate for texturing;
2) B diffusion;
3) Removing the BSG on the back;
4) Carrying out alkali polishing on the back surface;
5) Preparing and depositing a first oxide layer on the back surface, and then annealing the first oxide layer;
6) Preparing a semiconductor layer, a second oxidation layer and a polycrystalline silicon layer on the back surface, wherein the semiconductor layer, the second oxidation layer and the polycrystalline silicon layer are sequentially deposited on one side of the first oxidation layer, which is far away from the silicon substrate;
7) Removing the front polysilicon layer for coil plating;
8) Back doping;
9) Annealing to crystallize the polysilicon layer and activate the impurity;
10 Front and back surfaces are coated with film;
11 To generate electrodes.
The invention also provides a photovoltaic module which comprises glass, a first packaging adhesive film, a battery string, a second packaging adhesive film and a back plate which are arranged in a laminated mode, wherein the battery string is formed by electrically connecting a plurality of solar batteries.
Compared with the prior art, the solar cell, the preparation method thereof and the photovoltaic module provided by the invention at least realize the following beneficial effects:
according to the solar cell, the first oxide layer, the semiconductor layer, the second oxide layer, the polycrystalline silicon layer and the first passivation layer are sequentially arranged on one surface of the silicon substrate in a stacking mode along the direction far away from the silicon substrate, the first oxide layer and the second oxide layer are provided with the through holes, the density of the through holes in the first oxide layer is larger than that of the through holes in the second oxide layer, resonant tunneling is formed by the first oxide layer and the second oxide layer, high-density through holes are formed by the first oxide layer on the basis of the resonant tunneling, electron transmission efficiency is improved by the high-density through holes, series resistance is reduced, cell filling factors and cell efficiency are improved, diffusion defect density can be reduced, passivation quality is improved, the second oxide layer forms the complete passivation layer, passivation quality is guaranteed, meanwhile, the two oxide layers form a wall-like structure during phosphorus diffusion, phosphorus can be prevented from entering the silicon substrate, and metal sintering and burning-through can be prevented.
Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic diagram of a solar cell according to the present invention;
FIG. 2 is a schematic structural diagram of a first oxide layer provided in the present invention;
FIG. 3 is a schematic diagram of a second oxide layer according to the present invention;
FIG. 4 is a schematic view of another embodiment of a solar cell according to the present invention;
FIG. 5 is a schematic diagram of a first region of a first oxide layer according to the present invention;
FIG. 6 is a schematic diagram of a second region of the first oxide layer according to the present invention;
FIG. 7 is a schematic flow chart of a method for fabricating a solar cell according to the present invention;
fig. 8 is a schematic structural diagram of a photovoltaic module provided by the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be discussed further in subsequent figures.
FIG. 1 is a schematic diagram of a solar cell according to the present invention; FIG. 2 is a schematic structural diagram of a first oxide layer provided in the present invention; FIG. 3 is a schematic structural diagram of a second oxide layer provided in the present invention; FIG. 4 is a schematic view of another structure of a solar cell provided by the present invention; referring to fig. 1 to 4, the present embodiment provides a solar cell including: a silicon substrate 1, a first electrode 2 and a second electrode 3;
one surface of the silicon substrate 1 is sequentially provided with a first oxidation layer 10, a semiconductor layer 11, a second oxidation layer 12, a polycrystalline silicon layer 13 and a first passivation layer 14 in a laminated manner along a direction far away from the silicon substrate 1, the first oxidation layer 10 and the second oxidation layer 12 are respectively provided with through holes 110, and the density of the through holes 110 in the first oxidation layer 10 is greater than that of the through holes 110 in the second oxidation layer 12;
the first electrode 2 penetrates through the first passivation layer 14 and is electrically connected with the polysilicon layer 13, or the first electrode 2 penetrates through the first passivation layer 14, the polysilicon layer 13 and the second oxide layer 12 in sequence and is electrically connected with the semiconductor layer 11;
the silicon substrate 1 comprises a base region 15 and an emitter 16, wherein the emitter 16 is positioned on one side of the base region 15, which is far away from the first oxide layer 10; a second passivation layer 17 is arranged on one side of the emitter 16, which is far away from the base region 15;
the second electrode 3 is electrically connected to the emitter electrode 16 through the second passivation layer 17.
Specifically, the solar cell may be a TOPCon cell including a silicon substrate 1, the silicon substrate 1 may be an N-type silicon substrate, a first electrode 2 and a second electrode 3;
a first oxidation layer 10, a semiconductor layer 11, a second oxidation layer 12, a polysilicon layer 13 and a first passivation layer 14 are sequentially stacked on one surface of the silicon substrate 1 along a direction away from the silicon substrate 1, the first oxidation layer 10 and the second oxidation layer 12 are both provided with through holes 110, the density of the through holes 110 in the first oxidation layer 10 is greater than that of the through holes 110 in the second oxidation layer 12, wherein the first oxidation layer 10 and the second oxidation layer 12 can be tunneling oxidation layers, and the semiconductor layer 11 is polysilicon, silicon carbide or a silicon germanium alloy; in order to reduce the series resistance, it is an effective method to introduce a resonant tunnel double-barrier two-dimensional quantum well type passivation contact, in this embodiment, a resonant tunneling is formed by the first oxide layer 10 and the second oxide layer 12, the resonant tunneling is a process in which electrons pass through a quasi-bound energy level in a double-barrier quantum well without loss, and the conditions for implementing the resonant tunneling are mainly three: (1) The thicknesses of the two quantum well layers are the same so as to ensure the matching of quantum energy level positions; (2) The fermi level of the quantum well layer cannot be pinned with the fermi level of an adjacent electrode; (3) The voltage dropped on the middle barrier layer must be very small to ensure that the quantum well state energy level positions in the two layers of quantum wells are aligned, on the basis of resonant tunneling, the first oxidation layer 10 is optimized to form a high-density through hole 110, the through hole 110 can be a pinhole with a small aperture, the diffusion defect density can be reduced and the passivation quality can be improved while the electron transmission efficiency is improved by utilizing the high-density through hole 110, through the quantum wells, the structure is similar to a sandwich structure, the first oxidation layer 10 forms the high-density through hole 110 through rapid heating and cooling, electrons can better pass through the first oxidation layer 10, the second oxidation layer 12 is complete and can provide better passivation, and meanwhile, smooth transmission of the electrons can be ensured; that is, pinhole tunneling is formed by using the high-density through holes 110 on the first oxide layer 10, which is beneficial to the transport of a small amount of carriers, so that the forward current and the reverse saturation current are increased, and when a certain amount of carriers pass through the through holes 110 of the first oxide layer 10, the J-V characteristic curve of the current density and the voltage will show linear or ohmic behavior; when the second oxide layer 12 is introduced, the second oxide layer 12 is utilized to play a role in blocking, so that the density of diffusion defects can be reduced to a certain extent, and the passivation quality is improved;
in summary, in the two tunnel oxide layers, the first oxide layer 10 forms the high-density through holes 110, the electron transmission efficiency is improved by using the high-density through holes 110, and the second oxide layer 12 forms the complete passivation layer, thereby ensuring the passivation quality.
Due to the fact that the first oxidation layer 10 is provided with the through holes 110 with high density, pinhole tunneling is formed, when the pinhole tunneling is combined with resonance tunneling, an additional chemical reaction can be achieved, for example, the semiconductor layer 11 is used as polycrystalline silicon, the concentration of P of the silicon substrate 1 is five orders of magnitude different from that of the polycrystalline silicon doped with P, through the resonance tunneling, namely the through holes 110 are introduced into the first oxidation layer 10, the concentration of P at the junction of the first oxidation layer 10 and the silicon substrate 1 is correspondingly increased, the Fermi level potential difference at the junction is correspondingly increased, the resonance tunneling condition (2) is better met, and the Fermi level of the quantum well layer cannot be pinned with the Fermi level of an adjacent electrode under the resonance tunneling condition (2).
As shown in fig. 1, the first electrode 2 may penetrate through the first passivation layer 14 to be electrically connected to the polysilicon layer 13, and the first electrode 2 forms a good ohmic contact with the polysilicon layer 13, which is favorable for the transmission of carriers; alternatively, the first and second electrodes may be,
as shown in fig. 4, the first electrode 2 may also sequentially penetrate through the first passivation layer 14, the polysilicon layer 13 and the second oxide layer 12 to be electrically connected to the semiconductor layer 11, and the first electrode 2 and the semiconductor layer 11 form a good ohmic contact, which is favorable for the transmission of carriers;
placing the silicon substrate 1 in a tube-type LPCVD, depositing a second passivation layer 17 on the front surface of the silicon substrate 1, wherein the second electrode 3 penetrates through the second passivation layer 17 and is electrically connected with the emitter 16, and in the direction of the emitter 16 away from the base region 15, the second passivation layer 17 may include an aluminum oxide layer 171 and a silicon nitride layer 172 which are sequentially stacked, that is, placing the silicon substrate 1 in a tube-type LPCVD, sequentially depositing the aluminum oxide layer 171 and the silicon nitride layer 172 on the front surface of the silicon substrate 1, and sequentially penetrating through the silicon nitride layer 172 and the aluminum oxide layer 171 and electrically connecting with the emitter 16, the second electrode 3.
As can be seen from the foregoing embodiments, the solar cell provided in this embodiment at least achieves the following beneficial effects:
in the solar cell provided in this embodiment, a first oxide layer 10, a semiconductor layer 11, a second oxide layer 12, a polysilicon layer 13, and a first passivation layer 14 are sequentially stacked on one surface of a silicon substrate 1 along a direction away from the silicon substrate 1, the first oxide layer 10 and the second oxide layer 12 both have through holes 110, the density of the through holes 110 in the first oxide layer 10 is greater than that of the through holes 110 in the second oxide layer 12, the first oxide layer 10 and the second oxide layer 12 are used to form resonant tunneling, on the basis of the resonant tunneling, the first oxide layer 10 forms high-density through holes 110, the high-density through holes 110 are used to improve electron transmission efficiency, thereby reducing series resistance, improving cell filling factor and cell efficiency, reducing diffusion defect density, improving passivation quality, and the second oxide layer 12 forms a complete passivation layer, thereby ensuring passivation quality, and at the same time, the two oxide layers form a wall-like structure during phosphorus diffusion, which can prevent phosphorus from entering the silicon substrate 1, and can also prevent metal sintering from burning through.
In some alternative embodiments, fig. 5 is a schematic structural view of a first region in a first oxide layer provided in the present invention; FIG. 6 is a schematic diagram of a second region of the first oxide layer according to the present invention; referring to fig. 5 to 6, in the present embodiment, the first oxide layer 10 has a first region 120 and a second region 130, in a direction perpendicular to the silicon substrate 1, the first region 120 at least partially overlaps the first electrode 2, the second region 130 does not overlap the second electrode 3, and the density of the through holes 110 in the first region 120 is greater than the density of the through holes 110 in the second region 130.
Specifically, the first oxide layer 10 is subdivided into a first region 120 and a second region 130, in a direction perpendicular to the silicon substrate 1, the first region 120 may partially overlap with the first electrode 2, the first region 120 may also overlap with the first electrode 2, and the second region 130 overlaps with the second electrode 3, the density of the through holes 110 in the first region 120 is greater than that of the through holes 110 in the second region 130, and since the first region 120 and the first electrode 2 at least partially overlap, the carrier transmission is facilitated, the electron transmission efficiency is further improved, and thus the solar cell efficiency is improved.
In some alternative embodiments, and with continued reference to FIG. 2, the first oxide layer 10 has a via 110 density in the range of 10 8 cm -2 ～10 12 cm -2 。
Specifically, the through holes 110 in the first oxide layer 10 may be pinholes with high density and small aperture if the density of the through holes 110 in the first oxide layer 10 is less than 10 8 cm -2 The electron transmission efficiency is reduced, which is not favorable for reducing the series resistance, if the density of the through holes 110 in the first oxide layer 10 is higher than 10 12 cm -2 The density of defects may be decreased to deteriorate passivation quality, and thus, the density of the through holes 110 in the first oxide layer 10 is designed to be 10 8 ～10 12 cm -2 Not only can the electron transmission efficiency be improved, thereby being beneficial to reducing the series resistance, but also the diffusion defect density can be reduced, thereby improving the passivation quality, and particularly, the density of the through holes 110 in the first oxidation layer 10 can be 10 8 cm -2 、10 9 cm -2 、10 10 cm -2 、10 11 cm -2 Or 10 12 cm -2 。
In some alternative embodiments, and with continued reference to FIG. 2, the diameter of the via 110 in the first oxide layer 10 may range from 1nm to 100nm.
Specifically, if the diameter of the through hole 110 in the first oxide layer 10 is smaller than 1nm, or if the diameter of the through hole 110 in the first oxide layer 10 is greater than 100nm, the concentration of P at the junction between the first oxide layer 10 and the silicon substrate 1 is correspondingly reduced, and the fermi level potential difference at the junction is correspondingly reduced, which is not favorable for meeting the resonant tunneling condition (2), so that the diameter range of the through hole 110 in the first oxide layer 10 is designed to be 1nm-100nm, which not only can correspondingly improve the concentration of P at the junction between the first oxide layer 10 and the silicon substrate 1, but also can correspondingly improve the fermi level potential difference at the junction, thereby better meeting the resonant tunneling condition (2), and specifically, the diameter of the through hole 110 in the first oxide layer 10 may be 1nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm.
In some alternative embodiments, as shown with continued reference to fig. 1 and 4, the thickness of the semiconductor layer 11 ranges from 1nm to 3nm in a direction perpendicular to the silicon substrate 1.
Specifically, along the direction perpendicular to the silicon substrate 1, if the thickness of the semiconductor layer 11 is less than 1nm, or if the thickness of the semiconductor layer 11 is greater than 3nm, the resonant tunneling condition (3) cannot be satisfied, and the resonant tunneling condition (3) is that the voltage dropped on the intermediate barrier layer must be small to ensure that the quantum well state energy level positions in the two quantum wells are aligned, so that the thickness range of the semiconductor layer 11 along the direction perpendicular to the silicon substrate 1 is designed to be 1nm to 3nm, which may satisfy the resonant tunneling condition (3), specifically, the thickness of the semiconductor layer 11 along the direction perpendicular to the silicon substrate 1 may be 1nm, 2nm, or 3nm.
In some alternative embodiments, as shown with continued reference to fig. 1 and 4, the polysilicon layer 13 has a thickness in the range of 30-200nm in a direction perpendicular to the silicon substrate 1.
Specifically, the total thickness of the polysilicon layer 13 can be reduced by using a semiconductor layer 11 and a polysilicon layer 13, wherein the semiconductor layer 11 is located between the first oxide layer 10 and the second oxide layer 12, and if the thickness of the polysilicon layer 13 is less than 30nm along a direction perpendicular to the silicon substrate 1, on one hand, phosphorus can penetrate through the tunneling oxide layer to enter the silicon substrate, and phosphorus atoms are in an inactivated state, and can form an intermediate level to generate SRH recombination and reduce minority carrier lifetime, thereby reducing the battery efficiency, and on the other hand, when subsequent metal sintering is performed, the metal can be burnt through to the substrate layer due to the limitation of temperature change and the material of metal slurry to form an intermediate level to generate SRH recombination, reduce the minority carrier lifetime, and reduce the battery efficiency; if the thickness of the polysilicon layer 13 is greater than 200nm along the direction perpendicular to the silicon substrate 1, the process time is prolonged while the cost is increased, and therefore, the thickness range of the polysilicon layer 13 is designed to be 30-200nm along the direction perpendicular to the silicon substrate 1, which not only can prevent phosphorus from penetrating through a tunneling oxide layer to enter a silicon substrate, but also can prevent metal from burning through to a substrate layer due to the limitation of metal slurry materials due to temperature change when subsequent metal sintering is performed, thereby preventing SRH recombination from occurring, increasing minority carrier lifetime, improving battery efficiency, reducing cost and shortening process time, and particularly, along the direction perpendicular to the silicon substrate 1, the thickness of the polysilicon layer 13 can be 30nm, 50nm, 100nm, 150nm or 200nm.
In some alternative embodiments, as shown with continued reference to fig. 1 and 4, the first oxide layer 10 and the second oxide layer 12 have a thickness in a range of 0.5nm to 2nm in a direction perpendicular to the silicon substrate 1.
Specifically, along the direction perpendicular to the silicon substrate 1, the thickness of the first oxide layer 10 is the same as that of the second oxide layer 12, so that the first oxide layer and the second oxide layer better satisfy the resonant tunneling condition (1), wherein the resonant tunneling condition (1) is that the thicknesses of two quantum well layers are the same so as to ensure the quantum energy level position matching;
if the thickness of the first oxide layer 10 is less than 0.5nm or the thickness of the first oxide layer 10 is greater than 2nm along the direction perpendicular to the silicon substrate 1, it is not favorable for forming high-density pinholes on the first oxide layer 10, thereby affecting the reduction of the series resistance; therefore, the thickness range of the first oxide layer 10 is designed to be 0.5 nm-2 nm along the direction perpendicular to the silicon substrate 1, which is beneficial to forming high-density pinholes on the first oxide layer 10, reducing the series resistance and improving the photocurrent.
If the thickness of the second oxide layer 12 is less than 0.5nm or the thickness of the second oxide layer 12 is greater than 2nm along the direction perpendicular to the silicon substrate 1, the second oxide layer 12 is not favorable to playing a blocking role, and the cost is increased while the passivation quality is reduced; therefore, the thickness of the second oxide layer 12 is designed to be 0.5 nm-2 nm along the direction perpendicular to the silicon substrate 1, which is beneficial for the second oxide layer 12 to play a role in blocking, and reduces the passivation quality and cost.
FIG. 7 is a schematic flow chart of a method for fabricating a solar cell according to the present invention; referring to fig. 7, the present embodiment provides a method for manufacturing a solar cell, including the following steps:
1) Cleaning the silicon substrate for texturing;
2) B diffusion;
3) Removing the BSG on the back;
4) Carrying out alkali polishing on the back surface;
5) Preparing and depositing a first oxide layer on the back surface, and annealing the first oxide layer;
6) Preparing a semiconductor layer, a second oxidation layer and a polycrystalline silicon layer on the side, far away from the silicon substrate, of the first oxidation layer in sequence on the back surface;
7) Removing the front polysilicon layer for coil plating;
8) Back doping;
9) Annealing to crystallize the polysilicon layer and activate the impurity;
10 Front and back surfaces are coated with film;
11 To generate electrodes.
Specifically, this embodiment further provides a method for manufacturing a solar cell, where the method for manufacturing a solar cell may be a TOPCon cell, and the method may have a resistivity range of 0.8 to 1.5ohm>2.5ms of n-type monocrystalline silicon wafer; in KOH and H 2 O 2 Removing a damaged layer on the surface of the silicon wafer from the mixed solution, and then performing texturing in a KOH solution to form a pyramid textured surface on the surface of the silicon wafer, wherein the size of the pyramid textured surface is controlled to be 1-5 mu m; after the texture surface is finished, preparing an emitter on the front side of the silicon wafer by adopting B diffusion, wherein the sheet resistance is 110-150ohm.cm, the BSG thickness of the front side is 50-120 nm, and the BSG on the back side of the silicon wafer is removed and then alkali polishing is carried out, so that the reflectivity of the back side of the silicon wafer is more than 40%; after alkali polishing, preparing and depositing a first oxidation layer on the back surface by LPCVD, then carrying out oxidation annealing on the first oxidation layer, forming high-density small-aperture through holes on the first oxidation layer, wherein the oxidation annealing time range is 30-120 minThe temperature range of the oxidation annealing is 600-1100 ℃; depositing a semiconductor layer, a second oxide layer and a polysilicon layer on one side of the first oxide layer, which is far away from the silicon substrate, in sequence by the aid of LPCVD preparation on the back surface, and removing the front polysilicon layer by means of alkali washing after deposition of the polysilicon layer is finished (BSG is used as a barrier layer); then flatly placing the front side of the silicon wafer on a support plate, roll-coating a liquid doping agent containing P on the back side of the silicon wafer, and drying for 10-120 s at 100-200 ℃; then annealing in a tube furnace to crystallize the polysilicon and drive in and activate the impurity (P), wherein the annealing process conditions are as follows: high temperature of 700-900 deg.c for 3-20 min, normal pressure and nitrogen atmosphere; then depositing an aluminum oxide layer on the front side of the silicon wafer by using ALD (atomic layer deposition), and preparing a silicon nitride layer by using PECVD (plasma enhanced chemical vapor deposition); depositing a first passivation layer on the back of the silicon wafer to finish the preparation of a cell precursor; and after the surface passivation is finished, metallization is carried out on the front side and the back side of the silicon wafer, a first electrode is printed on the back side of the silicon wafer in a screen printing mode, a second electrode is printed on the front side of the silicon wafer in sequence, and then the silicon wafer is sintered to finish the preparation of the cell.
According to the embodiment, the preparation method of the solar cell provided by the invention at least has the following beneficial effects:
in the preparation method of the solar cell provided by the embodiment, after alkali polishing, a first oxide layer is prepared and deposited on the back surface, then the first oxide layer is annealed to form a through hole with high density and small aperture, and a semiconductor layer, a second oxide layer and a polycrystalline silicon layer are sequentially deposited on one side, far away from a silicon substrate, of the first oxide layer on the back surface; utilize the through-hole in the little aperture of high density to be favorable to improving electron transmission efficiency, thereby reduce the string and hinder, when improving battery fill factor and battery efficiency, can also reduce diffusion defect density, improve the passivation quality, form complete passivation layer by the second oxide layer, thereby guarantee the passivation quality, two-layer oxide layer forms the structure of similar wall when phosphorus expands simultaneously, can hinder phosphorus and enter into the silicon substrate, also can prevent the appearance that the metal sintering burns through.
Fig. 8 is a schematic structural diagram of a photovoltaic module provided by the present invention, and referring to fig. 8, the present embodiment provides a photovoltaic module, which includes a glass 201, a first encapsulant film 202, a cell string 203, a second encapsulant film 204, and a back sheet 205, which are stacked, wherein the cell string 203 is formed by electrically connecting a plurality of solar cells (not shown in the figure) of the above-mentioned type.
Specifically, the photovoltaic module comprises glass 201, a first packaging adhesive film 202, a battery string 203, a second packaging adhesive film 204 and a back plate 205 which are arranged in a laminated manner, wherein the glass 201 can be made of toughened glass, has high light transmittance which can reach more than 92%, and is generally made of low-iron toughened patterned glass; the back plate 205 can be made of glass, a TPT (polyvinyl fluoride) composite film or a TPE (thermoplastic elastomer), the back plate 205 is used for protecting an internal packaging material and a battery from mechanical damage and external environment erosion, and has good insulating property, the working life of the assembly is determined to a great extent, and the back plate has excellent weather resistance, low water vapor permeability, good electrical insulation property and certain bonding strength; the first adhesive packaging film 202 and the second adhesive packaging film 204 may be made of EVA (ethylene-vinyl acetate copolymer), POE (random copolymer elastomer of ethylene and high-carbon α -olefin), or PVB (polyvinyl butyral); the EVA material has low crystallinity, high toughness, high impact resistance, high filler intermiscibility and high heat sealing performance owing to the introduction of vinyl acetate monomer into the molecular chain. The molecular structure of the POE material ensures that the POE material has excellent mechanical property, rheological property and ultraviolet resistance, and also has the characteristics of good affinity with polyolefin, good low-temperature toughness, high cost performance and the like. The PVB material can be dissolved in methanol, ethanol, ketones, alkyl halides and aromatic solvents, has good intermiscibility with phthalate, sebacate benzene plasticizers, cellulose nitrate, phenolic resin, epoxy resin and the like, has higher transparency, cold resistance, impact resistance and ultraviolet radiation resistance, and has good bonding force with metal, glass, wood, ceramics, fiber products and the like. The first packaging adhesive film 202 and the second packaging adhesive film 204 are used for packaging and protecting the cell, so that the influence of the external environment on the performance of the cell is prevented, the glass 201, the solar cell and the back plate 205 are bonded together, and the solar cell has certain bonding strength, high light transmittance, reasonable crosslinking degree, excellent ultraviolet aging resistance, excellent humidity and heat aging resistance and extremely low shrinkage rate, has long-term strong bonding performance on various back plates 205 and glass 201, and has high volume resistivity; the cell string 203 is formed by electrically connecting a plurality of solar cells (not shown) of the above-mentioned type, and two adjacent solar cells are electrically connected by solder ribbons.
According to the embodiment, the solar cell, the preparation method thereof and the photovoltaic module provided by the invention at least realize the following beneficial effects:
according to the solar cell, the preparation method thereof and the photovoltaic module, the first oxide layer, the semiconductor layer, the second oxide layer, the polycrystalline silicon layer and the first passivation layer are sequentially arranged on one surface of the silicon substrate in a stacking mode along the direction far away from the silicon substrate, the first oxide layer and the second oxide layer are respectively provided with the through holes, the density of the through holes in the first oxide layer is larger than that of the through holes in the second oxide layer, resonance tunneling is formed by utilizing the first oxide layer and the second oxide layer, high-density through holes are formed by the first oxide layer on the basis of the resonance tunneling, the electron transmission efficiency is improved by utilizing the high-density through holes, the series resistance is reduced, the cell filling factor and the cell efficiency are improved, the diffusion defect density is reduced, the passivation quality is improved, the complete passivation layer is formed by the second oxide layer, the passivation quality is guaranteed, meanwhile, a wall-like structure is formed by the two oxide layers during phosphorus diffusion, phosphorus can be prevented from entering the silicon substrate, and the occurrence of metal sintering and burning through can also be prevented.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (10)
1. A solar cell, comprising: a silicon substrate, a first electrode and a second electrode;
the silicon substrate is characterized in that a first oxidation layer, a semiconductor layer, a second oxidation layer, a polycrystalline silicon layer and a first passivation layer are sequentially arranged on one surface of the silicon substrate in a stacking mode along the direction far away from the silicon substrate, the first oxidation layer and the second oxidation layer are provided with through holes, and the density of the through holes in the first oxidation layer is larger than that of the through holes in the second oxidation layer;
the first electrode penetrates through the first passivation layer and is electrically connected with the polycrystalline silicon layer, or the first electrode sequentially penetrates through the first passivation layer, the polycrystalline silicon layer and the second oxidation layer and is electrically connected with the semiconductor layer;
the silicon substrate comprises a base region and an emitter, and the emitter is located on one side, far away from the first oxidation layer, of the base region; a second passivation layer is arranged on one side of the emitter, which is far away from the base region;
the second electrode penetrates through the second passivation layer and is electrically connected with the emitter.
2. The solar cell of claim 1, wherein the first oxide layer has a first region and a second region, the first region at least partially overlapping the first electrode in a direction perpendicular to the silicon substrate, the second region not overlapping the second electrode, the via density in the first region being greater than the via density in the second region.
3. The solar cell of claim 1, wherein the first oxide layer has a via density in the range of 10 8 ～10 12 cm -2 。
4. The solar cell of claim 1, wherein the diameter of the through hole in the first oxide layer is in the range of 1-100nm.
5. The solar cell of claim 1, wherein the semiconductor layer is polycrystalline silicon, silicon carbide, or a silicon-germanium alloy.
6. The solar cell of claim 1, wherein the semiconductor layer has a thickness in a range of 1 to 3nm in a direction perpendicular to the silicon substrate.
7. The solar cell of claim 1, wherein the polysilicon layer has a thickness in a range of 30-200nm in a direction perpendicular to the silicon substrate.
8. The solar cell of claim 1, wherein the first oxide layer and the second oxide layer have a thickness in a range of 0.5 to 2nm in a direction perpendicular to the silicon substrate.
9. A preparation method of a solar cell is characterized by comprising the following steps:
1) Cleaning the silicon substrate for texturing;
2) B diffusion;
3) Removing the BSG on the back;
4) Carrying out alkali polishing on the back surface;
5) Preparing and depositing a first oxide layer on the back surface, and annealing the first oxide layer;
6) Preparing a semiconductor layer, a second oxidation layer and a polycrystalline silicon layer on the side, far away from the silicon substrate, of the first oxidation layer in sequence on the back surface;
7) Removing the front polysilicon layer for coil plating;
8) Back doping;
9) Annealing to crystallize the polysilicon layer and activate the impurity;
10 Front and back sides are coated with films;
11 To generate electrodes.
10. A photovoltaic module comprising a laminate of glass, a first encapsulant film, a string of cells, a second encapsulant film and a backsheet, the string of cells being formed by electrically connecting a plurality of solar cells of any one of claims 1-9.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117276361A (en) * | 2023-11-22 | 2023-12-22 | 天合光能股份有限公司 | Solar cell, manufacturing method thereof, photovoltaic module and photovoltaic system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117276361A (en) * | 2023-11-22 | 2023-12-22 | 天合光能股份有限公司 | Solar cell, manufacturing method thereof, photovoltaic module and photovoltaic system |
| CN117276361B (en) * | 2023-11-22 | 2024-02-02 | 天合光能股份有限公司 | Solar cell, manufacturing method thereof, photovoltaic module and photovoltaic system |
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