CN115863328A - 具有增大元件密度的同构管芯堆叠 - Google Patents
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Abstract
本公开提供了具有增大元件密度的同构管芯堆叠。一种集成电路器件,包括:多个微凸块;以及顶部可编程结构管芯,其包括第一可编程结构和耦合到多个微凸块的第一微凸块接口。该集成电路器件还包括底部可编程结构管芯,其具有第二可编程结构和经由与多个微凸块的耦合而耦合到第一微凸块接口的第二微凸块接口。顶部可编程结构管芯和底部可编程结构管芯具有相同的设计。此外,顶部可编程结构管芯和底部可编程结构管芯被布置在三维管芯布置中,使得顶部可编程结构管芯在底部可编程结构管芯上方被翻转。
Description
技术领域
本公开涉及同构管芯的管芯堆叠。具体地,同构管芯是使用相同的工艺制造的,并且具有相同的形状。
背景技术
该部分旨在向读者介绍可能与在下面描述和/或要求保护的本技术的各个方面有关的技术的各个方面。该论述被认为有助于为读者提供背景信息,以促进对本公开的各个方面的更好理解。因此,应注意,应该从这个角度解读这些陈述,而不是将这些陈述作为任何形式的承认。
集成电路存在于众多电子设备中,包括手持设备、计算机、游戏系统、机器人器件、汽车等。这些集成电路常常被放置在相互通信的硅管芯或芯片上。当多个集成电路被包括在同一封装中时,集成电路可能使用不同的工艺和/或形状因数。例如,集成电路之一(例如,底部集成电路)可以包含硅通孔(TSV),而另一个集成电路不包含TSV,导致集成电路具有不同的布局。每种不同的集成电路布局对应于不同的开发周期。因此,包含具有不同开发周期的不同集成电路可能会增加用于开发封装并将封装推向市场的时间和/或成本。
发明内容
本公开的一方面提供了一种集成电路器件。该集成电路器件包括:多个微凸块;顶部可编程结构(fabric)管芯,该顶部可编程结构管芯包括第一可编程结构和耦合到多个微凸块的第一微凸块接口;以及底部可编程结构管芯,该底部可编程结构管芯包括第二可编程结构和第二微凸块接口,该第二微凸块接口经由与多个微凸块的耦合而耦合到第一微凸块接口,其中顶部可编程结构管芯和底部可编程结构管芯具有相同的设计,并且顶部可编程结构管芯和底部可编程结构管芯被布置在三维管芯布置中,使得顶部可编程结构管芯在底部可编程结构管芯上方被翻转。
本公开的另一方面提供了一种集成电路器件。该集成电路器件包括:半导体器件;多个微凸块;顶部可编程结构管芯,该顶部可编程结构管芯包括第一可编程结构、第一硅通孔以及第一微凸块接口,该第一硅通孔耦合到半导体器件,该第一微凸块接口耦合到多个微凸块,其中,半导体器件耦合到顶部可编程结构管芯;以及底部可编程结构管芯,该底部可编程结构管芯包括第二可编程结构、第二硅通孔以及第二微凸块接口,该第二硅通孔未在底部可编程结构管芯的任何一侧上暴露,该第二微凸块接口经由与多个微凸块的耦合而与第一微凸块接口耦合。
本公开的另一方面提供了一种制造可编程逻辑器件的方法。该方法包括:使用工艺形成具有第一多个硅通孔的第一可编程逻辑管芯;使用工艺形成具有第二多个硅通孔的第二可编程逻辑管芯;以及通过翻转第一可编程逻辑管芯,使用微凸块将第一可编程逻辑管芯和第二可编程逻辑管芯一起安装在倒装芯片封装中。
附图说明
在阅读以下具体实施方式之后并在参考附图之后,可以更好地理解本公开的各个方面,在附图中:
图1是根据一实施例的用于对包括可编程结构的集成电路进行编程的过程的框图;
图2是根据一实施例的图1的可编程结构的图示;
图3是根据一实施例的包括异构集成电路的异构封装的图示,该异构集成电路包括图2的可编程结构;
图4是根据一实施例的包括同构集成电路的同构封装的图示,该同构集成电路包括图2的可编程结构;
图5是根据一替代实施例的包括同构集成电路的同构封装的示意图,该同构集成电路包括图2的可编程结构;
图6是根据一实施例的示出具有同构集成电路的同构封装的周边连通性的图示;以及
图7是根据一实施例的包括具有集成可编程结构单元的处理器的数据处理系统的框图。
具体实施方式
下面将描述一个或多个具体实施例。为了提供对这些实施例的简要描述,说明书中未描述实际实现方式的所有特征。应当理解,在任何此类实际实现方式的开发中,如在任何工程或设计项目中,必须做出许多特定于实现方式的决策,以实现开发者的特定目标,比如遵守可能因实现方式而异的与系统相关和与业务相关的约束。此外,应当理解,这样的开发工作可能是复杂且耗时的,但是对于受益于本公开的普通技术人员而言仍将是设计、制作和制造的例行工作。
当介绍本公开的各个实施例的元素时,冠词“一”、“一个”和“该”旨在表示存在一个或多个元素。术语“包括”和“具有”旨在是包括性的,并且表示除所列出的元素之外可能还存在其他元素。此外,应当理解的是,对本公开的“一些实施例”、“实施例”、“一个实施例”或“一实施例”的提及不旨在被解释为排除存在也包含所述特征的其他实施例。此外,短语A“基于”B旨在表示A至少部分地基于B。此外,术语“或”旨在是包括性的(例如,逻辑OR)而不是排他性的(例如,逻辑XOR)。换言之,短语A“或”B旨在表示A、B、或A和B两者。此外,本公开描述了各种数据结构(例如,用于指令集架构的指令)。这些被描述为具有某些域(例如,字段)和相应的位数。然而,应该理解的是,这些域和位大小仅作为示例,而不旨在是排他性的。实际上,本公开的数据结构(例如,指令)可以表现为任何合适的形式。
集成电路可以利用一个或多个可编程结构(例如,FPGA)。考虑到上述情况,图1图示了用于配置可编程器件的系统10的框图。设计者可以在集成电路(例如,包括一些可重新配置的电路(例如,FPGA)的集成电路12)上实现功能。设计者可以使用设计软件14(例如,AlteraTM的Quartus的一个版本)来实现将被编程到集成电路12上的电路设计。设计软件14可以使用编译器16来生成低级电路设计,该低级电路设计可以被提供为内核程序18,有时被称为程序目标文件或位元流,该内核程序18对集成电路12进行编程。也就是说,编译器16可以提供代表集成电路12的电路设计的机器可读指令。
集成电路12可以包括任何可编程逻辑器件,例如,现场可编程门阵列(FPGA)40,如图2所示。出于该示例的目的,FPGA 40被称为FPGA,但是应该理解该器件可以是任何合适类型的可编程逻辑器件(例如,专用集成电路和/或专用标准产品)。在一个示例中,FPGA 40是公开号为2016/0049941的美国专利文献“具有多个扇区的可编程电路”中所描述的类型的扇区化FPGA,该美国专利文献为所有目的而通过引用整体并入。FPGA 40可以形成在单个平面上。附加地或替代地,FPGA 40可以是第10,833,679号美国专利“用于配置数据和用户结构数据的多用途接口”中所描述的类型的具有底部管芯和结构管芯的三维FPGA,该美国专利为所有目的而通过引用整体并入。
在图2的示例中,FPGA 40可以包括收发器42,该收发器42可以包括和/或使用输入-输出电路来用于驱动信号离开FPGA 40并且用于接收来自其他器件的信号。互连资源44可以被用于通过FPGA 40来路由信号,例如,时钟或数据信号。图2的FPGA 40是扇区化的,这意味着可编程逻辑资源可以通过多个离散的可编程逻辑扇区46分布。每个可编程逻辑扇区46可以包括具有由配置存储器50(例如,配置随机存取存储器(CRAM))定义的操作的多个可编程逻辑元件48。可编程逻辑元件48可以包括组合或顺序逻辑电路。例如,可编程逻辑元件48可以包括查找表、寄存器、多路复用器、布线等。设计者可以对可编程逻辑元件48进行编程以执行各种期望的功能。电源52可以向配电网络(PDN)54提供电压和电流源,配电网络(PDN)54将电力分配给FPGA 40的各种组件。操作FPGA 40的电路导致从配电网络54汲取电力。
FPGA 40上可以有任何合适数量的可编程逻辑扇区46。实际上,虽然这里显示了29个可编程逻辑扇区46,但应该理解,在实际实现中可能会出现更多或更少(例如,在某些情况下,大约为50、100、500、1000、5000、10,000、50,000、或100,000个或更多)个扇区。每个可编程逻辑扇区46可以包括控制可编程逻辑扇区46的操作的扇区控制器(SC)56。每个扇区控制器56可以与器件控制器(DC)58通信。每个扇区控制器56可以接受来自器件控制器58的命令和数据,并且可以基于来自器件控制器58的控制信号,从其配置存储器50读取数据,并将数据写入其配置存储器50。除了这些操作之外,扇区控制器56还可被扩充有许多额外的能力。例如,这样的能力可以包括本地排序读取和写入,以在配置存储器50上实现错误检测和校正,以及对用于实现各种测试模式的测试控制信号进行排序。
扇区控制器56和器件控制器58可以被实现为状态机和/或处理器。例如,扇区控制器56或器件控制器58的每个操作可以被实现为包含控制程序的存储器中的单独例程。该控制程序存储器可以被固定在只读存储器(ROM)中、或被存储在可写存储器(例如,随机存取存储器(RAM))中。ROM的大小可能大于用于只存储每个例程的一个副本的大小。这可能允许每个例程具有多个变体(取决于本地控制器可能被放置到的“模式”)。当控制程序存储器被实现为随机存取存储器(RAM)时,可以用新例程写入RAM,以在可编程逻辑扇区46中实现新的操作和功能。这可以以有效且易于理解的方式提供可用的可扩展性。这可能是有用的,因为新命令可以仅以器件控制器58和扇区控制器56之间的少量通信为代价在扇区内带来大量本地活动。
每个扇区控制器56因此可以与器件控制器58通信,器件控制器58可以协调扇区控制器56的操作并传送从FPGA器件40外部发起的命令。为了支持这种通信,互连资源44可以充当器件控制器58和每个扇区控制器56之间的网络。互连资源可以支持器件控制器58和每个扇区控制器56之间的多种多样的信号。在一个示例中,这些信号可以作为通信分组被发送。
FPGA 40可以被电编程。对于电编程布置,可编程元件48可以包括一个或多个逻辑元件(线、门、寄存器等)。例如,在编程期间,使用引脚和输入/输出电路将配置数据加载到配置存储器50中。在一个示例中,配置存储器50可以被实现为配置随机存取存储器(CRAM)单元。如下所述,在一些实施例中,可以使用对嵌入了FPGA 40的处理器的微代码的更新来将配置数据加载到FPGA 40中。本文描述的基于RAM技术的配置存储器50的使用旨在仅作为一个示例。此外,配置存储器50可以分布(例如,作为RAM单元)遍及FPGA 40的各种可编程逻辑扇区46。配置存储器50可以提供相应的静态控制输出信号,该信号控制互连资源44的关联的可编程逻辑元件48或可编程组件的状态。配置存储器50的输出信号可以被施加到金属氧化物半导体(MOS)晶体管的栅极,该金属氧化物半导体(MOS)晶体管控制互连资源44的可编程逻辑元件48或可编程组件的状态。
扇区控制器56和/或器件控制器58可以确定每个扇区控制器56何时对其可编程逻辑扇区46的配置存储器50执行CRAM读取操作。每次扇区控制器56对配置存储器50执行CRAM读取时,从配电网络54汲取电力。如果在任一时间从配电网络54汲取过多电力,则配电网络54提供的电压可能下降到不可接受的低水平,或者配电网络54上可能出现过多噪声。为了避免这种情况,器件控制器58和/或扇区控制器56可以通过跨不同可编程逻辑扇区46在时间和/或空间上分布CRAM读取来构造可编程逻辑扇区46的CRAM读取,以避免过多的瞬时功耗。
可编程逻辑扇区46的扇区控制器56被示为通过以下方式来读取或写入配置存储器50:向地址寄存器提供地址(ADDRESS)信号,并向数据寄存器提供存储器写入信号(WRITE)、存储器读取信号(RD DATA)、和/或要写入的数据(WR DATA)。这些信号可以被用于使数据寄存器向配置存储器50的线写入数据或从配置存储器50的线读取数据,该配置存储器50已沿地址线(如被施加到地址寄存器的ADDRESS信号所规定的)被激活。存储器读/写电路可以被用于在数据寄存器正在写入数据时,将数据写入激活的配置存储器50的单元,并且可以被用于在数据寄存器正在读取数据时,从激活的配置存储器50的单元感知和读取数据。
集成电路12可以被组合成封装器件。例如,多个可编程结构管芯可以被组合成单个封装。例如,如图3所示,异构系统100可以集成顶部可编程结构管芯102和底部可编程结构管芯104。如图所示,顶部可编程结构管芯102和底部可编程结构管芯104有一些相似之处,但它们在形式上也有一些差异。底部可编程结构管芯102被布置在系统中的底部可编程结构管芯104的上方。顶部可编程结构管芯102包括可编程结构106。同样,底部可编程结构管芯104包括可编程结构108。顶部可编程结构管芯102包括微凸块接口110,而底部可编程结构管芯104包括微凸块接口112,微凸块接口112使用多个微凸块114与微凸块接口110相接。
如图所示,底部可编程结构管芯104(而非顶部可编程结构管芯102)耦合到多个焊球116,焊球116耦合到另一个器件(例如,基板或印刷电路板)。焊球116耦合到硅通孔(TSV)118,以提供该另一个器件与底部可编程结构管芯104和/或顶部可编程结构管芯102的各个层之间的连通性。底部可编程结构管芯104还包括管芯到管芯输入输出电路120(例如,收发器42),该管芯到管芯输入输出电路120可以被用于驱动信号离开FPGA 40并且接收来自其他器件的信号。
尽管异构系统100在紧凑封装中提供可编程结构106和108,但是即使可编程结构106和108的内容相同,顶部可编程结构管芯102和底部可编程结构管芯104也具有不同的设计。这些不同的设计导致比可用于单个管芯设计的成本更高的研发成本。附加地或替代地,这些不同的设计可能导致比单个管芯设计更高的制造成本。此外,由于底部可编程结构管芯104具有TSV 118而顶部可编程结构管芯102没有,可编程结构106和108可以具有不同的容量/密度/特性。如果可编程逻辑封装的顶部和底部管芯具有共同的设计,则整体封装可以提供具有更高效的研究、开发和制造成本的大容量可编程逻辑器件。
图4是具有相同设计、形状和节点工艺的顶部可编程结构管芯142(例如,倒装芯片)和底部可编程结构管芯144的同构系统140的图示。通过具有相同设计的顶部可编程结构管芯142和底部可编程结构管芯144,可以使用用于信令、TSV、和/或用于电源微凸块的对称性约束来确保顶部可编程结构管芯142和底部可编程结构管芯144之间的正确连通性。
返回图4,顶部可编程结构管芯142和底部可编程结构管芯144包括各自的可编程结构146和148。此外,顶部可编程结构管芯142包括微凸块接口150,而底部可编程结构管芯144包括微凸块接口152,该微凸块接口152使用微凸块154与微凸块接口150相接。如前所述,由于顶部可编程结构管芯142和底部可编程结构管芯144中的对称布置,电源微凸块可以被对齐。底部可编程结构管芯144直接耦合到焊球156,但顶部可编程结构管芯146不耦合到焊球。然而,即使顶部可编程结构管芯142不直接耦合到任何焊球,顶部可编程结构管芯142和底部可编程结构管芯144都包括TSV 158。事实上,顶部可编程结构管芯142的TSV 158可以被覆盖,因为它们在顶部可编程结构管芯的任何一侧未显露或暴露,但是顶部可编程结构管芯142和底部可编程结构管芯144仍然可以来自具有相同设计的相同管芯池。此外,顶部可编程结构管芯142中TSV 158的存在确保了可编程结构146和148中的相同的密度。此外,顶部可编程结构管芯142中TSV 158的存在连同它们的对称性有助于确保:在顶部可编程结构管芯142和底部可编程结构管芯144被布置在三维配置中时,顶部可编程结构管芯142和底部可编程结构管芯144之间对齐。此外,如图所示,顶部可编程结构管芯142和底部可编程结构管芯144包括管芯到管芯输入-输出电路160,以驱动数据离开相应的结构管芯和/或从相应的结构管芯接收数据。即使顶部可编程结构管芯142的管芯到管芯输入-输出电路160未被用于连接到其他管芯,这种布置也简化了顶部可编程结构管芯142和底部可编程结构管芯144的制造。
图5是具有顶部可编程结构管芯182和底部可编程结构管芯的同构系统180的图示。顶部可编程结构管芯182和底部可编程结构管芯184包括各自的可编程结构186和188。顶部可编程结构管芯182和底部可编程结构管芯184利用微凸块190在顶部可编程结构管芯182和底部可编程结构管芯184的相应区域/扇区之间相接。顶部可编程结构管芯182和底部可编程结构管芯184还包括可以被用于提供顶部可编程结构管芯182和底部可编程结构管芯184之间的连通性的周边三维接口192和194。
即使只有底部可编程结构管芯184耦合到焊球198,顶部可编程结构管芯182和底部可编程结构管芯184也包括TSV 196。顶部可编程结构管芯182包括管芯到管芯输入-输出电路200,而底部可编程结构管芯184包括管芯到管芯输入-输出电路202。管芯到管芯输入-输出电路202包括TSV 204,以提供从管芯到管芯输入-输出电路202内的凸块206(例如,微凸块)和/或到管芯到管芯输入-输出电路200的直通连接。此外,虽然所示的管芯到管芯输入-输出电路200不包括TSV,但在一些实施例中,管芯到管芯输入-输出电路202可以包括与TSV 204类似的TSV。然而,在某些实施例中,管芯到管芯输入-输出电路200中的TSV可以是未使用的和/或未暴露的/未显露的。
尽管周边三维接口194位于底部可编程结构管芯184右侧的右侧,并且周边三维接口192位于翻转的顶部可编程结构管芯182的右侧,但由于顶部可编程结构管芯182和底部可编程结构管芯184中的对称性,顶部可编程结构管芯182和底部可编程结构管芯184可以具有相同的设计。图6是图5的同构系统180的视图220的示意图,其中,顶部可编程结构管芯182被翻转,使得顶部可编程结构管芯182和底部可编程结构管芯184之间的接口被暴露。顶部可编程结构管芯182和底部可编程结构管芯184可以具有相同的设计。周边三维接口的位置可以归因于顶部可编程结构管芯182的旋转(例如,180度旋转)。
顶部可编程结构管芯182具有输入-输出电路222,而底部可编程结构管芯184具有输入-输出电路224。输入-输出电路222可以不经由凸块206连接到外部管芯。相反,由于顶部可编程结构管芯182的旋转和/或由于管芯到管芯输入-输出电路200没有直接耦合到相应的凸块,可以使用输入-输出电路224来执行(例如,恢复)输入-输出电路222的输入/输出。
考虑到上述内容,同构布置的处理器和两个或更多个可编程结构管芯可以被集成到数据处理系统中,或者可以是被包括在数据处理系统中的组件,例如图7中所示的数据处理系统300。数据处理系统300可以包括主机处理器304(例如,处理器130)、存储器和/或存储电路306、以及网络接口308。数据处理系统300可以包括更多或更少的组件(例如,电子显示器、用户接口结构、专用集成电路(ASIC))。主机处理器304可以包括可以管理数据处理系统300的数据处理请求(例如,执行加密、解密、机器学习、视频处理、语音识别、图像识别、数据压缩、数据库搜索排名、生物信息学、网络安全模式识别、空间导航、加密货币操作等)的任何前述处理器。存储器和/或存储电路306可以包括随机存取存储器(RAM)、只读存储器(ROM)、一个或多个硬盘驱动器、闪存等。存储器和/或存储电路306可以保存要由数据处理系统300处理的数据。在一些情况下,存储器和/或存储电路306还可以存储用于对同构可编程逻辑器件302进行编程的配置程序(位元流)。网络接口308可以允许数据处理系统300与其他电子器件通信。数据处理系统300可以包括几个不同的封装或者可以被包含在单个封装基板上的单个封装内。例如,数据处理系统300的组件可以位于一个位置(例如,数据中心)或多个位置处的几个不同封装上。例如,数据处理系统300的组件可以位于不同的地理位置或区域,例如,城市、州或国家。
在一个示例中,数据处理系统300可以是处理各种不同请求的数据中心的一部分。例如,数据处理系统300可以经由网络接口308接收数据处理请求,以执行加密、解密、机器学习、视频处理、语音识别、图像识别、数据压缩、数据库搜索排名、生物信息学、网络安全模式识别、空间导航、数字信号处理、或其他某个专门任务。
尽管本公开中阐述的实施例可易于进行各种修改和替代形式,但是在附图中已经通过示例的方式示出了并且在本文中已经详细描述了具体的实施例。然而,应当理解,本公开不旨在限于所公开的特定形式。本公开将覆盖落入如由所附权利要求限定的本公开的精神和范围内的所有修改、等同物和替代物。
本文提出并要求保护的技术被引用并应用于明确改善本技术领域的实践性质的实物和实例,因此不是抽象的、无形的或纯粹理论上的。另外,如果本说明书末尾所附的任何权利要求包含被指定为“用于[执行][功能]的装置……”或“用于[执行][功能]的步骤……”的一个或多个元素,则旨在将根据35U.S.C.112(f)来解释这样的元素。然而,对于包含以任何其他方式指定的元素的任何权利要求,旨在将不根据35U.S.C.112(f)来解释这样的元素。
示例实施例
示例实施例1.一种集成电路器件,包括:
多个微凸块;
顶部可编程结构管芯,该顶部可编程结构管芯包括第一可编程结构和耦合到多个微凸块的第一微凸块接口;以及
底部可编程结构管芯,该底部可编程结构管芯包括第二可编程结构和第二微凸块接口,该第二微凸块接口经由与多个微凸块的耦合而耦合到第一微凸块接口,其中顶部可编程结构管芯和底部可编程结构管芯具有相同的设计,并且顶部可编程结构管芯和底部可编程结构管芯被布置在三维管芯布置中,使得顶部可编程结构管芯在底部可编程结构管芯上方被翻转。
示例实施例2.根据示例实施例1的集成电路器件,其中,顶部可编程结构管芯和底部可编程结构管芯包括硅通孔。
示例实施例3.根据示例实施例2的集成电路器件,其中,顶部可编程结构管芯的硅通孔不暴露于顶部可编程结构管芯的任何表面。
示例实施例4.根据示例实施例1的集成电路器件,其中,顶部可编程结构管芯包括第一输入-输出电路,并且底部可编程结构管芯包括第二输入-输出电路。
示例实施例5.根据示例实施例4的集成电路器件,其中,第二输入-输出电路包括电连接到第一输入-输出电路的硅通孔。
示例实施例6.根据示例实施例4的集成电路器件,其中,第二输入-输出电路包括未暴露于第一输入-输出电路的硅通孔。
示例实施例7.根据示例实施例4的集成电路器件,其中,第二输入-输出电路可操作来连接到另一电子器件,并且第一输入-输出电路不可操作来连接到另一电子器件。
示例实施例8.根据示例实施例7的集成电路器件,其中,第一输入-输出电路的输入-输出通道经由第二输入-输出电路被恢复以被接收。
示例实施例9.根据示例实施例1的集成电路器件,其中,顶部可编程结构管芯包括位于顶部可编程结构管芯的周边的第一周边三维接口,并且底部可编程结构管芯包括在底部可编程结构管芯的周边处的第二周边三维接口,该第二周边三维接口可操作来与第一周边三维接口相接。
示例实施例10.根据示例实施例9的集成电路器件,其中,第一周边三维接口经由一个或多个微凸块耦合到第二周边三维接口。
示例实施例11.一种集成电路器件,包括:
半导体器件;
多个微凸块;
顶部可编程结构管芯,该顶部可编程结构管芯包括第一可编程结构、第一硅通孔以及第一微凸块接口,该第一硅通孔耦合到半导体器件,该第一微凸块接口耦合到多个微凸块,其中,半导体器件耦合到顶部可编程结构管芯;以及
底部可编程结构管芯,该底部可编程结构管芯包括第二可编程结构、第二硅通孔以及第二微凸块接口,该第二硅通孔未在底部可编程结构管芯的任何一侧上暴露,该第二微凸块接口经由与多个微凸块的耦合而与第一微凸块接口耦合。
示例实施例12.根据示例实施例11的集成电路器件,其中,第一硅通孔经由焊球耦合到半导体器件。
示例实施例13.根据示例实施例11的集成电路器件,其中,半导体器件包括印刷电路板或基板。
示例实施例14.根据示例实施例11的集成电路器件,其中,顶部可编程结构管芯和底部可编程结构管芯具有相同的设计。
示例实施例15.根据示例实施例11的集成电路器件,顶部可编程结构管芯和底部可编程结构管芯被布置在倒装芯片封装中。
示例实施例16.根据示例实施例11的集成电路器件,其中,底部可编程结构管芯包括耦合到一个或多个其他电子器件的输入-输出接口。
示例实施例17.根据示例实施例11的集成电路器件,其中,顶部可编程结构管芯包括不耦合到任何外部器件的输入-输出接口。
示例实施例18.一种制造可编程逻辑器件的方法,包括:
使用工艺形成具有第一多个硅通孔的第一可编程逻辑管芯;
使用工艺形成具有第二多个硅通孔的第二可编程逻辑管芯;以及
通过翻转第一可编程逻辑管芯,使用微凸块将第一可编程逻辑管芯和第二可编程逻辑管芯一起安装在倒装芯片封装中。
示例实施例19.根据示例实施例18的制造方法,包括暴露第二多个硅通孔而不暴露第一多个硅通孔。
示例实施例20.根据示例实施例19的制造方法,包括经由焊球将第二多个硅通孔耦合到基板或其他半导体器件。
Claims (20)
1.一种集成电路器件,包括:
多个微凸块;
顶部可编程结构管芯,该顶部可编程结构管芯包括第一可编程结构和耦合到所述多个微凸块的第一微凸块接口;以及
底部可编程结构管芯,该底部可编程结构管芯包括第二可编程结构和第二微凸块接口,该第二微凸块接口经由与所述多个微凸块的耦合而耦合到所述第一微凸块接口,其中所述顶部可编程结构管芯和所述底部可编程结构管芯具有相同的设计,并且所述顶部可编程结构管芯和所述底部可编程结构管芯被布置在三维管芯布置中,使得所述顶部可编程结构管芯在所述底部可编程结构管芯上方被翻转。
2.根据权利要求1所述的集成电路器件,其中,所述顶部可编程结构管芯和所述底部可编程结构管芯包括硅通孔。
3.根据权利要求2所述的集成电路器件,其中,所述顶部可编程结构管芯的所述硅通孔不暴露于所述顶部可编程结构管芯的任何表面。
4.根据权利要求1所述的集成电路器件,其中,所述顶部可编程结构管芯包括第一输入-输出电路,并且所述底部可编程结构管芯包括第二输入-输出电路。
5.根据权利要求4所述的集成电路器件,其中,所述第二输入-输出电路包括电连接到所述第一输入-输出电路的硅通孔。
6.根据权利要求4所述的集成电路器件,其中,所述第二输入-输出电路包括未暴露于所述第一输入-输出电路的硅通孔。
7.根据权利要求4所述的集成电路器件,其中,所述第二输入-输出电路可操作来连接到另一电子器件,并且所述第一输入-输出电路不可操作来连接到另一电子器件。
8.根据权利要求7所述的集成电路器件,其中,所述第一输入-输出电路的输入-输出通道经由所述第二输入-输出电路被恢复以被接收。
9.根据权利要求1所述的集成电路器件,其中,所述顶部可编程结构管芯包括位于所述顶部可编程结构管芯的周边的第一周边三维接口,并且所述底部可编程结构管芯包括在所述底部可编程结构管芯的周边处的第二周边三维接口,该第二周边三维接口可操作来与所述第一周边三维接口相接。
10.根据权利要求9所述的集成电路器件,其中,所述第一周边三维接口经由一个或多个微凸块耦合到所述第二周边三维接口。
11.一种集成电路器件,包括:
半导体器件;
多个微凸块;
顶部可编程结构管芯,该顶部可编程结构管芯包括第一可编程结构、第一硅通孔以及第一微凸块接口,该第一硅通孔耦合到所述半导体器件,该第一微凸块接口耦合到所述多个微凸块,其中,所述半导体器件耦合到所述顶部可编程结构管芯;以及
底部可编程结构管芯,该底部可编程结构管芯包括第二可编程结构、第二硅通孔以及第二微凸块接口,该第二硅通孔未在所述底部可编程结构管芯的任何一侧上暴露,该第二微凸块接口经由与所述多个微凸块的耦合而与所述第一微凸块接口耦合。
12.根据权利要求11所述的集成电路器件,其中,所述第一硅通孔经由焊球耦合到所述半导体器件。
13.根据权利要求11所述的集成电路器件,其中,所述半导体器件包括印刷电路板或基板。
14.根据权利要求11所述的集成电路器件,其中,所述顶部可编程结构管芯和所述底部可编程结构管芯具有相同的设计。
15.根据权利要求11所述的集成电路器件,所述顶部可编程结构管芯和所述底部可编程结构管芯被布置在倒装芯片封装中。
16.根据权利要求11所述的集成电路器件,其中,所述底部可编程结构管芯包括耦合到一个或多个其他电子器件的输入-输出接口。
17.根据权利要求11所述的集成电路器件,其中,所述顶部可编程结构管芯包括不耦合到任何外部器件的输入-输出接口。
18.一种制造可编程逻辑器件的方法,包括:
使用工艺形成具有第一多个硅通孔的第一可编程逻辑管芯;
使用所述工艺形成具有第二多个硅通孔的第二可编程逻辑管芯;以及
通过翻转所述第一可编程逻辑管芯,使用微凸块将所述第一可编程逻辑管芯和所述第二可编程逻辑管芯一起安装在倒装芯片封装中。
19.根据权利要求18所述的方法,包括暴露所述第二多个硅通孔而不暴露所述第一多个硅通孔。
20.根据权利要求19所述的方法,包括经由焊球将所述第二多个硅通孔耦合到基板或其他半导体器件。
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