CN115863258A - Manufacturing method for reducing on-resistance of MOSFET device - Google Patents
Manufacturing method for reducing on-resistance of MOSFET device Download PDFInfo
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- CN115863258A CN115863258A CN202310030128.1A CN202310030128A CN115863258A CN 115863258 A CN115863258 A CN 115863258A CN 202310030128 A CN202310030128 A CN 202310030128A CN 115863258 A CN115863258 A CN 115863258A
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- contact hole
- mosfet
- etching
- resistance
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 25
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 13
- 238000001312 dry etching Methods 0.000 claims abstract description 9
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910017604 nitric acid Inorganic materials 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 5
- 238000001465 metallisation Methods 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 239000011259 mixed solution Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 3
- 238000011010 flushing procedure Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims 1
- 239000007788 liquid Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
The application discloses a manufacturing method for reducing the on-resistance of an MOSFET device, which comprises the following steps: forming the basic appearance of a contact hole of the MOSFET; performing dry etching on the MOSFET contact hole by adopting radio frequency with first power; etching the residual silicon oxide in the contact hole of the MOSFET by adopting radio frequency with second power; mixed liquid of low-concentration nitric acid and hydrofluoric acid is adopted to treat the interface damage on the surface of the contact hole of the MOSFET, so that the density of the interface state is reduced; and removing the photoresist, and then performing metal deposition to form ohmic contact. The technical scheme of the application solves the problem that the existing MOSFET device fails due to the fact that the parameters of the on-resistance exceed the standards in the actual test process.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a manufacturing method for reducing the on-resistance of a MOSFET device.
Background
In the prior art, the on-resistance of the MOSFET device is composed of a plurality of series resistors, which are the main parameters for measuring the loss and performance of the MOSFET device, and mainly include fixed resistance, area resistance, contact resistance, and the like. The fixed resistance is determined by the resistivity and thickness of the raw material, the area resistance is mainly affected by the implantation dose, and the contact resistance can be reduced by adjusting the process.
Currently, in MOSFET devices, the contact resistance accounts for 5% to 40%. While the lower the voltage level of the MOSFET device, the higher its duty cycle. In the actual test process of the MOSFET device, the on-resistance parameter is often out of standard and fails.
Disclosure of Invention
The application provides a manufacturing method for reducing the on-resistance of an MOSFET device, and solves the problem that the existing MOSFET device fails due to the fact that the on-resistance parameter exceeds the standard in the actual test process.
The embodiment of the application provides a manufacturing method for reducing the on-resistance of a MOSFET device, which comprises the following steps:
s1: forming the basic appearance of a MOSFET contact hole;
s2: performing dry etching on the MOSFET contact hole by adopting radio frequency with first power;
s3: etching the residual silicon oxide in the contact hole of the MOSFET by adopting radio frequency with second power;
s4: the interface damage on the surface of the contact hole of the MOSFET is treated by adopting a mixed solution of low-concentration nitric acid and hydrofluoric acid, so that the interface state density is reduced;
s5: and removing the photoresist, and then carrying out metal deposition to form ohmic contact.
In some embodiments, step S1 specifically includes: thermally growing silicon oxide on the surface of a silicon wafer, depositing polycrystalline silicon, forming a preset pattern by adopting a photoetching and etching mode, depositing an ILD medium layer, flushing the ILD medium layer to remove impurities generated in the deposition process, exposing the position of a contact hole by adopting photoetching, and etching and exposing the contact hole.
In some embodiments, step S2 specifically includes: and performing dry etching on the contact hole by adopting the radio frequency with the power of 800W, and etching the ILD dielectric layer, the polysilicon and the silicon oxide.
In some embodiments, the step S3 specifically includes performing 30% over-etching on the silicon oxide remaining in the contact hole by using a radio frequency with a power of 200W, so as to completely remove the remaining oxide layer.
In some embodiments, step S4 specifically includes performing treatment on the interface damage on the surface of the contact hole for 10S to 20S by using a mixed solution of low-concentration nitric acid and hydrofluoric acid, so as to reduce the interface state density.
Compared with the prior art, the beneficial effects of this application are: according to the method, the radio frequency power of the equipment is reduced in the over-etching process, the over-etching time is shortened, the wet etching at a proper time is adopted to replace the dry over-etching, and the damage caused by the dry etching is reduced, so that the damage caused by the etching of the position of the contact hole is repaired, the contact resistance between metal and silicon is reduced, and the lower on-state resistance is realized.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic diagram corresponding to step S1 in the present application;
FIG. 2 is a schematic diagram corresponding to step S2 of the present application;
FIG. 3 is a schematic diagram corresponding to step S3 of the present application;
FIG. 4 is a schematic diagram corresponding to step S4 of the present application;
FIG. 5 is a schematic diagram corresponding to step S5 of the present application;
the implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
In the prior art, in the manufacturing process of chip contact hole etching, high-power radio frequency is generally used for dry etching, and in order to ensure that complete contact between metal and a device is realized, a time-increasing mode is generally adopted to completely remove a dielectric layer in a region. In the process of over-etching, a large amount of plasma continuously bombards the silicon surface to cause ion damage, so that the silicon surface is uneven, and finally, the contact resistance is increased.
The method improves the existing manufacturing process, also adopts the etching process, reduces the radio frequency power of equipment in the over-etching process, simultaneously reduces the over-etching time, adopts wet etching with proper time to replace dry over-etching, and reduces the damage caused by dry etching, thereby reducing the contact resistance between metal and silicon and realizing lower on-state resistance by repairing the damage caused by etching at the position of a contact hole.
Specifically, the manufacturing method for reducing the on-resistance of the MOSFET device proposed in this embodiment includes the following steps:
s1: referring to fig. 1, the basic topography of a MOSFET contact hole is formed; specifically, silicon oxide is thermally grown on the surface of a silicon wafer, then polycrystalline silicon is deposited, a preset pattern is formed in a photoetching and etching mode, finally an ILD dielectric layer is deposited, water flushing treatment is carried out on the ILD dielectric layer, impurities generated in the deposition process are removed, the PR photoresist can be adhered to an interface, the position of a contact hole is exposed by photoetching, and the contact hole is etched and exposed.
S2: referring to fig. 2, the MOSFET contact hole is dry etched using a radio frequency of a first power; specifically, the contact hole is subjected to dry etching by adopting a radio frequency with the power of 800W, and the ILD dielectric layer, the polysilicon and the silicon oxide are etched. At this time, the surface of the etched contact hole is made of silicon material, and a residual oxide layer still exists.
S3: referring to fig. 3, the residual silicon oxide in the contact hole of the MOSFET is over-etched by using a radio frequency of a second power; specifically, the residual silicon oxide in the contact hole is etched by 30% at a radio frequency of 200W power, so that the residual oxide layer is completely removed. At this time, some etching damage and higher interface states remain on the surface of the silicon material.
S4: referring to fig. 4, interface damage on the surface of the contact hole of the MOSFET is treated by using a mixed solution of low-concentration nitric acid and hydrofluoric acid to reduce the density of interface states; specifically, interface damage on the surface of the contact hole is treated for 10-20 s by adopting a mixed solution of low-concentration nitric acid and hydrofluoric acid, so that the interface state density is reduced. It should be noted that since the etching proceeds isochronously, the interface damage cannot be completely removed, and only the damaged area can be reduced.
S5: referring to fig. 5, the PR photoresist is removed and then metal deposition is performed to form an ohmic contact. The effective contact area is increased due to the repair of the interface damage, so that the contact resistance is reduced.
According to the technology, in the actual chip manufacturing process, the on-resistance of the low-voltage MOSFET device is obviously improved, the on-resistance is reduced by about 15% at present, the failure caused by the on-resistance is improved, the overall yield of the chip is improved by about 12%, and the production cost is reduced.
The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application, or which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.
Claims (5)
1. A manufacturing method for reducing the on-resistance of a MOSFET device is characterized by comprising the following steps:
s1: forming the basic appearance of a contact hole of the MOSFET;
s2: performing dry etching on the MOSFET contact hole by adopting radio frequency with first power;
s3: etching the residual silicon oxide in the contact hole of the MOSFET by adopting radio frequency with second power;
s4: the interface damage on the surface of the contact hole of the MOSFET is treated by adopting a mixed solution of low-concentration nitric acid and hydrofluoric acid, so that the interface state density is reduced;
s5: and removing the photoresist, and then carrying out metal deposition to form ohmic contact.
2. The manufacturing method for reducing the on-resistance of the MOSFET device according to claim 1, wherein the step S1 specifically comprises: thermally growing silicon oxide on the surface of a silicon wafer, depositing polycrystalline silicon, forming a preset pattern by adopting a photoetching and etching mode, depositing an ILD medium layer, flushing the ILD medium layer to remove impurities generated in the deposition process, exposing the position of a contact hole by adopting photoetching, and etching and exposing the contact hole.
3. The manufacturing method for reducing the on-resistance of the MOSFET device according to claim 2, wherein the step S2 specifically comprises: and performing dry etching on the contact hole by adopting the radio frequency with the power of 800W, and etching the ILD dielectric layer, the polysilicon and the silicon oxide.
4. The method according to claim 3, wherein step S3 comprises etching 30% of the residual silicon oxide in the contact hole at a radio frequency of 200W to completely remove the residual oxide layer.
5. The method according to claim 4, wherein the step S4 is performed by treating the interface damage on the surface of the contact hole for 10-20S with a mixture of low-concentration nitric acid and hydrofluoric acid to reduce the density of interface states.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310030128.1A CN115863258A (en) | 2023-01-09 | 2023-01-09 | Manufacturing method for reducing on-resistance of MOSFET device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310030128.1A CN115863258A (en) | 2023-01-09 | 2023-01-09 | Manufacturing method for reducing on-resistance of MOSFET device |
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| CN115863258A true CN115863258A (en) | 2023-03-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202310030128.1A Pending CN115863258A (en) | 2023-01-09 | 2023-01-09 | Manufacturing method for reducing on-resistance of MOSFET device |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0226025A (en) * | 1988-07-14 | 1990-01-29 | Fujitsu Ltd | Method of forming contact hole |
| US5962345A (en) * | 1998-07-13 | 1999-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to reduce contact resistance by means of in-situ ICP |
| US6337273B1 (en) * | 1999-07-27 | 2002-01-08 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating contact of semiconductor device |
| JP2004103680A (en) * | 2002-09-06 | 2004-04-02 | Advanced Display Inc | Method of forming contact hole and liquid crystal display device |
| KR20050122741A (en) * | 2004-06-25 | 2005-12-29 | 주식회사 하이닉스반도체 | Forming method of contact hole in semiconductor device |
| KR20060028239A (en) * | 2004-09-24 | 2006-03-29 | 주식회사 하이닉스반도체 | Method for forming bitline-contact hole in semiconductor device |
| CN111554575A (en) * | 2020-05-13 | 2020-08-18 | 南京大学 | Two-step dry etching method for low surface damage in semiconductor device preparation |
-
2023
- 2023-01-09 CN CN202310030128.1A patent/CN115863258A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0226025A (en) * | 1988-07-14 | 1990-01-29 | Fujitsu Ltd | Method of forming contact hole |
| US5962345A (en) * | 1998-07-13 | 1999-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to reduce contact resistance by means of in-situ ICP |
| US6337273B1 (en) * | 1999-07-27 | 2002-01-08 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating contact of semiconductor device |
| JP2004103680A (en) * | 2002-09-06 | 2004-04-02 | Advanced Display Inc | Method of forming contact hole and liquid crystal display device |
| KR20050122741A (en) * | 2004-06-25 | 2005-12-29 | 주식회사 하이닉스반도체 | Forming method of contact hole in semiconductor device |
| KR20060028239A (en) * | 2004-09-24 | 2006-03-29 | 주식회사 하이닉스반도체 | Method for forming bitline-contact hole in semiconductor device |
| CN111554575A (en) * | 2020-05-13 | 2020-08-18 | 南京大学 | Two-step dry etching method for low surface damage in semiconductor device preparation |
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