KR20050122741A - Forming method of contact hole in semiconductor device - Google Patents
Forming method of contact hole in semiconductor device Download PDFInfo
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- KR20050122741A KR20050122741A KR1020040048369A KR20040048369A KR20050122741A KR 20050122741 A KR20050122741 A KR 20050122741A KR 1020040048369 A KR1020040048369 A KR 1020040048369A KR 20040048369 A KR20040048369 A KR 20040048369A KR 20050122741 A KR20050122741 A KR 20050122741A
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 87
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 239000012535 impurity Substances 0.000 claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 21
- 230000001052 transient effect Effects 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000000926 separation method Methods 0.000 abstract description 2
- 239000007789 gas Substances 0.000 description 18
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 8
- 229910018540 Si C Inorganic materials 0.000 description 8
- 229910052799 carbon Inorganic materials 0.000 description 8
- 229910010271 silicon carbide Inorganic materials 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 239000010410 layer Substances 0.000 description 4
- 238000002513 implantation Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000004833 X-ray photoelectron spectroscopy Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004626 scanning electron microscopy Methods 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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Abstract
본 발명은 BLC2와 같이 기판을 노출시키는 식각 공정에서 PID와 콘택 저항의 증가를 방지할 수 있는 반도체 소자의 콘택홀 형성 방법을 제공하기 위한 것으로, 이를 위해 본 발명은, 불순물 확산영역을 갖는 기판 상의 절연막을 선택적으로 식각하여 상기 불순물 확산영역을 노출시키는 콘택홀을 형성하는 방법에 있어서, 상기 절연막을 선택적으로 식각하여 상기 기판에서 식각을 멈추는 주식각 단계와, 상기 기판의 일부를 과도 식각하는 단계로 분리하여 식각하며, 상기 과도 식각하는 단계에서는 CO와 O2를 제외한 가스를 이용하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법을 제공한다.The present invention provides a method for forming a contact hole in a semiconductor device capable of preventing an increase in PID and contact resistance in an etching process of exposing a substrate, such as BLC2. To this end, the present invention provides a method for forming a contact hole on a substrate having an impurity diffusion region. A method of forming a contact hole for selectively exposing an insulating layer to expose the impurity diffusion region, the method comprising: selectively etching the insulating layer to stop etching from the substrate, and over-etching a portion of the substrate. The separation and etching, the over-etching step provides a method for forming a contact hole in a semiconductor device, characterized in that using a gas other than CO and O 2 .
또한, 본 발명은, 불순물 확산영역을 갖는 기판 상에 절연막을 형성하는 단계; 상기 절연막 상에 반사방지막을 형성하는 단계; 마스크 패턴을 이용하여 상기 반사방지막을 식각하는 단계; 상기 마스크 패턴을 이용하여 상기 절연막을 식각함으로써, 상기 기판에서 식각을 멈추어 상기 불순물 확산영역을 노출시키는 콘택홀을 형성하는 단계; 및 CO와 O2를 제외한 가스를 이용하여 상기 콘택홀에서의 상기 기판의 일부를 과도 식각하는 단계를 포함하는 반도체 소자의 콘택홀 형성 방법을 제공한다.In addition, the present invention comprises the steps of forming an insulating film on a substrate having an impurity diffusion region; Forming an anti-reflection film on the insulating film; Etching the anti-reflection film using a mask pattern; Etching the insulating layer using the mask pattern to form a contact hole in the substrate to stop etching to expose the impurity diffusion region; And over-etching a portion of the substrate in the contact hole using a gas other than CO and O 2 .
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로 특히, PID(Plasma Induced Damage)와 콘택 저항 증가를 방지할 수 있는 반도체 소자의 콘택홀 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device capable of preventing an increase in plasma induced damage (PID) and contact resistance.
반도체 메모리소자 중 DRAM(Dynamic Random Access Memory) 등은 예컨대, 1T1C(하나의 트랜지스터와 하나의 캐패시터)로 구성된 단위 셀을 복수개 포함하는 셀영역과 그 이외의 주변영역으로 크게 구분된다.Among the semiconductor memory devices, a DRAM (Dynamic Random Access Memory) or the like is largely divided into, for example, a cell region including a plurality of unit cells composed of 1T1C (one transistor and one capacitor) and other peripheral regions.
예컨대, 비트라인(Bitline)은 셀 트랜지스터의 소스 쪽에 연결되어 실제로 데이타가 전송되는 라인으로, 셀 영역 측면에서는 이러한 비트라인의 전기적 연결을 위해 게이트전극(예컨대, 워드라인) 측면의 소스/드레인 접합 영역에 콘택된 셀콘택 플러그와의 연결되는 비트라인 콘택 플러그를 통해 콘택되며, 이러한 비트라인을 통해 전달된 셀 데이타를 감지 및 증폭하기 위한 비트라인 감지증폭기(Bitline sense amplifier)를 포함하는 주변영역 측면에서는 비트라인 감지증폭기(구체적으로 비트라인 감지증폭기를 이루는 트랜지스터의 게이트와 소스/드레인 접합)와 비트라인 간의 전기적 연결을 위해 콘택이 필요하다.For example, a bitline is a line connected to the source side of a cell transistor to actually transmit data. On the cell region side, a source / drain junction region on the side of a gate electrode (eg, a wordline) for electrical connection of such a bitline. In terms of the peripheral area, which is contacted through a bitline contact plug connected to a cell contact plug contacted to the cell contact plug, and including a bitline sense amplifier for sensing and amplifying the cell data transmitted through the bitline. A contact is required for the electrical connection between the bit line sense amplifier (specifically, the gate and source / drain junctions of the transistors that make up the bit line sense amplifier) and the bit line.
이하에서는, 셀영역에서의 비트라인콘택(Bitline line contact)을 BLC1이라 하고, 주변영역에서의 비트라인콘택을 BLC2라 한다.Hereinafter, the bit line contact in the cell region is referred to as BLC1, and the bit line contact in the peripheral region is referred to as BLC2.
BLC2 콘택 형성을 위한 식각 공정은 유기 계열의 반사방지막(Organic Bottom Anti-Reflective Coating)을 식각하는 공정과 산화막으로 이루어진 층간절연막을 식각하는 주식각(Main etch) 공정으로 이루어진다.The etching process for forming the BLC2 contact is performed by etching an organic bottom anti-reflective coating and a main etch process by etching an interlayer insulating layer made of an oxide film.
BLC2 식각 공정에서는 기판의 불순물 확산영역 즉, 소스/드레인 접합을 직접 노출시키는 공정이며, 콘택 저항에 영향을 미치는 식각 단계는 층간절연막을 식각하는 주식각 공정이다.In the BLC2 etching process, an impurity diffusion region of a substrate, that is, a source / drain junction is directly exposed, and an etching step that affects contact resistance is a stock angle process of etching an interlayer insulating layer.
한편, 종래의 BLC2 형성을 위한 식각 공정에서, 유기 계열의 반사방지막을 식각하는 단계에서는 CF4/O2/Ar의 가스 조합을 이용하며, 주식각 단계에서는 CHF3/CO/O2/Ar의 가스 조합을 이용하였다.Meanwhile, in the conventional etching process for forming BLC2, a gas combination of CF 4 / O 2 / Ar is used in the etching of the organic antireflection film, and in each stock step, CHF 3 / CO / O 2 / Ar is used. Gas combinations were used.
BLC2 공정에서의 콘택 저항은 에너지를 갖는 이온(Energetic ion)의 충격(Bombardment)에 의한 실리콘 본딩(Silicon bonding)의 데미지 또는 카본(Crabon)등 불순물의 침투(Permeation)에 의한 오염된 막(Contamination layer) 형성 등 PID에 의해 크게 영향을 받는다.The contact resistance in the BLC2 process is contamination layer due to damage of silicon bonding due to impact of energetic ions or permeation of impurities such as carbon. ) It is greatly affected by PID such as formation.
한편, BLC2 식각 공정 중 주식각 단계에서 전술한 거스 조합을 사용하게 되면, 기판의 손실이 과도하여 콘택 표면에서의 도펀트(Dopant)가 유실되어 콘택 저항이 증가하고, 높은 Vpp(peak to peak voltage)에 의한 카본의 기판으로의 주입(Implantation)을 초래하여 콘택 저항을 증가시키게 된다.On the other hand, if the above-mentioned gauze combination is used in the stock angle step of the BLC2 etching process, the substrate loss is excessive and dopants are lost on the contact surface, resulting in increased contact resistance and high peak to peak voltage (Vpp). This results in an implantation of carbon into the substrate, thereby increasing the contact resistance.
한편, Vpp의 검출은 매처(Matcher) 내부에 구성되어 있으며, 매처의 급전봉 둘레에 회로가 있으며, 그 장소에서 검출시키는 고주파 전압의 Vpp를 표시해 주는 값으로 RF 교류 성분을 전류 및 평활한 직류전압으로 해서 모니터링(Monitoring)한다.On the other hand, the detection of Vpp is configured inside the matcher, and there is a circuit around the feeder rod of the matcher. The value of Vpp indicates the high frequency voltage Vpp to be detected at the location. To monitor.
상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 본 발명은, BLC2와 같이 기판을 노출시키는 식각 공정에서 PID와 콘택 저항의 증가를 방지할 수 있는 반도체 소자의 콘택홀 형성 방법을 제공하는 것을 그 목적으로 한다. The present invention proposed to solve the above problems of the prior art, to provide a method for forming a contact hole of a semiconductor device that can prevent the increase of the PID and contact resistance in the etching process of exposing the substrate, such as BLC2. The purpose.
상기와 같은 문제점을 해결하기 위해 본 발명은, 불순물 확산영역을 갖는 기판 상의 절연막을 선택적으로 식각하여 상기 불순물 확산영역을 노출시키는 콘택홀을 형성하는 방법에 있어서, 상기 절연막을 선택적으로 식각하여 상기 기판에서 식각을 멈추는 주식각 단계와, 상기 기판의 일부를 과도 식각하는 단계로 분리하여 식각하며, 상기 과도 식각하는 단계에서는 CO와 O2를 제외한 가스를 이용하는 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법을 제공한다.In order to solve the above problems, the present invention provides a method of selectively etching an insulating film on a substrate having an impurity diffusion region to form a contact hole for exposing the impurity diffusion region, wherein the insulating film is selectively etched to form the contact hole. Method of forming a contact hole in a semiconductor device, characterized in that the etching is separated into a stock etching step of stopping the etching, and a portion of the substrate is over-etched, and in the over-etching step, gases other than CO and O 2 are used. To provide.
또한, 상기와 같은 문제점을 해결하기 위해 본 발명은, 불순물 확산영역을 갖는 기판 상에 절연막을 형성하는 단계; 상기 절연막 상에 반사방지막을 형성하는 단계; 마스크 패턴을 이용하여 상기 반사방지막을 식각하는 단계; 상기 마스크 패턴을 이용하여 상기 절연막을 식각함으로써, 상기 기판에서 식각을 멈추어 상기 불순물 확산영역을 노출시키는 콘택홀을 형성하는 단계; 및 CO와 O2를 제외한 가스를 이용하여 상기 콘택홀에서의 상기 기판의 일부를 과도 식각하는 단계를 포함하는 반도체 소자의 콘택홀 형성 방법을 제공한다.In addition, the present invention to solve the above problems, forming an insulating film on a substrate having an impurity diffusion region; Forming an anti-reflection film on the insulating film; Etching the anti-reflection film using a mask pattern; Etching the insulating layer using the mask pattern to form a contact hole in the substrate to stop etching to expose the impurity diffusion region; And over-etching a portion of the substrate in the contact hole using a gas other than CO and O 2 .
본 발명은 BLC2 등과 같이 기판을 노출시키는 콘택홀 형성을 위한 식각 공정에서 콘택 저항의 증가에 영향을 미치는 과도한 기판의 손실 및 높은 Vpp 현상을 개선하여 콘택 저항을 감소시키고자 한다. 기판의 손실 측면에서, 과도한 기판 손실은 기판의 불순물 확산영역에서의 도펀트를 유실시켜 콘택 저항을 증가시키는 문제가 있으므로, 기판 손실을 감소시키기 위해 종래의 콘택홀 형성시 사용하던 층간절연막에 대한 주식각 공정에서의 CHF3/CO/O2/Ar 가스 조합에서 O2를 빼고, Vpp 측면에서는 높은 Vpp는 카본 주입을 증가시켜 Si-C 본드를 증가시키므로 낮은 이온 에어지 식각을 위해 높은 Vpp를 유발하는 CO 가스를 뺀 레시피를 주식각 단계의 과도 식각 단계로 추가함으로써, 즉 주식각 단계를 기존의 하나의 스텝에서 2개의 스텝으로 분리 실시하여 BLC2 등의 콘택홀 형성시 콘택 저항을 감소시킨다.The present invention is to reduce the contact resistance by improving the high Vpp phenomenon and excessive substrate loss affecting the increase of the contact resistance in the etching process for forming a contact hole to expose the substrate, such as BLC2. In terms of substrate loss, excessive substrate loss causes a problem of increasing contact resistance by losing dopants in an impurity diffusion region of the substrate, so that the stock angle of the interlayer insulating film used to form a conventional contact hole to reduce substrate loss. Remove the CHF 3 / CO / O 2 / Ar O 2 in the gas combination in the process, in the Vpp side high Vpp increases the carbon injection increases the Si-C bond, which leads to high Vpp for low ion air not etch By adding a recipe without CO gas to the transient etching step of the stock angle step, that is, the stock angle step is separated into two steps from one existing step to reduce contact resistance when forming a contact hole such as BLC2.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세하게 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can more easily implement the present invention.
이하에서는 RIE(Reactive Ion Etcher) 타입의 식각 장치에서 식각 공정을 진행하는 것을 예로 하여 설명한다.Hereinafter, an etching process is performed in an RIE (Reactive Ion Etcher) type etching apparatus as an example.
종래의 경우 상기한 바와 같이, 두 단계로 콘택홀 형성을 위한 식각 공정을 진행하였는 바, 유기 계열의 반사방지막(OBARC)을 식각하는 단계와 산화막 계열의 층간절연막을 식각하는 주식각 단계로 이루어진다.In the conventional case, as described above, an etching process for forming a contact hole was performed in two steps. The etching process includes an etching of an organic antireflection film (OBARC) and an etching of an oxide interlayer insulating film.
이 때, 콘택 저항에 직접적으로 영향을 미치는 단계는 주식각 단계이며, 종래의 경우 CHF3/CO/O2/Ar의 가스 조합을 이용하여 이러한 주식각 단계를 하나의 스텝으로 진행하였다.In this case, the step of directly affecting the contact resistance is a stock angle step, and in the conventional case, the stock angle step was performed in one step by using a gas combination of CHF 3 / CO / O 2 / Ar.
그러나, 본 발명에서는 이러한 주식각 단계를 다시 2개의 단계로 나누어 실시하는 바, 첫번째 단계에서는 층간절연막을 식각하여 기판 근처에서 식각을 멈추고(Just etch), 두번째 단계에서는 기판의 일부를 식각하는 과도 식각 단계로 실시한다.However, in the present invention, the stock etch step is divided into two stages. In the first step, the interlayer insulating film is etched to stop the etch near the substrate, and in the second step, the excessive etching to etch a part of the substrate. Carry out in steps.
즉, 층간절연막을 식각할 때 기판 부근에 대한 직접적인 영향이 미치는 과도 식각 단계에서는 CO를 뺌으로써 Vpp에 의한 카본의 기판으로의 주입을 억제하고, 또한 O2를 뺌으로써 기판의 불순물 확산영역에서의 도펀트의 유실을 최소화한다. 이로 인해 PID를 감소시킬 수 있다.In other words, in the transient etching step in which a direct influence on the vicinity of the substrate is directly affected when the interlayer insulating film is etched, the injection of carbon into the substrate by Vpp is suppressed, and the removal of O 2 is performed in the impurity diffusion region of the substrate. Minimize dopant loss. This can reduce the PID.
구체적으로, 과도한 기판의 손실은 불순물 확산영역의 도펀트를 유실시켜 저항을 증가시키게 되므로 기판 손실 증가의 원인이 되는 O2 가스를 빼고, 높은 Vpp로 기판으로의 카본 주입을 초래하여 Si-C 본드를 형성시키는 CO 가스를 뺀 레시피를 과도 식각 단계에서 사용하여 콘택 저항을 감소시킴으로써 반도체 소자의 특성을 향상시킬 수 있다.Specifically, excessive substrate loss causes dopants in the impurity diffusion region to increase resistance, thereby excluding O 2 gas, which causes substrate loss, and injecting carbon into the substrate at a high Vpp to form Si-C bonds. The characteristics of the semiconductor device may be improved by reducing the contact resistance by using a recipe obtained by removing the CO gas to be formed in the transient etching step.
도 1은 X선 광전자 분광기(X-ray Photoelectron Spectroscope; 이하 XPS라 함)를 이용하여 Si-C와 CO의 결합 에너지를 분석한 그래프이다.1 is a graph analyzing binding energy of Si-C and CO using an X-ray photoelectron spectroscope (hereinafter referred to as XPS).
도 1은 Si-C 본드를 나타내는 카본 1s에 대한 분광(Spectra) 특성을 나타내며, Si-C 본드 피크의 강도가 Vpp에 비례하여 증가함을 알 수 있다. 따라서, Vpp가 높아지면 Si-C 강도가 증가하여 오염된 막이 증가하고, 이로 인해 콘택 저항이 증가히게 된다.Figure 1 shows the spectral (Spectra) characteristics for the carbon 1s representing the Si-C bond, it can be seen that the intensity of the Si-C bond peak increases in proportion to Vpp. Therefore, as the Vpp increases, the Si-C strength increases to increase the contaminated film, thereby increasing the contact resistance.
따라서, 낮은 Vpp의 낮은 이온 에너지를 위해 본발명은 CO 가스를 뺀 것이다.Thus, the invention is subtracted from CO gas for low Vpp low ion energy.
도 2는 CO 가스 만을 사용하는 경우와 Ar 가스 만을 사용하는 경우의 Vpp를 비교 도시한 그래프이다.2 is a graph illustrating a comparison of Vpp when using only CO gas and using only Ar gas.
도 2를 참조하면, Ar 만을 사용하는 경우 'A'에 비해 'CO' 만을 사용하는 경우에서 Vpp가 약 370(V) 정도의 높음을 알 수 있다.Referring to FIG. 2, it can be seen that Vpp is about 370 (V) higher in the case of using only 'CO' compared to 'A' when using only Ar.
도 3은 CO 가스의 비율에 따른 Vpp의 변화를 도시한 그래프이다.3 is a graph showing the change of Vpp according to the ratio of CO gas.
여기서, 가로축은 CO와 Ar의 비율 변화를 나타낸다. 도 3을 참조하면, 우측으로 갈수록 CO의 비율이 증가하며, CO의 비율이 증가할 수록 Vpp로 증가함을 확인할 수 있다.Here, the horizontal axis represents the change of the ratio of CO and Ar. Referring to FIG. 3, it can be seen that the ratio of CO increases toward the right side, and increases with Vpp as the ratio of CO increases.
이하에서는, 실제 공정 적용시 사용된 레시피에 따른 종래기술과 본 발명의 BLC2에서의 콘택 저항을 비교하여 살펴 보는 바, 하기의 표 1은 종래기술과 본 발명의 래시피 차이에 따른 BLC2의 콘택 저항을 비교도시한다.Hereinafter, comparing the contact resistance in the BLC2 of the prior art and the present invention according to the recipe used in the actual process application, Table 1 below shows the contact resistance of the BLC2 according to the difference between the prior art and the present invention. Comparison is shown.
표 1을 참조하면, 종래기술과 본 발명은 유기 계열의 반사방지막(OBARC)을 식각하는 공정 레시피는 동일하나, 본 발명은 산화막을 식각하는 주식각 단계를 산화막 식각 단계와 과도 식각 단계로 분리 실시하고 과도 식각 단계에서는 CO와 O2를 뺀 식각 레시피를 적용하였음을 알 수 있다.Referring to Table 1, the prior art and the present invention are the same process recipe for etching an organic anti-reflection film (OBARC), but the present invention is carried out to separate the stock etching step of etching the oxide film into the oxide film etching step and the transient etching step In the excessive etching step, it can be seen that the etching recipe was applied by subtracting CO and O 2 .
이 결과 BLC2의 저항을 1586(Ω)에서 1220(Ω)로 줄여 약 23%의 BLC2 저항 가소 효과가 있음을 확인할 수 있다.As a result, the resistance of BLC2 was reduced from 1586 (Ω) to 1220 (Ω), which shows that the BLC2 resistance plasticization effect is about 23%.
도 4는 종래기술과 본 발명의 콘택 형성에 따른 기판의 손실 양을 비교도시한 SEM(Scanning Electron Microscopy) 사진이다.FIG. 4 is a scanning electron microscopy (SEM) photograph comparing the loss amount of the substrate according to the prior art and the contact formation of the present invention.
도 4의 (a)는 종래의 BLC2 형성을 위한 식각 공정에서 기판의 손실이 153Å 발생한 것을 나타내고, 도 4의 (b)는 본 발명의 BLC2 형성을 위한 식각 공정에서 기판의 손실이 73Å 발생한 것을 나타낸다. 이를 통해, 본 발명의 식각 레시피 적용으로 인해 종래기술에 비해 기판의 손실이 1/2 이상 감소하였음을 알 수 있다. 4 (a) shows that a substrate loss of 153Å has occurred in a conventional etching process for forming BLC2, and FIG. 4 (b) shows that 73Å of substrate loss has occurred in an etching process for forming BLC2 of the present invention. . Through this, it can be seen that the loss of the substrate is reduced by 1/2 or more compared with the prior art due to the application of the etching recipe of the present invention.
도 5는 본 발명과 종래기술의 기판의 불순물 확산영역을 노출시키는 콘택홀 형성 시의 식각 레시피의 차이점을 비교 도시한 도면이다.FIG. 5 is a diagram illustrating a difference between an etching recipe when forming a contact hole exposing an impurity diffusion region of a substrate of the present invention and the prior art.
도 5를 참조하면, 상기한 바아 같이 반사방지막에 대한 식각 단계는 동일하게 실시한다. 반면, 종래기술의 경우 산화막을 식각하는 단계에서 과도 식각까지 동시에 하나의 주식각 공정으로 실시하였으나, 본 발명은 이를 산화막을 식각하여 기판에서 멈추는 주식각 단계와 기판의 일부를 식각하는 과도 식각 단계로 분리 실시하였다.Referring to Figure 5, as described above, the etching step for the anti-reflection film is performed in the same way. On the other hand, in the prior art, the step of etching the oxide film from the etching step to the transient etching at the same time was carried out in one stock etching process, the present invention is a stock etching step of stopping the substrate by etching the oxide film and a transient etching step of etching a part of the substrate. Separation was carried out.
아울러, 과도 식각 단계에서 이온 충격과 주입에 영향을 미치는 O2와 CO를 빼고, 주식각 단계의 시간을 종래의 약 1/2 정도로 실시한다.In addition, in the excess etching step, O 2 and CO, which affect the ion bombardment and implantation, are subtracted, and the stock etching step is performed at about 1/2 of the conventional time.
이하, 전술한 본 발명의 식각 레시피를 보다 구체적으로 살펴 본다.Hereinafter, the etching recipe of the present invention described above will be described in more detail.
유기 계열의 반사방지막 식각시에는, 압력을 20mTorr ∼ 80mTorr, 파워를 700W ∼ 2000W, Ar을 80SCCM ∼ 220SCCM, CF4를 40SCCM ∼ 120SCCM, O2를 10SCCM ∼ 40SCCM으로 하며, 10초 ∼ 30초 동안 실시한다.For organic anti-reflection film etching, pressure is 20mTorr ~ 80mTorr, power is 700W ~ 2000W, Ar is 80SCCM ~ 220SCCM, CF 4 is 40SCCM ~ 120SCCM, O 2 is 10SCCM ~ 40SCCM, and it is carried out for 10 seconds to 30 seconds. do.
또한, 산화막을 식각하는 주식각 단계에서는, 압력을 30mTorr ∼ 90mTorr, 파워를 1000W ∼ 2500W, Ar을 50SCCM ∼ 150SCCM, CO를 80SCCM ∼ 230SCCM, CHF3를 20SCCM ∼ 60SCCM, O2를 10SCCM ∼ 20SCCM으로 하며, 15초 ∼ 45초 동안 실시한다.In the stock angle step of etching the oxide film, the pressure is 30 mTorr to 90 mTorr, the power is 1000 W to 2500 W, the power is 50 SCCM to 150 SCCM, the CO is 80 SCCM to 230 SCCM, the CHF 3 is 20 SCCM to 60 SCCM, and the O 2 is 10 SCCM to 20 SCCM. , 15 seconds to 45 seconds.
아울러, 과도 식각 단계에서는, 압력을 30mTorr ∼ 90mTorr, 파워를 1000W ∼ 2500W, Ar을 120SCCM ∼ 370SCCM, CHF3를 20SCCM ∼ 60SCCM, 10초 ∼ 40초 동안 실시한다.In the transient etching step, the pressure is 30 mTorr to 90 mTorr, the power is 1000 W to 2500 W, the Ar is 120 SCCM to 370 SCCM, and the CHF 3 is performed at 20 SCCM to 60 SCCM for 10 to 40 seconds.
상기한 본 발명에서는 BLC2 형성을 위한 콘택홀 공정을 그 예로 하여 설명하였으나, 전술한 BLC2 이외에 기판과 직접 콘택되는 BLC1, 셀콘택 플러그, 금속 콘택 등 기판의 불순물 확산영역과 접속되는 모든 콘택을 위한 콘택홀 형성 공정에 응용이 가능하다.In the present invention described above, the contact hole process for forming the BLC2 has been described as an example, but in addition to the above-described BLC2, all the contacts for contact with the impurity diffusion region of the substrate, such as BLC1, cell contact plug, and metal contact, which are in direct contact with the substrate, are used. Application to the hole forming process is possible.
전술한 바와 같이 이루어지는 본 발명은, 과도한 기판 손실은 기판의 불순물 확산영역에서의 도펀트를 유실시켜 콘택 저항을 증가시키는 문제가 있으므로, 기판 손실을 감소시키기 위해 종래의 콘택홀 형성시 사용하던 층간절연막에 대한 주식각 공정에서의 CHF3/CO/O2/Ar 가스 조합에서 O2를 빼고, 높은 Vpp는 카본 주입을 증가시켜 Si-C 본드를 증가시키므로 낮은 이온 에너지를 이용한 식각을 위해 높은 Vpp를 유발하는 CO 가스를 뺀 레시피를 주식각 단계 후의 과도 식각 단계로 추가함으로써 콘택홀 형성시 콘택 저항을 감소시킬 수 있음을 실시예를 통해 알아 보았다.According to the present invention, as described above, excessive substrate loss causes a problem of increasing the contact resistance by losing the dopant in the impurity diffusion region of the substrate. Therefore, in order to reduce the substrate loss, the interlayer insulating film used in the conventional contact hole formation is reduced. Subtracting O 2 from the CHF 3 / CO / O 2 / Ar gas combination in the KST process, high Vpp increases carbon implantation and increases Si-C bond, resulting in high Vpp for etching with low ion energy It was found through the example that the contact resistance can be reduced when forming the contact hole by adding a recipe obtained by subtracting CO gas into the transient etching step after the stock angle step.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은, 기판의 불순물 확산영역을 오픈시키는 콘택홀 형성시 도펀트의 감소와 카본 주입등으로 인한 콘택 저항 증가를 방지할 수 있어, 반도체 소자의 성능을 향상시킬 수 있는 효과가 있다.As described above, the present invention can prevent a decrease in dopants and an increase in contact resistance due to carbon injection when forming a contact hole for opening an impurity diffusion region of a substrate, thereby improving performance of a semiconductor device.
도 1은 X선 광전자 분광기를 이용하여 Si-C와 CO의 결합 에너지를 분석한 그래프.1 is a graph analyzing the binding energy of Si-C and CO using an X-ray photoelectron spectroscopy.
도 2는 CO 가스 만을 사용하는 경우와 Ar 가스 만을 사용하는 경우의 Vpp를 비교 도시한 그래프.2 is a graph comparing Vpp when using only CO gas and using only Ar gas.
도 3은 CO 가스의 비율에 따른 Vpp의 변화를 도시한 그래프.3 is a graph showing the change of Vpp according to the ratio of CO gas.
도 4는 종래기술과 본 발명의 콘택 형성에 따른 기판의 손실 양을 비교도시한 SEM 사진.Figure 4 is a SEM photograph showing the amount of loss of the substrate according to the prior art and the contact formation of the present invention.
도 5는 본 발명과 종래기술의 기판의 불순물 확산영역을 노출시키는 콘택홀 형성 시의 식각 레시피의 차이점을 비교 도시한 도면.FIG. 5 is a diagram illustrating a difference between an etching recipe when forming a contact hole exposing an impurity diffusion region of a substrate of the present invention and the prior art. FIG.
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