CN115863149A - Preparation method of gallium oxide structure - Google Patents
Preparation method of gallium oxide structure Download PDFInfo
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- CN115863149A CN115863149A CN202211599581.6A CN202211599581A CN115863149A CN 115863149 A CN115863149 A CN 115863149A CN 202211599581 A CN202211599581 A CN 202211599581A CN 115863149 A CN115863149 A CN 115863149A
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Abstract
The invention provides a preparation method of a gallium oxide structure, which transfers wafer-level gallium nitride to a high-heat-conductivity substrate by an intelligent stripping and transferring method, and then oxidizes a gallium nitride film into a gallium oxide film by oxidation annealing, thereby realizing the heterogeneous integration of the gallium oxide and the high-heat-conductivity substrate, effectively solving the bottleneck problem of heat dissipation of the gallium oxide, and being capable of preparing the gallium oxide structure with large area and high quality.
Description
Technical Field
The invention belongs to the field of semiconductors, and relates to a preparation method of a gallium oxide structure.
Background
Gallium oxide (Ga) 2 O 3 ) As a super-wide bandgap semiconductor material, due to the extremely large bandgap width, the maximum critical breakdown field strength of the super-wide bandgap semiconductor material reaches 8MV/cm, meanwhile, gallium oxide is easy to carry out n-type doping, and good ohmic contact is easy to prepare, so that a power device prepared based on the super-wide bandgap semiconductor material not only has high breakdown voltage, but also has low conduction loss, and the power conversion efficiency of the device is greatly improved. The power quality factor (PFOM) of gallium oxide is 4 times that of gallium nitride (GaN) and 10 times that of silicon carbide (SiC), which are both wide bandgap semiconductor materials. The gallium oxide material has very wide application in power devices in the futureAnd (4) foreground.
However, due to the extremely low thermal conductivity of gallium oxide, the power device of gallium oxide has very serious self-heating effect, thereby reducing the power characteristics of gallium oxide, and simultaneously damaging the service life of gallium oxide, thereby hindering the marketable application of gallium oxide power device.
The intelligent method for peeling and transferring heterogeneous integration is a method for solving better heat dissipation, but because the gallium oxide and the heterogeneous high-heat-conductivity substrate have great thermal mismatch, and meanwhile, the gallium oxide substrate material has two cleavage surfaces, the gallium oxide heterogeneous integration structure is easy to crack in the annealing and peeling process, and the flexibility of the gallium oxide structure prepared by heterogeneous integration is greatly limited.
Therefore, it is necessary to provide a novel method for preparing a gallium oxide structure.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a method for preparing a gallium oxide structure, which is used to solve the problem that it is difficult to prepare a large-area high-thermal-conductivity, integrable gallium oxide structure in the prior art.
To achieve the above and other related objects, the present invention provides a method for preparing a gallium oxide structure, comprising the steps of:
providing a substrate and a gallium nitride single crystal wafer;
carrying out ion implantation on the gallium nitride single crystal wafer to form a defect layer in the gallium nitride single crystal wafer;
bonding the implantation surface of the gallium nitride single crystal wafer with the substrate;
performing annealing stripping to strip off part of the gallium nitride single crystal wafer from the defect layer to form a gallium nitride film on the substrate;
and performing oxidation annealing to convert the gallium nitride film into a gallium oxide film, and preparing the gallium oxide structure.
Optionally, the ion implantation comprises one or a combination of H ion implantation and He ion implantation; the energy of the ion implantation is 3 Kev-150 Kev, and the dosage isIs 2 x 10 16 ions/cm 2 ～5×10 18 ions/cm 2 The temperature is 20-200 ℃.
Optionally, the depth of the ion implantation is 300nm to 500nm.
Optionally, the method of bonding comprises hydrophilic bonding or surface activated bonding.
Optionally, when the surface activation bonding is adopted, the vacuum degree of the surface activation bonding is 1 × 10 -7 Pa～5×10 -6 Pa, pressure of 10 MPa-20 MPa, activation energy of 0.5 Kev-5 Kev for ion implantation, activation voltage of 1000V, and beam current of 10 mA-500 mA.
Optionally, the annealing stripping is performed under a protective atmosphere formed by at least one of nitrogen, oxygen and inert gas, the annealing temperature is 300-800 ℃, and the annealing time is 30 min-36 h.
Optionally, the annealing temperature of the oxidation annealing is 750-1000 ℃, and the annealing time is 30 min-10 h.
Optionally, a process step of performing O ion implantation on the gallium nitride thin film before performing the oxidation annealing is further included, and implantation energy is 5Kev to 50Kev.
Optionally, the substrate comprises one of a SiC substrate, an AlN substrate, a diamond substrate, and a metal substrate.
Optionally, the substrate and the gallium nitride single crystal wafer are both wafer-level in size.
As described above, according to the method for preparing a gallium oxide structure of the present invention, the wafer-level gallium nitride is transferred onto the high thermal conductive substrate by the intelligent lift-off transfer method, and then the gallium nitride thin film is oxidized into the gallium oxide thin film by the oxidation annealing, so that the heterogeneous integration of the gallium oxide and the high thermal conductive substrate is realized, the bottleneck problem of the heat dissipation of the gallium oxide is effectively solved, and the large-area and high-quality gallium oxide structure can be prepared.
Drawings
FIG. 1 is a flow chart of a process for fabricating a gallium oxide structure according to an embodiment of the present invention.
FIG. 2 is a schematic structural diagram of a GaN single-crystal wafer after ion implantation to form a defect layer.
Fig. 3 is a schematic structural view showing a bonded gallium nitride single-crystal wafer and a substrate according to an embodiment of the present invention.
FIG. 4 is a schematic structural diagram of an embodiment of the present invention after an annealing and peeling process.
Fig. 5 is a schematic structural diagram of a gallium oxide structure prepared after performing oxidation annealing according to an embodiment of the present invention.
Description of the element reference numerals
100. Substrate
200. Gallium nitride single crystal wafer
210. Gallium nitride thin film
201. Defective layer
200a implantation surface
300. Gallium oxide thin film
S1 to S5
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Spatially relative terms, such as "under," "below," "lower," "below," "over," "upper," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Where an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
Expressions such as "between 8230 \\8230"; "between 8230"; "may be used herein, inclusive, and expressions such as" plurality "may be used, inclusive, and expressions such as two or more, unless specifically limited otherwise. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
It should be noted that the drawings provided in the present embodiment are only for schematically illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Referring to fig. 1, this embodiment provides a method for fabricating a gallium oxide structure, and the fabrication of the gallium oxide structure is described below with reference to fig. 2 to 5.
First, as shown in fig. 2 and fig. 3, step S1 is performed to provide a substrate 100 and a gan single-chip 200.
As an example, the substrate 100 and the gan single-crystal wafer 200 may have wafer-level dimensions, wherein the dimensions may be selected to include 2 inches to 12 inches, such as 4 inches, 6 inches, 8 inches, 12 inches, etc., so as to prepare large-sized gan structures in subsequent process steps, which may be selected according to requirements.
As an example, the substrate 100 may include one of a SiC substrate, an AlN substrate, a diamond substrate, and a metal substrate to provide a highly thermally conductive substrate to improve heat dissipation capability.
Next, referring to fig. 2, step S2 is performed to perform ion implantation on the single-crystal gan wafer 200 to form a defect layer 201 in the single-crystal gan wafer 200.
As an example, the ion implantation includes one or a combination of H ion implantation and He ion implantation; the ion implantation energy is 3 Kev-150 Kev, such as 3Kev, 30Kev, 50Kev, 80Kev, 100Kev, 150Kev, etc., and the dose is 2 × 10 16 ions/cm 2 ～5×10 18 ions/cm 2 E.g. 2X 10 16 ions/cm 2 、2×10 17 ions/cm 2 、1×10 18 ions/cm 2 、5×10 18 ions/cm 2 And the like at a temperature of 20 ℃ to 200 ℃, such as 20 ℃, 100 ℃, 150 ℃, 200 ℃ and the like.
Illustratively, the depth of the ion implantation is 300nm to 500nm, such as 300nm, 400nm, 500nm, and the like.
Specifically, the arrows in fig. 2 indicate the direction of ion implantation, and the implantation surface is 200a. The ion implantation may be one or a combination of H ion implantation and He ion implantation, and the defect layer 201 may be formed at a predetermined depth in the gallium oxide substrate 200 by controlling an implantation process, and the depth of the ion implantation may be selected as desired.
Next, referring to fig. 3, step S3 is performed to bond the implantation surface 200a of the single-crystal gan wafer 200 to the substrate 100.
As an example, the method of bonding may include hydrophilic bonding or surface activated bonding.
Wherein, when the surface activation bonding is adopted, the vacuum degree of the surface activation bonding can be 1 × 10 -7 Pa～5×10 -6 Pa, e.g. 1X 10 -7 Pa、1×10 -6 Pa、5×10 -6 Pa, etc., pressure of 10MPa &20MPa, such as 10MPa, 15MPa, 20MPa, etc.; the activation energy of ion implantation is 0.5 Kev-5 Kev, such as 0.5Kev, 1Kev, 5Kev, etc.; the activation voltage is 1000V, and the beam current is 10 mA-500 mA, such as 10mA, 100mA, 500mA, and the like.
Next, as shown in fig. 4, step S4 is performed to perform annealing stripping, and strip and remove a portion of the single gallium nitride wafer from the defect layer 201 to form a gallium nitride thin film 210 on the substrate 100.
By way of example, the annealing stripping is performed under a protective atmosphere formed by at least one of nitrogen, oxygen and inert gas, the annealing temperature is 300 ℃ to 800 ℃, such as 300 ℃, 500 ℃, 800 ℃ and the like, and the annealing time is 30min to 36h, such as 30min, 1h, 10h, 36h and the like.
As an example, the method may further include a step of performing O ion implantation on the gallium nitride film 210, wherein the implantation energy is 5Kev to 50Kev, such as 5Kev, 10Kev, 20Kev, 50Kev, and the like, so as to facilitate subsequent oxidation of the gallium nitride film 210.
Next, as shown in fig. 5, step S5 is performed to perform oxidation annealing to convert the gallium nitride film 210 into a gallium oxide film 300, so as to prepare the gallium oxide structure.
By way of example, the annealing temperature of the oxidation annealing is 750 ℃ to 1000 ℃, such as 750 ℃, 800 ℃, 900 ℃, 1000 ℃ and the like, and the annealing time is 30min to 10h, such as 30min, 1h, 2h, 5h, 10h and the like.
Specifically, the oxidation annealing may be performed at a high temperature in an oxidation furnace, so that the gallium nitride film 210 is oxidized and converted into the gallium oxide film 300, thereby realizing heterogeneous integration of gallium oxide and a high thermal conductive substrate, effectively solving a bottleneck problem of heat dissipation of gallium oxide, and preparing a large-area and high-quality gallium oxide structure.
In summary, according to the preparation method of the gallium oxide structure of the present invention, the wafer-level gallium nitride is transferred to the high thermal conductive substrate by the intelligent peeling transfer method, and then the gallium nitride thin film is oxidized into the gallium oxide thin film by the oxidation annealing, so that the heterogeneous integration of the gallium oxide and the high thermal conductive substrate is realized, the bottleneck problem of the heat dissipation of the gallium oxide is effectively solved, and the gallium oxide structure with large area and high quality can be prepared.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (10)
1. A preparation method of a gallium oxide structure is characterized by comprising the following steps:
providing a substrate and a gallium nitride single chip;
carrying out ion implantation on the gallium nitride single crystal wafer to form a defect layer in the gallium nitride single crystal wafer;
bonding the implantation surface of the gallium nitride single crystal wafer with the substrate;
performing annealing stripping to strip off part of the gallium nitride single crystal wafer from the defect layer to form a gallium nitride film on the substrate;
and performing oxidation annealing to convert the gallium nitride film into a gallium oxide film, and preparing the gallium oxide structure.
2. The method for producing a gallium oxide structure according to claim 1, wherein: the ion implantation comprises one or a combination of H ion implantation and He ion implantation; the energy of the ion implantation is 3 Kev-150 Kev, and the dosage is 2 x 10 16 ions/cm 2 ～5×10 18 ions/cm 2 The temperature is 20-200 ℃.
3. The method for producing a gallium oxide structure according to claim 1, characterized in that: the depth of the ion implantation is 300 nm-500 nm.
4. The method for producing a gallium oxide structure according to claim 1, wherein: methods of such bonding include hydrophilic bonding or surface activated bonding.
5. The method for producing a gallium oxide structure according to claim 4, characterized in that: when the surface activation bonding is adopted, the vacuum degree of the surface activation bonding is 1X 10 -7 Pa～5×10 -6 Pa, pressure of 10 MPa-20 MPa, activation energy of 0.5 Kev-5 Kev for ion implantation, activation voltage of 1000V and beam current of 10 mA-500 mA.
6. The method for producing a gallium oxide structure according to claim 1, characterized in that: the annealing stripping is carried out in a protective atmosphere formed by at least one of nitrogen, oxygen and inert gas, the annealing temperature is 300-800 ℃, and the annealing time is 30 min-36 h.
7. The method for producing a gallium oxide structure according to claim 1, characterized in that: the annealing temperature of the oxidation annealing is 750-1000 ℃, and the annealing time is 30 min-10 h.
8. The method for producing a gallium oxide structure according to claim 1, characterized in that: before the oxidation annealing, the method also comprises a process step of carrying out O ion implantation on the gallium nitride film, wherein the implantation energy is 5 Kev-50 Kev.
9. The method for producing a gallium oxide structure according to claim 1, wherein: the substrate includes one of a SiC substrate, an AlN substrate, a diamond substrate, and a metal substrate.
10. The method for producing a gallium oxide structure according to claim 1, characterized in that: the substrate and the gallium nitride single chip are both wafer-level in size.
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| CN111663181A (en) * | 2020-05-20 | 2020-09-15 | 辛国庆 | Preparation method and application of gallium oxide film |
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