WO2015093550A1 - METHOD FOR MANUFACTURING SiC WAFER, METHOD FOR MANUFACTURING SiC SEMICONDUCTOR, AND GRAPHITE SILICON CARBIDE COMPOSITE SUBSTRATE - Google Patents

METHOD FOR MANUFACTURING SiC WAFER, METHOD FOR MANUFACTURING SiC SEMICONDUCTOR, AND GRAPHITE SILICON CARBIDE COMPOSITE SUBSTRATE Download PDF

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WO2015093550A1
WO2015093550A1 PCT/JP2014/083471 JP2014083471W WO2015093550A1 WO 2015093550 A1 WO2015093550 A1 WO 2015093550A1 JP 2014083471 W JP2014083471 W JP 2014083471W WO 2015093550 A1 WO2015093550 A1 WO 2015093550A1
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sic
substrate
layer
graphite
silicon carbide
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PCT/JP2014/083471
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French (fr)
Japanese (ja)
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渉 古市
高木　俊
久保　修一
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イビデン株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

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  • the present invention relates to a method for manufacturing a SiC wafer, a method for manufacturing a SiC semiconductor, and a graphite silicon carbide composite substrate.
  • SiC silicon carbide
  • the dielectric breakdown electric field strength is 10 times that of Si and the band gap is 3 times that of Si.
  • the p-type and n-type control required for device fabrication can be controlled over a wide range. It is expected as a material for power devices exceeding.
  • SiC has a high withstand voltage even with a thinner thickness, it is characterized that a thin semiconductor can be obtained with a low ON resistance by being made thin.
  • SiC semiconductors are expensive and cannot be mass-produced as compared with Si semiconductors because a large-area wafer cannot be obtained and the process is complicated as compared with widely used Si semiconductors.
  • Patent Document 1 discloses a method for manufacturing a silicon carbide substrate, comprising at least a single crystal silicon carbide substrate and a polycrystalline silicon carbide substrate having a micropipe density of 30 / cm 2 or less, and a single crystal silicon carbide substrate. And a step of laminating the polycrystalline silicon carbide substrate and then a step of thinning the single crystal silicon carbide substrate to manufacture a substrate having a single crystal layer formed on the polycrystalline substrate. Yes.
  • a step of forming a hydrogen ion implanted layer by performing hydrogen ion implantation on the single crystal silicon carbide substrate is performed, and a step of bonding the polycrystalline silicon carbide substrate and a step of thinning the single crystal silicon carbide substrate by performing a heat treatment at a temperature of 350 ° C. or less before the step of thinning the single crystal silicon carbide substrate,
  • a method for manufacturing a silicon carbide substrate is described which is a step of mechanically peeling at a hydrogen ion implanted layer. By such a method, more SiC wafers can be obtained from one SiC single crystal ingot.
  • the SiC wafer uses a polycrystalline SiC substrate having a sufficient thickness so as to have mechanical strength so as not to be damaged during handling such as polishing. Therefore, it is necessary to use a polycrystalline SiC substrate that is thicker than necessary to function as a semiconductor.
  • the polycrystalline SiC substrate is thick, the ON resistance increases, and the characteristics of the original SiC semiconductor cannot be exhibited sufficiently. That is, in order to prevent damage to the substrate in the manufacturing process, it is preferable to increase the thickness of the polycrystalline SiC substrate, and to reduce the ON resistance of the obtained SiC semiconductor, it is preferable to use a thin polycrystalline SiC substrate.
  • the first problem of the present invention is that a single-crystal SiC substrate and a polycrystalline SiC substrate are bonded together and then peeled off to obtain a SiC wafer, which is less likely to be damaged by handling, and a thinner SiC wafer can be easily obtained. It is to provide a manufacturing method.
  • the second problem of the present invention is that the SiC semiconductor manufacturing process using the SiC wafer obtained by laminating and bonding the single crystal SiC substrate and the polycrystalline SiC substrate is less likely to be damaged by handling and is thinner.
  • An object of the present invention is to provide a manufacturing method in which a SiC semiconductor can be easily obtained.
  • a third problem of the present invention is that in a manufacturing process for obtaining a SiC wafer by bonding a single crystal SiC substrate and a polycrystalline SiC substrate and then separating them, it is difficult to damage by handling, and a thinner SiC wafer can be easily obtained.
  • An object of the present invention is to provide a polycrystalline SiC substrate.
  • a method for producing an SiC wafer of the present invention for solving the above problems includes a graphite silicon carbide composite substrate having a pyrolytic carbon layer on the surface of a graphite substrate and a CVD-SiC layer on the pyrolytic carbon layer, and a surface A step of preparing a single-crystal SiC substrate having an ion-implanted layer into which hydrogen ions are implanted, and a CVD-SiC layer of the graphite silicon carbide composite substrate and an ion-implanted layer of the single-crystal SiC substrate A bonding step of obtaining a single crystal-coated substrate by heating the bonded body and peeling the ion-implanted layer from the single-crystal SiC substrate; and the pyrolytic carbon layer of the single-crystal-coated substrate; A second peeling step of peeling the CVD-SiC layer to obtain a SiC wafer.
  • the CVD-SiC layer and the ion implantation layer which will later become a SiC wafer, are handled while being bonded to the graphite substrate together with the pyrolytic carbon layer, so that they are damaged during handling such as polishing. Can be difficult.
  • the CVD-SiC layer is supported by the graphite base material, it can be easily handled even if it is thin, and a thin SiC wafer having a small ON resistance can be easily obtained.
  • the SiC wafer manufacturing method of the present invention preferably has the following mode.
  • the graphite silicon carbide composite substrate is a disk and has a marking indicating a direction at the edge thereof
  • the single crystal SiC substrate is a disk and has a marking indicating a direction at the edge
  • the joining step includes The graphite silicon carbide composite substrate and the single crystal SiC substrate are joined together with markings indicating directions.
  • a pattern is formed in a certain direction from a SiC wafer and diced.
  • a graphite silicon carbide composite substrate and a single crystal SiC substrate each having a marking indicating a direction, and joining the graphite silicon carbide composite substrate and the single crystal SiC substrate together with the marking indicating the direction, thereby joining the single crystal SiC substrate can be reflected in the crystal orientation of the SiC wafer, and the crystal orientation of the SiC wafer can be easily confirmed.
  • the marking is an orientation flat or a notch.
  • a crystal manufacturing direction is confirmed by an orientation flat or notch, and semiconductor manufacturing processes such as pattern shape and dicing are performed. For this reason, when the SiC wafer of this invention has an orientation flat or a notch, a SiC semiconductor can be manufactured using the semiconductor manufacturing apparatus which prevails widely.
  • the method for manufacturing the SiC wafer further includes a heat treatment step after the first peeling step.
  • the ion-implanted layer and the CVD-SiC layer can diffuse to each other and be bonded more firmly by a heat treatment process.
  • the thickness of the CVD-SiC layer is 50 to 1000 ⁇ m.
  • the thickness of the CVD-SiC layer is 50 ⁇ m or more, sufficient mechanical strength can be imparted to the SiC semiconductor obtained from the SiC wafer.
  • the thickness of the CVD-SiC layer is 1000 ⁇ m or less, the ON resistance of the SiC semiconductor obtained from the SiC wafer can be reduced.
  • the graphite silicon carbide composite substrate has a region having no pyrolytic carbon layer on the side wall or edge thereof, and the CVD-SiC layer is in contact with the graphite substrate in the region without the pyrolytic carbon layer.
  • SiC having a region without a pyrolytic carbon layer on the side wall or edge of the graphite silicon carbide composite substrate, where the CVD-SiC layer is in contact with the graphite base material in the region without the pyrolytic carbon layer The central portion of the wafer can be easily peeled from the graphite base material, and the peripheral portion can be made difficult to peel from the graphite base material. By appropriately setting the area and region where the graphite base material is exposed, the ease of peeling of the SiC wafer from the single crystal-coated substrate can be easily controlled.
  • a region without the pyrolytic carbon layer on the graphite silicon carbide composite substrate for example, a region where the CVD-SiC layer and the graphite substrate are not in contact with each other at an orientation flat or a notch portion can be formed. Can be easily peeled off.
  • a SiC semiconductor can be obtained by dicing after forming a pattern on the ion-implanted layer of the single crystal-coated substrate. At this time, the CVD-SiC layer constituting the SiC semiconductor is easily peeled off because it is bonded to the graphite base material via the pyrolytic carbon layer.
  • the SiC semiconductor manufacturing method of the present invention includes the above-described SiC wafer manufacturing method and a semiconductor forming step, and the semiconductor forming step is after the heat treatment step and before the second peeling step. .
  • the SiC semiconductor is formed on the single crystal coated substrate and then separated, it is not necessary to handle a thin SiC wafer, and it can be made difficult to damage, and a thin CVD-SiC layer can be used as a part of the SiC semiconductor.
  • the ON resistance of the semiconductor can be easily reduced.
  • a pyrolytic carbon layer and a CVD-SiC layer are sequentially laminated on the surface of a graphite base material which is a disk having a marking on the edge.
  • the CVD-SiC layer and the ion implantation layer which will later become a SiC wafer, are handled while being bonded to the graphite base material together with the pyrolytic carbon layer, and therefore are damaged during handling such as polishing. Can be difficult.
  • the CVD-SiC layer is supported by the graphite base material, it can be easily handled even if it is thin, and a thin SiC wafer having a small ON resistance can be easily obtained.
  • a pattern is formed in a certain direction from a SiC wafer and diced.
  • the graphite silicon carbide composite substrate and the single crystal SiC substrate have markings, and the direction of the single crystal SiC substrate is changed to the crystal of the SiC wafer by joining the graphite silicon carbide composite substrate and the single crystal SiC substrate in alignment.
  • the crystal orientation of the SiC wafer can be easily confirmed.
  • the graphite silicon carbide composite substrate of the present invention desirably has the following mode.
  • the marking is an orientation flat or a notch.
  • semiconductor manufacturing processes such as pattern formability and dicing are performed by confirming crystal orientation by orientation flats or notches. For this reason, when the SiC wafer of this invention has an orientation flat or a notch, a SiC semiconductor can be manufactured using the semiconductor manufacturing apparatus which prevails widely.
  • the thickness of the CVD-SiC layer is 50 to 1000 ⁇ m. When the thickness of the CVD-SiC layer is 50 ⁇ m or more, sufficient mechanical strength can be imparted to the SiC semiconductor obtained from the SiC wafer. When the thickness of the CVD-SiC layer is 1000 ⁇ m or less, the ON resistance of the SiC semiconductor obtained from the SiC wafer can be reduced.
  • the graphite silicon carbide composite substrate has a region having no pyrolytic carbon layer on the side wall or edge thereof, and the CVD-SiC layer is in contact with the graphite substrate in the region without the pyrolytic carbon layer.
  • the central portion of the wafer can be easily peeled from the graphite base material, and the peripheral portion can be made difficult to peel from the graphite base material.
  • a region without the pyrolytic carbon layer on the graphite silicon carbide composite substrate for example, a region where the CVD-SiC layer and the graphite substrate are not in contact with each other at the orientation flat or notch portion can be formed. Can be easily peeled off.
  • a SiC semiconductor can be obtained by forming a pattern on the ion-implanted layer as a single crystal-coated substrate with the graphite base material bonded, and then dicing. At this time, the CVD-SiC layer constituting the SiC semiconductor is easily peeled off because it is bonded to the graphite base material via the pyrolytic carbon layer.
  • a thin SiC wafer can be handled in a state bonded to a graphite substrate, it can be made difficult to damage in the manufacturing process of the SiC wafer, and the obtained SiC wafer can be made thin.
  • a SiC wafer having a small ON resistance can be obtained.
  • a thin SiC wafer can be handled in a state bonded to a graphite substrate, it can be made difficult to damage in the manufacturing process of the SiC semiconductor, and the obtained SiC semiconductor can be made thin.
  • a SiC semiconductor having a small ON resistance can be obtained.
  • a thin SiC wafer can be handled in a state of being bonded to a graphite base material, so that it can be made difficult to be damaged in the manufacturing process of the SiC wafer.
  • the obtained SiC wafer can be thinned, and a SiC wafer having a small ON resistance can be obtained.
  • S1 is a joining process
  • S2 is a 1st peeling process
  • S3 is a 2nd peeling process.
  • the SiC wafer manufacturing method of the present invention includes a graphite silicon carbide composite substrate having a pyrolytic carbon layer on the surface of a graphite substrate and a CVD-SiC layer on the pyrolytic carbon layer, and hydrogen ions are implanted on the surface.
  • the CVD-SiC layer and the ion implantation layer which will later become a SiC wafer, are handled while being bonded to the graphite substrate together with the pyrolytic carbon layer, so that they are damaged during handling such as polishing. Can be difficult.
  • the CVD-SiC layer is supported by the graphite base material, it can be easily handled even if it is thin, and a thin SiC wafer having a small ON resistance can be easily obtained.
  • hydrogen ions By implanting hydrogen into a single crystal SiC substrate, hydrogen ions can reach a depth corresponding to the incident energy.
  • hydrogen collects in implantation defects formed at the time of ion implantation, and the crystal bond can be cut. Since the single crystal SiC substrate is bonded to the CVD-SiC layer, the ion-implanted surface can move to the CVD-SiC layer side in the first peeling step.
  • the single crystal SiC substrate into which hydrogen ions are implanted is brittle while maintaining the surface of the single crystal, and thus can be moved to the CVD-SiC layer while maintaining the single crystal. Since the single-crystal SiC layer is formed on the surface of the CVD-SiC layer after the first peeling step, it is possible to provide an SiC wafer that can be suitably used for an SiC semiconductor by further epitaxially growing the SiC layer. it can.
  • the bonding step of bonding the CVD-SiC layer and the single crystal SiC substrate can be performed as follows.
  • Both the CVD-SiC layer and the single crystal SiC substrate are mirror-polished.
  • the mirror-polished surfaces can be brought into close contact with each other to form a joint surface without a gap.
  • the CVD-SiC layer and the single crystal SiC substrate are preferably cleaned in advance.
  • the cleaning method is not particularly limited, but it is preferable to use, for example, a chemical such as an acid and pure water.
  • a cleaning method RCA cleaning widely used in semiconductor cleaning can be used.
  • RCA cleaning is a cleaning method called SC1, which is a cleaning method using a combination of ammonia, hydrogen peroxide and water, and a cleaning method called SC2, which is a combination of hydrochloric acid, hydrogen peroxide and water. It is mainly used to remove particles and organic contaminants, and in SC2, it is used to remove metal contaminants.
  • the plasma-activated surface is easy to bond, and the CVD-SiC layer and the single crystal SiC substrate can be bonded more firmly.
  • the first peeling step can be peeled by heating the joined body.
  • the ion-implanted layer is fragile because hydrogen ions penetrate inside. When the bonded body is heated, the ion-implanted layer portion that has become brittle due to a difference in thermal expansion between the single crystal SiC substrate and the graphite silicon carbide composite substrate peels off.
  • a single crystal coated substrate is obtained in which about 1 to 10 ⁇ m of the surface of the ion implantation layer is attached to the CVD-SiC layer, and a part of the ion implantation layer is attached to the CVD-SiC layer of the graphite silicon carbide composite substrate. That is, the ion-implanted layer is exposed on either side of the peeled surface.
  • the first peeling step is aimed at separation of the ion implantation layer due to the difference in thermal expansion, so that it can be separated by heating to a temperature of 200 to 1000 ° C., for example, without being involved in a chemical reaction.
  • the graphite silicon carbide composite substrate is a disk and has a marking indicating the direction at the edge thereof
  • the single crystal SiC substrate is a disk and has a marking indicating the direction at the edge
  • the joining step includes the graphite carbonization.
  • the silicon composite substrate and the single crystal SiC substrate are joined together with markings indicating directions.
  • a pattern is formed in a certain direction from a SiC wafer and diced.
  • a graphite silicon carbide composite substrate and a single crystal SiC substrate each having a marking indicating a direction, and joining the graphite silicon carbide composite substrate and the single crystal SiC substrate together with the marking indicating the direction, thereby joining the single crystal SiC
  • the direction of the substrate can be reflected in the crystal orientation of the SiC wafer, and the crystal orientation of the SiC wafer can be easily confirmed.
  • the marking is preferably an orientation flat or a notch.
  • the crystal orientation is confirmed by an orientation flat or notch, and semiconductor formation and dicing are performed. For this reason, when the SiC wafer of this invention has an orientation flat or a notch, a SiC semiconductor can be manufactured using the semiconductor manufacturing apparatus which prevails widely.
  • the SiC wafer manufacturing method preferably further includes a heat treatment step after the first peeling step.
  • the ion-implanted layer and the CVD-SiC layer can be diffused and bonded more firmly to each other by a heat treatment process.
  • the temperature of the heat treatment step is not particularly limited, but is, for example, 1000 to 2000 ° C.
  • the bonding between the ion implantation layer and the CVD-SiC layer can be further strengthened, and when the temperature is 2000 ° C. or lower, crystal defects are less likely to occur in the ion implantation layer that is single crystal SiC.
  • the heating temperature in the heat treatment step is preferably higher than the heating temperature in the first peeling step in order to promote the bonding between the polycrystalline CVD-SiC layer and the single crystal ion implantation layer. Bonding can be further strengthened by heating to a temperature higher than the heating temperature in the first peeling step.
  • the heat treatment step may be either before the second peeling step or after the second peeling step, and is not particularly limited, but is preferably before the second peeling step.
  • the heat treatment step may be either before the second peeling step or after the second peeling step, and is not particularly limited, but is preferably before the second peeling step.
  • the thickness of the CVD-SiC layer is preferably 50 to 1000 ⁇ m. When the thickness of the CVD-SiC layer is 50 ⁇ m or more, sufficient mechanical strength can be imparted to the SiC semiconductor obtained from the SiC wafer. When the thickness of the CVD-SiC layer is 1000 ⁇ m or less, the ON resistance of the SiC semiconductor obtained from the SiC wafer can be reduced.
  • a more desirable CVD-SiC layer thickness is 100 to 500 ⁇ m.
  • the thickness of the CVD-SiC layer is 100 ⁇ m or more, the strength of the SiC semiconductor obtained from the SiC wafer can be further increased.
  • the thickness of the CVD-SiC layer is 500 ⁇ m or less, the ON resistance of the SiC semiconductor obtained from the SiC wafer can be further reduced.
  • the method for producing the SiC wafer includes a region having no pyrolytic carbon layer on a side wall or an edge of the graphite silicon carbide composite substrate, and the CVD-SiC layer is in contact with the graphite substrate in the region without the pyrolytic carbon layer. Preferably it is.
  • the central portion of the wafer can be easily peeled from the graphite base material, and the peripheral portion can be made difficult to peel from the graphite base material.
  • a SiC semiconductor can be formed on the single crystal.
  • a SiC semiconductor can be obtained by forming a SiC semiconductor on a single crystal of a single crystal-coated substrate and then dicing. At this time, the CVD-SiC layer constituting the SiC semiconductor is easily peeled off because it is bonded to the graphite base material via the pyrolytic carbon layer.
  • the formation of the SiC semiconductor is appropriately selected according to the desired SiC semiconductor, such as pattern shape, oxidation, diffusion, CVD, ion implantation, CMP, electrode shape, etching, pattern shape, electrode shape, and photoresist coating. can do.
  • FIG. 1 shows a manufacturing process of the SiC wafer manufacturing method of the present invention, where S1 is a bonding process, S2 is a first peeling process, and S3 is a second peeling process.
  • FIG. 2 is one embodiment of a graphite silicon carbide composite substrate described in the production method of the present invention, wherein (a) has an orientation flat 8a, and (b) is a notch that is a modification thereof. 8b.
  • FIG. 3 is one embodiment of a graphite silicon carbide composite substrate described in the production method of the present invention, wherein (a) has a region having no pyrolytic carbon layer at the edge, and (b) is on the side wall.
  • FIG. 3 (a) has a pyrolytic carbon layer (inside the dotted line) having a smaller diameter than the graphite substrate, and the graphite substrate and the CVD-SiC layer are in contact with the outside of the pyrolytic carbon layer.
  • FIG. 3B has a pyrolytic carbon layer having the same diameter as the graphite base material, but no pyrolytic carbon layer is formed on the side surface of the graphite base material. And the CVD-SiC layer are in contact with each other.
  • a graphite silicon carbide composite substrate 6 including a graphite base material 1, a pyrolytic carbon layer 2, and a CVD-SiC layer 3 is prepared.
  • the graphite substrate 1 has a disk shape with a diameter of 150 mm and a thickness of 2 mm, and is provided with an orientation flat 8a serving as a marking at the edge.
  • the length of the side of the orientation flat 8a is 2 cm.
  • the surface of the graphite substrate 1 is provided with a pyrolytic carbon layer 2 having a thickness of 40 ⁇ m and a diameter of 149 mm. That is, the edge 0.5 mm has no pyrolytic carbon layer 2 and the graphite substrate 1 is in contact with the CVD-SiC layer 3.
  • the outside of the pyrolytic carbon layer 2 is a region 9 without the pyrolytic carbon layer 2.
  • a CVD-SiC layer 3 having a thickness of 500 ⁇ m is provided on the pyrolytic carbon layer 2. That is, the edge 0.5 mm of the CVD-SiC layer 3 is directly formed on the graphite substrate 1 without the pyrolytic carbon layer 2 interposed.
  • RCA cleaning is performed. The RCA cleaning can be performed with a commercially available RCA cleaning solution.
  • a single crystal SiC substrate 4 having an orientation flat is prepared, and hydrogen ions are implanted into one surface thereof.
  • hydrogen ions are implanted into one surface thereof.
  • an ion implantation layer 4a and other regions 4d are formed.
  • RCA cleaning is performed. The RCA cleaning can be performed with a commercially available RCA cleaning solution.
  • the ion-implanted layer 4a of the single crystal SiC substrate 4 and the CVD-SiC layer 3 of the graphite silicon carbide composite substrate 6 are brought into contact with each other and bonded to obtain a joined body 7.
  • the obtained bonded body 7 is heated to be separated by the ion implantation layer 4a. Since the ion implantation layer 4a becomes brittle when hydrogen ions are implanted, the surface portion of the ion implantation layer 4a can be peeled off. In FIG. 1, the ion implantation layer remaining on the single crystal SiC substrate side is 4c, and the ion implantation layer moved to the graphite silicon carbide composite substrate 6 side is 4b.
  • the heating temperature is not particularly limited, but is 400 ° C.
  • the bonded body 7 is separated at the portion of the ion implantation layer 4a by the difference in thermal expansion generated inside the bonded body (FIG. 1 shows the separated ion implanted layer 4b and ion implanted layer 4c).
  • a single crystal coated substrate 5 composed of the graphite substrate 1, the pyrolytic carbon layer 2, the CVD-SiC layer 3, and the ion implantation layer 4b is heat-treated.
  • the heat treatment is performed at 1200 ° C. for 10 minutes. By this treatment, the bonding between the CVD-SiC layer 3 and the ion implantation layer 4b can be strengthened.
  • ⁇ Second peeling step> The single crystal SiC wafer is peeled from the orientation flat portion of the heat-treated single crystal coated substrate.
  • the orientation flat portion can be easily peeled off because the pyrolytic carbon layer 2 is present between the graphite substrate 1 and the CVD-SiC layer 3.
  • Example 2 is a manufacturing method of a SiC semiconductor, and includes a semiconductor formation process between the heat treatment process and the second peeling process of Example 1.
  • the process up to the first peeling step is performed in the same manner as in Example 1 to obtain a single crystal-coated substrate, and then an SiC single crystal is epitaxially grown to form an SiC epitaxial layer. Furthermore, after obtaining the desired SiC semiconductor by pattern formability, oxidation, diffusion, CVD, ion implantation, CMP, electrode formability, etching, pattern formability, electrode formability, and photoresist coating, the SiC semiconductor is formed by dicing. Disconnect. Since the cut SiC semiconductor is in contact with the graphite substrate 1 via the pyrolytic carbon layer 2, it can be easily separated between the pyrolytic carbon layer 2 and the CVD-SiC layer 3.

Abstract

　A method for manufacturing a SiC wafer provided with: a step for readying a graphite silicon carbide composite substrate having a pyrolytic carbon layer on the surface of a graphite substrate and a CVD-SiC layer on the pyrolytic carbon layer, and a monocrystalline SiC substrate having on the surface an ion injection layer into which hydrogen ions are injected; a bonding step for affixing the CVD-SiC layer of the graphite silicon carbide composite substrate and the ion injection layer of the monocrystalline SiC substrate to each other to form an assembly; a first separation step for heating the assembly, separating the ion injection layer from the single crystal SiC substrate, and obtaining a single crystal coated substrate; and a second separation step for separating the pyrolytic carbon layer and the CVD-SiC layer of the single crystal coated substrate and obtaining an SiC wafer.

Description

ＳｉＣウェハの製造方法、ＳｉＣ半導体の製造方法及び黒鉛炭化珪素複合基板SiC wafer manufacturing method, SiC semiconductor manufacturing method, and graphite silicon carbide composite substrate
　本発明は、ＳｉＣウェハの製造方法、ＳｉＣ半導体の製造方法及び黒鉛炭化珪素複合基板に関する。 The present invention relates to a method for manufacturing a SiC wafer, a method for manufacturing a SiC semiconductor, and a graphite silicon carbide composite substrate.
　ＳｉＣ（炭化珪素）はシリコンと炭素で構成される化合物半導体材料である。絶縁破壊電界強度がＳｉの１０倍、バンドギャップがＳｉの３倍と優れているだけでなくデバイス作製に必要なｐ型、ｎ型の制御が広い範囲で可能であることなどから、Ｓｉの限界を超えるパワーデバイス用材料として期待されている。
　また、ＳｉＣは、より薄い厚さでも高い耐電圧が得られるため、薄く構成することにより、ＯＮ抵抗が小さく、低損失の半導体が得られることが特徴である。 SiC (silicon carbide) is a compound semiconductor material composed of silicon and carbon. The dielectric breakdown electric field strength is 10 times that of Si and the band gap is 3 times that of Si. In addition, the p-type and n-type control required for device fabrication can be controlled over a wide range. It is expected as a material for power devices exceeding.
In addition, since SiC has a high withstand voltage even with a thinner thickness, it is characterized that a thin semiconductor can be obtained with a low ON resistance by being made thin.
　しかしながら、ＳｉＣ半導体は、広く普及するＳｉ半導体と比較し、大面積のウェハが得られず、工程も複雑であることから、Ｓｉ半導体と比較して大量生産ができず、高価であった。 However, SiC semiconductors are expensive and cannot be mass-produced as compared with Si semiconductors because a large-area wafer cannot be obtained and the process is complicated as compared with widely used Si semiconductors.
　ＳｉＣ半導体のコストを下げるため、様々な工夫が行われてきた。
　特許文献１には、炭化珪素基板の製造方法であって、少なくとも、マイクロパイプの密度が３０個／ｃｍ２以下の単結晶炭化珪素基板と多結晶炭化珪素基板を準備し、単結晶炭化珪素基板と前記多結晶炭化珪素基板とを貼り合わせる工程を行い、その後、単結晶炭化珪素基板を薄膜化する工程を行い、多結晶基板上に単結晶層を形成した基板を製造することが記載されている。 Various attempts have been made to reduce the cost of SiC semiconductors.
Patent Document 1 discloses a method for manufacturing a silicon carbide substrate, comprising at least a single crystal silicon carbide substrate and a polycrystalline silicon carbide substrate having a micropipe density of 30 / cm 2 or less, and a single crystal silicon carbide substrate. And a step of laminating the polycrystalline silicon carbide substrate and then a step of thinning the single crystal silicon carbide substrate to manufacture a substrate having a single crystal layer formed on the polycrystalline substrate. Yes.
　更に、単結晶炭化珪素基板と多結晶炭化珪素基板とを貼り合わせる工程の前に、単結晶炭化珪素基板に水素イオン注入を行って水素イオン注入層を形成する工程を行い、単結晶炭化珪素基板と多結晶炭化珪素基板とを貼り合わせる工程の後、単結晶炭化珪素基板を薄膜化する工程の前に、３５０℃以下の温度で熱処理を行い、単結晶炭化珪素基板を薄膜化する工程を、水素イオン注入層にて機械的に剥離する工程とする炭化珪素基板の製造方法が記載されている。
　このような方法により、１つのＳｉＣの単結晶のインゴットからより多くのＳｉＣウェハが得られるようになった。 Further, before the step of bonding the single crystal silicon carbide substrate and the polycrystalline silicon carbide substrate, a step of forming a hydrogen ion implanted layer by performing hydrogen ion implantation on the single crystal silicon carbide substrate is performed, And a step of bonding the polycrystalline silicon carbide substrate and a step of thinning the single crystal silicon carbide substrate by performing a heat treatment at a temperature of 350 ° C. or less before the step of thinning the single crystal silicon carbide substrate, A method for manufacturing a silicon carbide substrate is described which is a step of mechanically peeling at a hydrogen ion implanted layer.
By such a method, more SiC wafers can be obtained from one SiC single crystal ingot.
日本国特開２００９－１１７５３３号公報Japanese Unexamined Patent Publication No. 2009-117533
　しかしながら、上記記載されたＳｉＣウェハの製造方法は、水素イオン注入を行って薄いイオン注入層の形成された単結晶ＳｉＣ基板と、多結晶ＳｉＣ基板と、を貼り合わせたのちに加熱して剥離することによって製造されているので、ＳｉＣウェハは、厚さの大部分が多結晶ＳｉＣ基板である。このため、ＳｉＣウェハは、研磨などハンドリングの際に損傷しないよう機械的な強度を有するよう十分な厚さの多結晶ＳｉＣの基板を使用する。そのため、半導体として機能するために必要な厚さよりも厚い多結晶ＳｉＣ基板を用いなければならなない。 However, in the above-described method for manufacturing an SiC wafer, hydrogen ion implantation is performed and a single crystal SiC substrate on which a thin ion implantation layer is formed and a polycrystalline SiC substrate are bonded together, and then heated and peeled off. In most cases, the SiC wafer is a polycrystalline SiC substrate. For this reason, the SiC wafer uses a polycrystalline SiC substrate having a sufficient thickness so as to have mechanical strength so as not to be damaged during handling such as polishing. Therefore, it is necessary to use a polycrystalline SiC substrate that is thicker than necessary to function as a semiconductor.
　多結晶ＳｉＣ基板が厚いと、ＯＮ抵抗が大きくなり、本来のＳｉＣ半導体の特徴が充分に発揮できなくなる。
　つまり、製造工程において基板の損傷を防ぐためには多結晶ＳｉＣ基板を厚くすることが好ましく、得られるＳｉＣ半導体のＯＮ抵抗を小さくするためには薄い多結晶ＳｉＣ基板が好ましい。 If the polycrystalline SiC substrate is thick, the ON resistance increases, and the characteristics of the original SiC semiconductor cannot be exhibited sufficiently.
That is, in order to prevent damage to the substrate in the manufacturing process, it is preferable to increase the thickness of the polycrystalline SiC substrate, and to reduce the ON resistance of the obtained SiC semiconductor, it is preferable to use a thin polycrystalline SiC substrate.
　本発明の第１の課題は、単結晶ＳｉＣ基板と多結晶ＳｉＣ基板とを貼り合わせたのち剥離することによってＳｉＣウェハを得る製造工程において、ハンドリングで損傷しにくく、より薄いＳｉＣウェハが容易に得られる製造方法を提供することにある。 The first problem of the present invention is that a single-crystal SiC substrate and a polycrystalline SiC substrate are bonded together and then peeled off to obtain a SiC wafer, which is less likely to be damaged by handling, and a thinner SiC wafer can be easily obtained. It is to provide a manufacturing method.
　本発明の第２の課題は、単結晶ＳｉＣ基板と多結晶ＳｉＣ基板とを貼り合わせたのち剥離することによって得られるＳｉＣウェハを利用するＳｉＣ半導体の製造工程において、ハンドリングで損傷しにくく、より薄いＳｉＣ半導体が容易に得られる製造方法を提供することにある。 The second problem of the present invention is that the SiC semiconductor manufacturing process using the SiC wafer obtained by laminating and bonding the single crystal SiC substrate and the polycrystalline SiC substrate is less likely to be damaged by handling and is thinner. An object of the present invention is to provide a manufacturing method in which a SiC semiconductor can be easily obtained.
　本発明の第３の課題は、単結晶ＳｉＣ基板と多結晶ＳｉＣ基板とを貼り合わせたのち剥離することによってＳｉＣウェハを得る製造工程において、ハンドリングで損傷しにくく、より薄いＳｉＣウェハが容易に得られる多結晶ＳｉＣ基板を提供することにある。 A third problem of the present invention is that in a manufacturing process for obtaining a SiC wafer by bonding a single crystal SiC substrate and a polycrystalline SiC substrate and then separating them, it is difficult to damage by handling, and a thinner SiC wafer can be easily obtained. An object of the present invention is to provide a polycrystalline SiC substrate.
　前記課題を解決するための本発明のＳｉＣウェハの製造方法は、黒鉛基材の表面に熱分解炭素層および前記熱分解炭素層の上にＣＶＤ－ＳｉＣ層を有する黒鉛炭化珪素複合基板と、表面に水素イオンが注入されたイオン注入層を有する単結晶ＳｉＣ基板とを準備する工程と、前記黒鉛炭化珪素複合基板のＣＶＤ－ＳｉＣ層と前記単結晶ＳｉＣ基板のイオン注入層とを貼り合せ接合体を得る接合工程と、前記接合体を加熱し、前記イオン注入層を単結晶ＳｉＣ基板から剥離し、単結晶被覆基板を得る第１剥離工程と、前記単結晶被覆基板の前記熱分解炭素層とＣＶＤ－ＳｉＣ層とを剥離しＳｉＣウェハを得る第２剥離工程と、を備える。 A method for producing an SiC wafer of the present invention for solving the above problems includes a graphite silicon carbide composite substrate having a pyrolytic carbon layer on the surface of a graphite substrate and a CVD-SiC layer on the pyrolytic carbon layer, and a surface A step of preparing a single-crystal SiC substrate having an ion-implanted layer into which hydrogen ions are implanted, and a CVD-SiC layer of the graphite silicon carbide composite substrate and an ion-implanted layer of the single-crystal SiC substrate A bonding step of obtaining a single crystal-coated substrate by heating the bonded body and peeling the ion-implanted layer from the single-crystal SiC substrate; and the pyrolytic carbon layer of the single-crystal-coated substrate; A second peeling step of peeling the CVD-SiC layer to obtain a SiC wafer.
　本発明のＳｉＣウェハの製造方法は、後にＳｉＣウェハとなるＣＶＤ－ＳｉＣ層とイオン注入層が、熱分解炭素層と共に黒鉛基材と接合したまま取り扱われるので、研磨などのハンドリングの際に損傷しにくくすることができる。 In the method for producing a SiC wafer according to the present invention, the CVD-SiC layer and the ion implantation layer, which will later become a SiC wafer, are handled while being bonded to the graphite substrate together with the pyrolytic carbon layer, so that they are damaged during handling such as polishing. Can be difficult.
　また、ＣＶＤ－ＳｉＣ層は黒鉛基材に支持されているので薄くても容易に取り扱うことができ、厚さが薄いＯＮ抵抗の小さなＳｉＣウェハを容易に得ることができる。 Further, since the CVD-SiC layer is supported by the graphite base material, it can be easily handled even if it is thin, and a thin SiC wafer having a small ON resistance can be easily obtained.
　本発明のＳｉＣウェハの製造方法は、次の態様が好ましい。
（１）前記黒鉛炭化珪素複合基板は円盤であってその縁に方向を示すマーキングを有するともに、前記単結晶ＳｉＣ基板は円盤であってその縁に方向を示すマーキングを有し、前記接合工程は前記黒鉛炭化珪素複合基板と前記単結晶ＳｉＣ基板とを、方向を示すマーキングを合わせて接合する。 The SiC wafer manufacturing method of the present invention preferably has the following mode.
(1) The graphite silicon carbide composite substrate is a disk and has a marking indicating a direction at the edge thereof, and the single crystal SiC substrate is a disk and has a marking indicating a direction at the edge, and the joining step includes The graphite silicon carbide composite substrate and the single crystal SiC substrate are joined together with markings indicating directions.
　ＳｉＣ半導体が充分に機能するために、ＳｉＣウェハから一定の方向に揃えてパターンを形成しダイシングされる。黒鉛炭化珪素複合基板および単結晶ＳｉＣ基板がそれぞれ方向を示すマーキングを有する円盤であって黒鉛炭化珪素複合基板と単結晶ＳｉＣ基板とを方向を示すマーキングを合わせて接合することにより、単結晶ＳｉＣ基板の方向をＳｉＣウェハの結晶方位に反映させることができ、ＳｉＣウェハの結晶方位を容易に確認することができる。 In order for a SiC semiconductor to function sufficiently, a pattern is formed in a certain direction from a SiC wafer and diced. A graphite silicon carbide composite substrate and a single crystal SiC substrate each having a marking indicating a direction, and joining the graphite silicon carbide composite substrate and the single crystal SiC substrate together with the marking indicating the direction, thereby joining the single crystal SiC substrate Can be reflected in the crystal orientation of the SiC wafer, and the crystal orientation of the SiC wafer can be easily confirmed.
（２）前記マーキングは、オリエンテーションフラットまたは切り欠きである。
　一般の半導体製造装置は、オリエンテーションフラットまたは切り欠きによって結晶方向を確認しパターン形性、ダイシングなどの半導体製造工程が行われている。このため本発明のＳｉＣウェハがオリエンテーションフラットまたは切り欠きを有していることにより、広く普及する半導体製造装置を用いてＳｉＣ半導体を製造することができる。 (2) The marking is an orientation flat or a notch.
In a general semiconductor manufacturing apparatus, a crystal manufacturing direction is confirmed by an orientation flat or notch, and semiconductor manufacturing processes such as pattern shape and dicing are performed. For this reason, when the SiC wafer of this invention has an orientation flat or a notch, a SiC semiconductor can be manufactured using the semiconductor manufacturing apparatus which prevails widely.
（３）前記ＳｉＣウェハの製造方法は、第１剥離工程のあとに、熱処理工程を更に有する。
　イオン注入層と、ＣＶＤ－ＳｉＣ層は、熱処理工程によって互いに拡散し合いより強固に接合することができる。 (3) The method for manufacturing the SiC wafer further includes a heat treatment step after the first peeling step.
The ion-implanted layer and the CVD-SiC layer can diffuse to each other and be bonded more firmly by a heat treatment process.
（４）前記ＣＶＤ－ＳｉＣ層の厚さは５０～１０００μｍである。
　ＣＶＤ－ＳｉＣ層の厚さが、５０μｍ以上であると、ＳｉＣウェハから得られるＳｉＣ半導体に十分な機械的な強度を付与することができる。ＣＶＤ－ＳｉＣ層の厚さが、１０００μｍ以下であると、ＳｉＣウェハから得られるＳｉＣ半導体のＯＮ抵抗を小さくすることができる。 (4) The thickness of the CVD-SiC layer is 50 to 1000 μm.
When the thickness of the CVD-SiC layer is 50 μm or more, sufficient mechanical strength can be imparted to the SiC semiconductor obtained from the SiC wafer. When the thickness of the CVD-SiC layer is 1000 μm or less, the ON resistance of the SiC semiconductor obtained from the SiC wafer can be reduced.
（５）前記黒鉛炭化珪素複合基板の側壁または縁に熱分解炭素層の無い領域を有し、前記熱分解炭素層の無い領域ではＣＶＤ－ＳｉＣ層が黒鉛基材と接している。
　黒鉛炭化珪素複合基板の側壁または縁に熱分解炭素層の無い領域を有し、熱分解炭素層の無い領域ではＣＶＤ－ＳｉＣ層が黒鉛基材と接していることにより、ＳｉＣ半導体の得られるＳｉＣウェハの中央部分は黒鉛基材から剥離しやすく、周辺部分は黒鉛基材から剥離しにくくすることができる。黒鉛基材を露出させる面積、領域を適宜設定することにより単結晶被覆基板からＳｉＣウェハの剥離しやすさを容易に制御することができる。 (5) The graphite silicon carbide composite substrate has a region having no pyrolytic carbon layer on the side wall or edge thereof, and the CVD-SiC layer is in contact with the graphite substrate in the region without the pyrolytic carbon layer.
SiC having a region without a pyrolytic carbon layer on the side wall or edge of the graphite silicon carbide composite substrate, where the CVD-SiC layer is in contact with the graphite base material in the region without the pyrolytic carbon layer The central portion of the wafer can be easily peeled from the graphite base material, and the peripheral portion can be made difficult to peel from the graphite base material. By appropriately setting the area and region where the graphite base material is exposed, the ease of peeling of the SiC wafer from the single crystal-coated substrate can be easily controlled.
　黒鉛炭化珪素複合基板に熱分解炭素層の無い領域を適宜形成することにより、例えばオリエンテーションフラットまたは切り欠き部位でＣＶＤ－ＳｉＣ層と黒鉛基材が接していない領域を作ることができ、この部位から容易に剥がすことができる。 By appropriately forming a region without the pyrolytic carbon layer on the graphite silicon carbide composite substrate, for example, a region where the CVD-SiC layer and the graphite substrate are not in contact with each other at an orientation flat or a notch portion can be formed. Can be easily peeled off.
　また、単結晶被覆基板のイオン注入層の上にパターンを形成したのちにダイシングし、ＳｉＣ半導体を得ることができる。このとき、ＳｉＣ半導体を構成するＣＶＤ－ＳｉＣ層は、熱分解炭素層を介して黒鉛基材と接合されているので容易に剥離することができる。 Also, a SiC semiconductor can be obtained by dicing after forming a pattern on the ion-implanted layer of the single crystal-coated substrate. At this time, the CVD-SiC layer constituting the SiC semiconductor is easily peeled off because it is bonded to the graphite base material via the pyrolytic carbon layer.
　また、本発明のＳｉＣ半導体の製造方法は、前記記載のＳｉＣウェハの製造方法と、半導体形成工程とからなり、前記半導体形成工程は、前記熱処理工程の後、前記第２剥離工程の前である。 The SiC semiconductor manufacturing method of the present invention includes the above-described SiC wafer manufacturing method and a semiconductor forming step, and the semiconductor forming step is after the heat treatment step and before the second peeling step. .
　単結晶被覆基板にＳｉＣ半導体を形成したのちに切り離すので、薄いＳｉＣウェハを取り扱う必要が無く、損傷しにくくすることができる上に、薄いＣＶＤ－ＳｉＣ層をＳｉＣ半導体の一部として利用でき、ＳｉＣ半導体のＯＮ抵抗を容易に小さくすることができる。 Since the SiC semiconductor is formed on the single crystal coated substrate and then separated, it is not necessary to handle a thin SiC wafer, and it can be made difficult to damage, and a thin CVD-SiC layer can be used as a part of the SiC semiconductor. The ON resistance of the semiconductor can be easily reduced.
　また、本発明の黒鉛炭化珪素複合基板は、縁にマーキングを有する円盤である黒鉛基材の表面に、順に熱分解炭素層、ＣＶＤ－ＳｉＣ層が積層されている。 In the graphite silicon carbide composite substrate of the present invention, a pyrolytic carbon layer and a CVD-SiC layer are sequentially laminated on the surface of a graphite base material which is a disk having a marking on the edge.
　本発明の黒鉛炭化珪素複合基板は、後にＳｉＣウェハとなるＣＶＤ－ＳｉＣ層とイオン注入層が、熱分解炭素層と共に黒鉛基材と接合したまま取り扱われるので、研磨などのハンドリングの際に損傷しにくくすることができる。 In the graphite silicon carbide composite substrate of the present invention, the CVD-SiC layer and the ion implantation layer, which will later become a SiC wafer, are handled while being bonded to the graphite base material together with the pyrolytic carbon layer, and therefore are damaged during handling such as polishing. Can be difficult.
　また、ＣＶＤ－ＳｉＣ層は黒鉛基材に支持されているので薄くても容易に取り扱うことができ、厚さが薄いＯＮ抵抗の小さなＳｉＣウェハを容易に得ることができる。 Further, since the CVD-SiC layer is supported by the graphite base material, it can be easily handled even if it is thin, and a thin SiC wafer having a small ON resistance can be easily obtained.
　ＳｉＣ半導体が充分に機能するために、ＳｉＣウェハから一定の方向に揃えてパターンを形成しダイシングされる。黒鉛炭化珪素複合基板および単結晶ＳｉＣ基板にマーキングを有し、黒鉛炭化珪素複合基板と単結晶ＳｉＣ基板のマーキングとの方向を合わせて接合することにより、単結晶ＳｉＣ基板の方向をＳｉＣウェハの結晶方位に反映させることができ、ＳｉＣウェハの結晶方位を容易に確認することができる。 In order for a SiC semiconductor to function sufficiently, a pattern is formed in a certain direction from a SiC wafer and diced. The graphite silicon carbide composite substrate and the single crystal SiC substrate have markings, and the direction of the single crystal SiC substrate is changed to the crystal of the SiC wafer by joining the graphite silicon carbide composite substrate and the single crystal SiC substrate in alignment. The crystal orientation of the SiC wafer can be easily confirmed.
　本発明の黒鉛炭化珪素複合基板は次の態様であることが望ましい。
（６）前記マーキングは、オリエンテーションフラットまたは切り欠きである。
　一般の半導体製造装置は、オリエンテーションフラットまたは切り欠きによって結晶方位を確認しパターン形性、ダイシングなどの半導体製造プロセスが行われている。このため本発明のＳｉＣウェハがオリエンテーションフラットまたは切り欠きを有していることにより、広く普及する半導体製造装置を用いてＳｉＣ半導体を製造することができる。 The graphite silicon carbide composite substrate of the present invention desirably has the following mode.
(6) The marking is an orientation flat or a notch.
In general semiconductor manufacturing apparatuses, semiconductor manufacturing processes such as pattern formability and dicing are performed by confirming crystal orientation by orientation flats or notches. For this reason, when the SiC wafer of this invention has an orientation flat or a notch, a SiC semiconductor can be manufactured using the semiconductor manufacturing apparatus which prevails widely.
（７）前記ＣＶＤ－ＳｉＣ層の厚さは５０～１０００μｍである。
　ＣＶＤ－ＳｉＣ層の厚さが、５０μｍ以上であると、ＳｉＣウェハから得られるＳｉＣ半導体に十分な機械的な強度を付与することができる。ＣＶＤ－ＳｉＣ層の厚さが、１０００μｍ以下であると、ＳｉＣウェハから得られるＳｉＣ半導体のＯＮ抵抗を小さくする
ことができる。 (7) The thickness of the CVD-SiC layer is 50 to 1000 μm.
When the thickness of the CVD-SiC layer is 50 μm or more, sufficient mechanical strength can be imparted to the SiC semiconductor obtained from the SiC wafer. When the thickness of the CVD-SiC layer is 1000 μm or less, the ON resistance of the SiC semiconductor obtained from the SiC wafer can be reduced.
（８）前記黒鉛炭化珪素複合基板の側壁または縁に熱分解炭素層の無い領域を有し、前記熱分解炭素層の無い領域ではＣＶＤ－ＳｉＣ層が黒鉛基材と接している。 (8) The graphite silicon carbide composite substrate has a region having no pyrolytic carbon layer on the side wall or edge thereof, and the CVD-SiC layer is in contact with the graphite substrate in the region without the pyrolytic carbon layer.
　黒鉛炭化珪素複合基板の側壁または縁に熱分解炭素層の無い領域を有し、熱分解炭素層の無い領域ではＣＶＤ－ＳｉＣ層が黒鉛基材と接していることにより、ＳｉＣ半導体の得られるＳｉＣウェハの中央部分は黒鉛基材から剥離しやすく、周辺部分は黒鉛基材から剥離しにくくすることができる。黒鉛基材を露出させる面積、領域を適宜設定することにより単結晶被覆基板からＳｉＣウェハの剥離しやすさを容易に制御することができる。 SiC having a region without a pyrolytic carbon layer on the side wall or edge of the graphite silicon carbide composite substrate, where the CVD-SiC layer is in contact with the graphite base material in the region without the pyrolytic carbon layer The central portion of the wafer can be easily peeled from the graphite base material, and the peripheral portion can be made difficult to peel from the graphite base material. By appropriately setting the area and region where the graphite base material is exposed, the ease of peeling of the SiC wafer from the single crystal-coated substrate can be easily controlled.
　黒鉛炭化珪素複合基板に熱分解炭素層の無い領域を適宜形成することにより、例えば、オリエンテーションフラットまたは切り欠き部位でＣＶＤ－ＳｉＣ層と黒鉛基材が接していない領域を作ることができ、この部位から容易に剥がすこともできる。 By appropriately forming a region without the pyrolytic carbon layer on the graphite silicon carbide composite substrate, for example, a region where the CVD-SiC layer and the graphite substrate are not in contact with each other at the orientation flat or notch portion can be formed. Can be easily peeled off.
　また、黒鉛基材の接合したままの単結晶被覆基板としてイオン注入層の上にパターンを形成したのちにダイシングし、ＳｉＣ半導体を得ることができる。このとき、ＳｉＣ半導体を構成するＣＶＤ－ＳｉＣ層は、熱分解炭素層を介して黒鉛基材と接合されているので容易に剥離することができる。 Also, a SiC semiconductor can be obtained by forming a pattern on the ion-implanted layer as a single crystal-coated substrate with the graphite base material bonded, and then dicing. At this time, the CVD-SiC layer constituting the SiC semiconductor is easily peeled off because it is bonded to the graphite base material via the pyrolytic carbon layer.
　本発明によれば、薄いＳｉＣウェハが黒鉛基材に接合した状態で取り扱うことができるので、ＳｉＣウェハの製造工程で損傷しにくくすることができる上に、得られるＳｉＣウェハを薄くすることができ、ＯＮ抵抗の小さなＳｉＣウェハを得ることができる。 According to the present invention, since a thin SiC wafer can be handled in a state bonded to a graphite substrate, it can be made difficult to damage in the manufacturing process of the SiC wafer, and the obtained SiC wafer can be made thin. A SiC wafer having a small ON resistance can be obtained.
　本発明によれば、薄いＳｉＣウェハが黒鉛基材に接合した状態で取り扱うことができるので、ＳｉＣ半導体の製造工程で損傷しにくくすることができる上に、得られるＳｉＣ半導体を薄くすることができ、ＯＮ抵抗の小さなＳｉＣ半導体を得ることができる。 According to the present invention, since a thin SiC wafer can be handled in a state bonded to a graphite substrate, it can be made difficult to damage in the manufacturing process of the SiC semiconductor, and the obtained SiC semiconductor can be made thin. A SiC semiconductor having a small ON resistance can be obtained.
　本発明の多結晶ＳｉＣ基板である黒鉛炭化珪素複合基板によれば、薄いＳｉＣウェハが黒鉛基材に接合した状態で取り扱うことができるので、ＳｉＣウェハの製造工程で損傷しにくくすることができる上に、得られるＳｉＣウェハを薄くすることができ、ＯＮ抵抗の小さなＳｉＣウェハを得ることができる。 According to the graphite silicon carbide composite substrate which is a polycrystalline SiC substrate of the present invention, a thin SiC wafer can be handled in a state of being bonded to a graphite base material, so that it can be made difficult to be damaged in the manufacturing process of the SiC wafer. In addition, the obtained SiC wafer can be thinned, and a SiC wafer having a small ON resistance can be obtained.
本発明のＳｉＣウェハの製造方法の製造工程を示し、Ｓ１は接合工程、Ｓ２は第１剥離工程、Ｓ３は第２剥離工程である。The manufacturing process of the manufacturing method of the SiC wafer of this invention is shown, S1 is a joining process, S2 is a 1st peeling process, S3 is a 2nd peeling process. 本発明の製造方法に記載された黒鉛炭化珪素複合基板の一実施形態であり、（ａ）はオリエンテーションフラットを有し、（ｂ）は切り欠きを有している。It is one Embodiment of the graphite silicon carbide composite substrate described in the manufacturing method of this invention, (a) has an orientation flat, (b) has a notch. 本発明の製造方法に記載された黒鉛炭化珪素複合基板の一実施形態であり、（ａ）は、縁に熱分解炭素層の無い領域を有し、（ｂ）は、側壁に熱分解炭素層の無い領域を有する変形例である。It is one Embodiment of the graphite silicon carbide composite substrate described in the manufacturing method of this invention, (a) has an area | region without a pyrolytic carbon layer in an edge, (b) is a pyrolytic carbon layer in a side wall. It is a modification which has an area | region without.
　本発明のＳｉＣウェハの製造方法は、黒鉛基材の表面に熱分解炭素層および前記熱分解炭素層の上にＣＶＤ－ＳｉＣ層を有する黒鉛炭化珪素複合基板と、表面に水素イオンが注入されたイオン注入層を有する単結晶ＳｉＣ基板とを準備し、前記黒鉛炭化珪素複合基板のＣＶＤ－ＳｉＣ層と前記単結晶ＳｉＣ基板のイオン注入層とを貼り合せ接合体を得る接合工程と、前記接合体を加熱し、前記イオン注入層を単結晶ＳｉＣ基板から剥離し、単結晶被覆基板を得る第１剥離工程と、前記単結晶被覆基板の前記熱分解炭素層とＣＶＤ－ＳｉＣ層とを剥離しＳｉＣウェハを得る第２剥離工程と、からなる。 The SiC wafer manufacturing method of the present invention includes a graphite silicon carbide composite substrate having a pyrolytic carbon layer on the surface of a graphite substrate and a CVD-SiC layer on the pyrolytic carbon layer, and hydrogen ions are implanted on the surface. A bonding step of preparing a single crystal SiC substrate having an ion implantation layer, and bonding a CVD-SiC layer of the graphite silicon carbide composite substrate and an ion implantation layer of the single crystal SiC substrate to obtain a bonded body; And the ion-implanted layer is peeled from the single crystal SiC substrate to obtain a single crystal coated substrate, and the pyrolytic carbon layer and the CVD-SiC layer of the single crystal coated substrate are peeled off to form SiC. A second peeling step for obtaining a wafer.
　本発明のＳｉＣウェハの製造方法は、後にＳｉＣウェハとなるＣＶＤ－ＳｉＣ層とイオン注入層が、熱分解炭素層と共に黒鉛基材と接合したまま取り扱われるので、研磨などのハンドリングの際に損傷しにくくすることができる。 In the method for producing a SiC wafer according to the present invention, the CVD-SiC layer and the ion implantation layer, which will later become a SiC wafer, are handled while being bonded to the graphite substrate together with the pyrolytic carbon layer, so that they are damaged during handling such as polishing. Can be difficult.
　また、ＣＶＤ－ＳｉＣ層は黒鉛基材に支持されているので薄くても容易に取り扱うことができ、厚さが薄いＯＮ抵抗の小さなＳｉＣウェハを容易に得ることができる。 Further, since the CVD-SiC layer is supported by the graphite base material, it can be easily handled even if it is thin, and a thin SiC wafer having a small ON resistance can be easily obtained.
　単結晶ＳｉＣ基板に水素をイオン注入することにより、入射エネルギーに応じた深さまで水素イオンを到達させることができる。水素イオンの注入された単結晶基板は、加熱することによりイオン注入の際に形成された注入欠陥に水素が集まり、結晶の結合を切断することができる。単結晶ＳｉＣ基板は、ＣＶＤ－ＳｉＣ層に接合されているので、イオン注入された表面が第１剥離工程でＣＶＤ－ＳｉＣ層側に移動することができる。 By implanting hydrogen into a single crystal SiC substrate, hydrogen ions can reach a depth corresponding to the incident energy. When a single crystal substrate into which hydrogen ions are implanted is heated, hydrogen collects in implantation defects formed at the time of ion implantation, and the crystal bond can be cut. Since the single crystal SiC substrate is bonded to the CVD-SiC layer, the ion-implanted surface can move to the CVD-SiC layer side in the first peeling step.
　水素イオンが注入された単結晶ＳｉＣ基板は、表面が単結晶の状態を維持したまま脆くなっているので単結晶を維持したままＣＶＤ－ＳｉＣ層に移動させることができる。第１剥離工程の後、ＣＶＤ－ＳｉＣ層の表面に単結晶ＳｉＣ層が形成されているので、さらにＳｉＣ層をエピタキシャル成長させることにより、ＳｉＣ半導体に好適に用いることができるＳｉＣウェハを提供することができる。 The single crystal SiC substrate into which hydrogen ions are implanted is brittle while maintaining the surface of the single crystal, and thus can be moved to the CVD-SiC layer while maintaining the single crystal. Since the single-crystal SiC layer is formed on the surface of the CVD-SiC layer after the first peeling step, it is possible to provide an SiC wafer that can be suitably used for an SiC semiconductor by further epitaxially growing the SiC layer. it can.
　ＣＶＤ－ＳｉＣ層と、単結晶ＳｉＣ基板とを貼り合わせる接合工程は、次のようにして行うことができる。 The bonding step of bonding the CVD-SiC layer and the single crystal SiC substrate can be performed as follows.
　ＣＶＤ－ＳｉＣ層及び単結晶ＳｉＣ基板は、共に鏡面研磨されたものを用いる。鏡面研磨された面同士を密着させ、隙間のない接合面を形成することができる。 Both the CVD-SiC layer and the single crystal SiC substrate are mirror-polished. The mirror-polished surfaces can be brought into close contact with each other to form a joint surface without a gap.
　ＣＶＤ－ＳｉＣ層及び単結晶ＳｉＣ基板は、あらかじめ洗浄されたものを用いることが好ましい。洗浄の方法は特に限定されないが、例えば酸などの化学薬品と純水を用いて洗浄することが好ましい。例えば、洗浄方法は、半導体の洗浄で広く使用されているＲＣＡ洗浄などを利用することができる。ＲＣＡ洗浄とは、ＳＣ１と呼ばれるアンモニアと過酸化水素と水とを組み合わせた洗浄と、ＳＣ２と呼ばれる塩酸と過酸化水素と水とを組み合わせた洗浄の２段階で行われる洗浄方法で、ＳＣ１では、主にパーティクル、有機物汚染の除去、ＳＣ２では、金属汚染の除去に使用される。 The CVD-SiC layer and the single crystal SiC substrate are preferably cleaned in advance. The cleaning method is not particularly limited, but it is preferable to use, for example, a chemical such as an acid and pure water. For example, as a cleaning method, RCA cleaning widely used in semiconductor cleaning can be used. RCA cleaning is a cleaning method called SC1, which is a cleaning method using a combination of ammonia, hydrogen peroxide and water, and a cleaning method called SC2, which is a combination of hydrochloric acid, hydrogen peroxide and water. It is mainly used to remove particles and organic contaminants, and in SC2, it is used to remove metal contaminants.
　ＣＶＤ－ＳｉＣ層または単結晶ＳｉＣ基板の少なくとも一方にプラズマ活性化処理を施すことが好ましい。プラズマ活性化処理された表面は、接合しやすくなっており、より強固にＣＶＤ－ＳｉＣ層と単結晶ＳｉＣ基板を接合することができる。
　第１剥離工程は、接合体を加熱することにより剥離することができる。イオン注入層は、水素イオンが内部に侵入しているので、脆くなっている。接合体を加熱すると、単結晶ＳｉＣ基板と、黒鉛炭化珪素複合基板との熱膨張差で、脆くなったイオン注入層部分で剥離する。イオン注入層の表面の１～１０μｍ程度がＣＶＤ－ＳｉＣ層に貼り付き、黒鉛炭化珪素複合基板のＣＶＤ―ＳｉＣ層にイオン注入層の一部が貼り付いた単結晶被覆基板が得られる。つまり、剥離した面は、いずれの側もイオン注入層が露出している。 It is preferable to perform plasma activation treatment on at least one of the CVD-SiC layer and the single crystal SiC substrate. The plasma-activated surface is easy to bond, and the CVD-SiC layer and the single crystal SiC substrate can be bonded more firmly.
The first peeling step can be peeled by heating the joined body. The ion-implanted layer is fragile because hydrogen ions penetrate inside. When the bonded body is heated, the ion-implanted layer portion that has become brittle due to a difference in thermal expansion between the single crystal SiC substrate and the graphite silicon carbide composite substrate peels off. A single crystal coated substrate is obtained in which about 1 to 10 μm of the surface of the ion implantation layer is attached to the CVD-SiC layer, and a part of the ion implantation layer is attached to the CVD-SiC layer of the graphite silicon carbide composite substrate. That is, the ion-implanted layer is exposed on either side of the peeled surface.
　第１剥離工程は、熱膨張差によるイオン注入層の分離を目的とするので、化学反応に関与せず、例えば２００～１０００℃の温度に加熱することにより分離することができる。 The first peeling step is aimed at separation of the ion implantation layer due to the difference in thermal expansion, so that it can be separated by heating to a temperature of 200 to 1000 ° C., for example, without being involved in a chemical reaction.
　前記黒鉛炭化珪素複合基板は円盤であってその縁に方向を示すマーキングを有するともに、前記単結晶ＳｉＣ基板は円盤であってその縁に方向を示すマーキングを有し、前記接合工程は前記黒鉛炭化珪素複合基板と前記単結晶ＳｉＣ基板と、を方向を示すマーキングを合わせて接合する。 The graphite silicon carbide composite substrate is a disk and has a marking indicating the direction at the edge thereof, and the single crystal SiC substrate is a disk and has a marking indicating the direction at the edge, and the joining step includes the graphite carbonization. The silicon composite substrate and the single crystal SiC substrate are joined together with markings indicating directions.
　ＳｉＣ半導体が充分に機能するために、ＳｉＣウェハから一定の方向に揃えてパターンを形成しダイシングされる。黒鉛炭化珪素複合基板および単結晶ＳｉＣ基板がそれぞれ方向を示すマーキングを有する円盤であって黒鉛炭化珪素複合基板と単結晶ＳｉＣ基板と、を方向を示すマーキングを合わせて接合することにより、単結晶ＳｉＣ基板の方向をＳｉＣウェハの結晶方位に反映させることができ、ＳｉＣウェハの結晶方位を容易に確認することができる。 In order for a SiC semiconductor to function sufficiently, a pattern is formed in a certain direction from a SiC wafer and diced. A graphite silicon carbide composite substrate and a single crystal SiC substrate each having a marking indicating a direction, and joining the graphite silicon carbide composite substrate and the single crystal SiC substrate together with the marking indicating the direction, thereby joining the single crystal SiC The direction of the substrate can be reflected in the crystal orientation of the SiC wafer, and the crystal orientation of the SiC wafer can be easily confirmed.
　前記マーキングは、オリエンテーションフラットまたは切り欠きであることが好ましい。
　一般の半導体製造装置は、オリエンテーションフラットまたは切り欠きによって結晶方位を確認し半導体の形成、ダイシングが行われている。このため本発明のＳｉＣウェハがオリエンテーションフラットまたは切り欠きを有していることにより、広く普及する半導体製造装置を用いてＳｉＣ半導体を製造することができる。 The marking is preferably an orientation flat or a notch.
In a general semiconductor manufacturing apparatus, the crystal orientation is confirmed by an orientation flat or notch, and semiconductor formation and dicing are performed. For this reason, when the SiC wafer of this invention has an orientation flat or a notch, a SiC semiconductor can be manufactured using the semiconductor manufacturing apparatus which prevails widely.
　前記ＳｉＣウェハの製造方法は、第１剥離工程のあとに、熱処理工程を更に有することが好ましい。イオン注入層と、ＣＶＤ－ＳｉＣ層は、熱処理工程によって互いに拡散し合いより強固に接合することができる。 The SiC wafer manufacturing method preferably further includes a heat treatment step after the first peeling step. The ion-implanted layer and the CVD-SiC layer can be diffused and bonded more firmly to each other by a heat treatment process.
　熱処理工程の温度は特に限定されないが、例えば１０００～２０００℃である。１０００℃以上であるとイオン注入層とＣＶＤ－ＳｉＣ層との接合をより強固にでき、２０００℃以下であると単結晶ＳｉＣであるイオン注入層に結晶の欠陥を生じにくくすることができる。熱処理工程の加熱温度は、多結晶であるＣＶＤ－ＳｉＣ層と、単結晶であるイオン注入層との接合を促進する目的から、第１剥離工程の加熱温度より高いことが好ましい。第１剥離工程の加熱温度よりも高温に加熱することによってより接合を強固にすることができる。 The temperature of the heat treatment step is not particularly limited, but is, for example, 1000 to 2000 ° C. When the temperature is 1000 ° C. or higher, the bonding between the ion implantation layer and the CVD-SiC layer can be further strengthened, and when the temperature is 2000 ° C. or lower, crystal defects are less likely to occur in the ion implantation layer that is single crystal SiC. The heating temperature in the heat treatment step is preferably higher than the heating temperature in the first peeling step in order to promote the bonding between the polycrystalline CVD-SiC layer and the single crystal ion implantation layer. Bonding can be further strengthened by heating to a temperature higher than the heating temperature in the first peeling step.
　熱処理工程は、第２剥離工程の前あるいは第２剥離工程の後のいずれであっても良く、特に限定されないが第２剥離工程の前にあることが好ましい。第２剥離工程の前に熱処理工程があると、熱処理工程で反りが発生しにくくすることができる。 The heat treatment step may be either before the second peeling step or after the second peeling step, and is not particularly limited, but is preferably before the second peeling step. When there is a heat treatment step before the second peeling step, it is possible to make it difficult for warpage to occur in the heat treatment step.
　前記ＣＶＤ－ＳｉＣ層の厚さは５０～１０００μｍであることが好ましい。
　ＣＶＤ－ＳｉＣ層の厚さが、５０μｍ以上であると、ＳｉＣウェハから得られるＳｉＣ半導体に十分な機械的な強度を付与することができる。ＣＶＤ－ＳｉＣ層の厚さが、１０００μｍ以下であると、ＳｉＣウェハから得られるＳｉＣ半導体のＯＮ抵抗を小さくすることができる。 The thickness of the CVD-SiC layer is preferably 50 to 1000 μm.
When the thickness of the CVD-SiC layer is 50 μm or more, sufficient mechanical strength can be imparted to the SiC semiconductor obtained from the SiC wafer. When the thickness of the CVD-SiC layer is 1000 μm or less, the ON resistance of the SiC semiconductor obtained from the SiC wafer can be reduced.
　さらに望ましいＣＶＤ－ＳｉＣ層の厚さは１００～５００μｍである。ＣＶＤ－ＳｉＣ層の厚さが、１００μｍ以上であると、ＳｉＣウェハから得られるＳｉＣ半導体の強度をより強くすることができる。ＣＶＤ－ＳｉＣ層の厚さが、５００μｍ以下であると、ＳｉＣウェハから得られるＳｉＣ半導体のＯＮ抵抗をより小さくすることができる。 A more desirable CVD-SiC layer thickness is 100 to 500 μm. When the thickness of the CVD-SiC layer is 100 μm or more, the strength of the SiC semiconductor obtained from the SiC wafer can be further increased. When the thickness of the CVD-SiC layer is 500 μm or less, the ON resistance of the SiC semiconductor obtained from the SiC wafer can be further reduced.
　前記ＳｉＣウェハの製造方法は、前記黒鉛炭化珪素複合基板の側壁または縁に熱分解炭素層の無い領域を有し、前記熱分解炭素層の無い領域ではＣＶＤ－ＳｉＣ層が黒鉛基材と接していることが好ましい。 The method for producing the SiC wafer includes a region having no pyrolytic carbon layer on a side wall or an edge of the graphite silicon carbide composite substrate, and the CVD-SiC layer is in contact with the graphite substrate in the region without the pyrolytic carbon layer. Preferably it is.
　黒鉛炭化珪素複合基板の側壁または縁に熱分解炭素層の無い領域を有し、熱分解炭素層の無い領域ではＣＶＤ－ＳｉＣ層が黒鉛基材と接していることにより、ＳｉＣ半導体の得られるＳｉＣウェハの中央部分は黒鉛基材から剥離しやすく、周辺部分は黒鉛基材から剥離しにくくすることができる。黒鉛基材を露出させる面積、領域を適宜設定することにより単結晶被覆基板からＳｉＣウェハの剥離しやすさを容易に制御することができる。 SiC having a region without a pyrolytic carbon layer on the side wall or edge of the graphite silicon carbide composite substrate, where the CVD-SiC layer is in contact with the graphite base material in the region without the pyrolytic carbon layer The central portion of the wafer can be easily peeled from the graphite base material, and the peripheral portion can be made difficult to peel from the graphite base material. By appropriately setting the area and region where the graphite base material is exposed, the ease of peeling of the SiC wafer from the single crystal-coated substrate can be easily controlled.
　このように黒鉛基材の一部を露出させて黒鉛炭化珪素複合基板を形成することによりＳｉＣウェハの製造工程の途中で黒鉛基材がＳｉＣウェハと分離してしまうことを防止することができる。 In this way, by forming a graphite silicon carbide composite substrate by exposing a part of the graphite base material, it is possible to prevent the graphite base material from being separated from the SiC wafer during the SiC wafer manufacturing process.
　また、ＳｉＣウェハを分離する第２剥離工程の前に、単結晶上にＳｉＣ半導体を形成することができる。具体的には、単結晶被覆基板の単結晶の上にＳｉＣ半導体を形成した後にダイシングし、ＳｉＣ半導体を得ることができる。このとき、ＳｉＣ半導体を構成するＣＶＤ－ＳｉＣ層は、熱分解炭素層を介して黒鉛基材と接合されているので容易に剥離することができる。 Also, before the second peeling step for separating the SiC wafer, a SiC semiconductor can be formed on the single crystal. Specifically, a SiC semiconductor can be obtained by forming a SiC semiconductor on a single crystal of a single crystal-coated substrate and then dicing. At this time, the CVD-SiC layer constituting the SiC semiconductor is easily peeled off because it is bonded to the graphite base material via the pyrolytic carbon layer.
　ＳｉＣ半導体の形成は、パターン形性、酸化、拡散、ＣＶＤ、イオン注入、ＣＭＰ、電極形性、エッチング、パターン形性、電極形性、フォトレジスト塗布など、目的とするＳｉＣ半導体に応じて適宜選択することができる。 The formation of the SiC semiconductor is appropriately selected according to the desired SiC semiconductor, such as pattern shape, oxidation, diffusion, CVD, ion implantation, CMP, electrode shape, etching, pattern shape, electrode shape, and photoresist coating. can do.
　次に本発明に係る実施例１について説明する。図１は、本発明のＳｉＣウェハの製造方法の製造工程を示し、Ｓ１は接合工程、Ｓ２は第１剥離工程、Ｓ３は第２剥離工程である。　図２は、本発明の製造方法に記載された黒鉛炭化珪素複合基板の一実施形態であり、（ａ）はオリエンテーションフラット８ａを有し、（ｂ）はその変形例である切り欠き（ノッチ）８ｂを有している。図３は、本発明の製造方法に記載された黒鉛炭化珪素複合基板の一実施形態であり、（ａ）は、縁に熱分解炭素層の無い領域を有し、（ｂ）は、側壁に熱分解炭素層の無い領域を有する変形例である。図３（ａ）は、黒鉛基材よりも直径の小さな熱分解炭素層（点線の内側）を有し、熱分解炭素層の外側では、黒鉛基材とＣＶＤ－ＳｉＣ層とが接している。図３（ｂ）は、黒鉛基材と同じ直径の熱分解炭素層を有しているが、黒鉛基材の側面には、熱分解炭素層が形成されておらず、側面では、黒鉛基材とＣＶＤ－ＳｉＣ層とが接している。 Next, Example 1 according to the present invention will be described. FIG. 1 shows a manufacturing process of the SiC wafer manufacturing method of the present invention, where S1 is a bonding process, S2 is a first peeling process, and S3 is a second peeling process. FIG. 2 is one embodiment of a graphite silicon carbide composite substrate described in the production method of the present invention, wherein (a) has an orientation flat 8a, and (b) is a notch that is a modification thereof. 8b. FIG. 3 is one embodiment of a graphite silicon carbide composite substrate described in the production method of the present invention, wherein (a) has a region having no pyrolytic carbon layer at the edge, and (b) is on the side wall. It is a modification which has an area | region without a pyrolytic carbon layer. FIG. 3 (a) has a pyrolytic carbon layer (inside the dotted line) having a smaller diameter than the graphite substrate, and the graphite substrate and the CVD-SiC layer are in contact with the outside of the pyrolytic carbon layer. FIG. 3B has a pyrolytic carbon layer having the same diameter as the graphite base material, but no pyrolytic carbon layer is formed on the side surface of the graphite base material. And the CVD-SiC layer are in contact with each other.
＜接合工程＞
　まず、黒鉛基材１と、熱分解炭素層２と、ＣＶＤ－ＳｉＣ層３とを含む黒鉛炭化珪素複合基板６を準備する。黒鉛基材１は、直径φ１５０ｍｍ厚さ２ｍｍの円盤状であり、縁にマーキングとなるオリエンテーションフラット８ａが備えられている。オリエンテーションフラット８ａの辺の長さは２ｃｍである。黒鉛基材１の表面には、厚さが４０μｍ、直径φ１４９ｍｍの熱分解炭素層２が備えられている。すなわち、縁０．５ｍｍは熱分解炭素層２がなく、黒鉛基材１がＣＶＤ－ＳｉＣ層３と接している。すなわち、熱分解炭素層２の外側は熱分解炭素層２の無い領域９である。熱分解炭素層２の上に５００μｍの厚さのＣＶＤ－ＳｉＣ層３が備えられている。すなわち、ＣＶＤ－ＳｉＣ層３の縁０．５ｍｍは、熱分解炭素層２を介在することなく直接黒鉛基材１の上に形成されている。ＣＶＤ－ＳｉＣ層３の表面は研磨されたのち、ＲＣＡ洗浄が行われている。ＲＣＡ洗浄は市販のＲＣＡ洗浄液により行うことができる。 <Joint process>
First, a graphite silicon carbide composite substrate 6 including a graphite base material 1, a pyrolytic carbon layer 2, and a CVD-SiC layer 3 is prepared. The graphite substrate 1 has a disk shape with a diameter of 150 mm and a thickness of 2 mm, and is provided with an orientation flat 8a serving as a marking at the edge. The length of the side of the orientation flat 8a is 2 cm. The surface of the graphite substrate 1 is provided with a pyrolytic carbon layer 2 having a thickness of 40 μm and a diameter of 149 mm. That is, the edge 0.5 mm has no pyrolytic carbon layer 2 and the graphite substrate 1 is in contact with the CVD-SiC layer 3. That is, the outside of the pyrolytic carbon layer 2 is a region 9 without the pyrolytic carbon layer 2. A CVD-SiC layer 3 having a thickness of 500 μm is provided on the pyrolytic carbon layer 2. That is, the edge 0.5 mm of the CVD-SiC layer 3 is directly formed on the graphite substrate 1 without the pyrolytic carbon layer 2 interposed. After the surface of the CVD-SiC layer 3 is polished, RCA cleaning is performed. The RCA cleaning can be performed with a commercially available RCA cleaning solution.
　次に、オリエンテーションフラットを有する単結晶ＳｉＣ基板４を準備し、その一方の面に水素イオンを注入する。水素イオンを注入することによりイオン注入層４ａとそれ以外の領域４ｄが形成される。水素イオンを注入した後、ＲＣＡ洗浄が行われている。ＲＣＡ洗浄は市販のＲＣＡ洗浄液により行うことができる。 Next, a single crystal SiC substrate 4 having an orientation flat is prepared, and hydrogen ions are implanted into one surface thereof. By implanting hydrogen ions, an ion implantation layer 4a and other regions 4d are formed. After implanting hydrogen ions, RCA cleaning is performed. The RCA cleaning can be performed with a commercially available RCA cleaning solution.
　次に単結晶ＳｉＣ基板４のイオン注入層４ａと、黒鉛炭化珪素複合基板６のＣＶＤ－ＳｉＣ層３を接触させ、圧着することにより接合体７を得る。圧着の温度、圧力は特に限定されない。 Next, the ion-implanted layer 4a of the single crystal SiC substrate 4 and the CVD-SiC layer 3 of the graphite silicon carbide composite substrate 6 are brought into contact with each other and bonded to obtain a joined body 7. There are no particular limitations on the temperature and pressure for pressure bonding.
　＜第１剥離工程＞
　得られた接合体７を加熱することにより、イオン注入層４ａで分離する。イオン注入層４ａは、水素イオンが注入されることにより脆くなっているので、イオン注入層４ａの表面部分を剥離させることができる。図１において単結晶ＳｉＣ基板側に残ったイオン注入層は４ｃ、黒鉛炭化珪素複合基板６側に移動したイオン注入層は４ｂである。加熱の温度は特に限定されないが、４００℃である。接合体７は、接合体内部に発生する熱膨張差によって、イオン注入層４ａの部分で分離する（図１においては分離後のイオン注入層４ｂとイオン注入層４ｃを示す）。 <First peeling step>
The obtained bonded body 7 is heated to be separated by the ion implantation layer 4a. Since the ion implantation layer 4a becomes brittle when hydrogen ions are implanted, the surface portion of the ion implantation layer 4a can be peeled off. In FIG. 1, the ion implantation layer remaining on the single crystal SiC substrate side is 4c, and the ion implantation layer moved to the graphite silicon carbide composite substrate 6 side is 4b. The heating temperature is not particularly limited, but is 400 ° C. The bonded body 7 is separated at the portion of the ion implantation layer 4a by the difference in thermal expansion generated inside the bonded body (FIG. 1 shows the separated ion implanted layer 4b and ion implanted layer 4c).
　＜熱処理工程＞
　黒鉛基材１と熱分解炭素層２とＣＶＤ－ＳｉＣ層３とイオン注入層４ｂとからなる単結晶被覆基板５を熱処理する。熱処理は１２００℃で１０分間行う。この処理により、ＣＶＤ－ＳｉＣ層３とイオン注入層４ｂとの接合を強固にすることができる。 <Heat treatment process>
A single crystal coated substrate 5 composed of the graphite substrate 1, the pyrolytic carbon layer 2, the CVD-SiC layer 3, and the ion implantation layer 4b is heat-treated. The heat treatment is performed at 1200 ° C. for 10 minutes. By this treatment, the bonding between the CVD-SiC layer 3 and the ion implantation layer 4b can be strengthened.
　＜第２剥離工程＞
　熱処理された単結晶被覆基板のオリエンテーションフラット部分から単結晶ＳｉＣウェハを剥離する。オリエンテーションフラット部分は、黒鉛基材１とＣＶＤ－ＳｉＣ層３との間に熱分解炭素層２があるので容易に剥離することができる。 <Second peeling step>
The single crystal SiC wafer is peeled from the orientation flat portion of the heat-treated single crystal coated substrate. The orientation flat portion can be easily peeled off because the pyrolytic carbon layer 2 is present between the graphite substrate 1 and the CVD-SiC layer 3.
　次に本発明に係る実施例２について説明する。
　実施例２は、ＳｉＣ半導体の製造方法であり、実施例１の熱処理工程と第２剥離工程との間に、半導体形成工程を有している。 Next, a second embodiment according to the present invention will be described.
Example 2 is a manufacturing method of a SiC semiconductor, and includes a semiconductor formation process between the heat treatment process and the second peeling process of Example 1.
　第１剥離工程まで実施例１と同様に行い、単結晶被覆基板を得た後、ＳｉＣ単結晶をエピタキシャル成長しＳｉＣエピタキシャル層を形成する。更に、パターン形性、酸化、拡散、ＣＶＤ、イオン注入、ＣＭＰ、電極形性、エッチング、パターン形性、電極形性、フォトレジスト塗布によって目的のＳｉＣ半導体を得た後に、ダイシングによって、ＳｉＣ半導体を切断する。切断されたＳｉＣ半導体は、黒鉛基材１と熱分解炭素層２を介して接しているので、熱分解炭素層２とＣＶＤ－ＳｉＣ層３との間で容易に分離することができる。 The process up to the first peeling step is performed in the same manner as in Example 1 to obtain a single crystal-coated substrate, and then an SiC single crystal is epitaxially grown to form an SiC epitaxial layer. Furthermore, after obtaining the desired SiC semiconductor by pattern formability, oxidation, diffusion, CVD, ion implantation, CMP, electrode formability, etching, pattern formability, electrode formability, and photoresist coating, the SiC semiconductor is formed by dicing. Disconnect. Since the cut SiC semiconductor is in contact with the graphite substrate 1 via the pyrolytic carbon layer 2, it can be easily separated between the pyrolytic carbon layer 2 and the CVD-SiC layer 3.
　本出願は、２０１３年１２月１９日出願の日本特許出願、特願２０１３－２６１９０９に基づくものであり、その内容はここに参照として取り込まれる。 This application is based on Japanese Patent Application No. 2013-261909 filed on Dec. 19, 2013, the contents of which are incorporated herein by reference.
１　黒鉛基材
２　熱分解炭素層
３　ＣＶＤ－ＳｉＣ層
４　単結晶ＳｉＣ基板
４ａ、４ｂ、４ｃ　イオン注入層
５　単結晶被覆基板
６　黒鉛炭化珪素複合基板
７　接合体
８ａ　オリエンテーションフラット
８ｂ　切り欠き（ノッチ）
９　熱分解炭素層の無い領域 DESCRIPTION OF SYMBOLS 1 Graphite base material 2 Pyrolytic carbon layer 3 CVD-SiC layer 4 Single crystal SiC substrate 4a, 4b, 4c Ion implantation layer 5 Single crystal coated substrate 6 Graphite silicon carbide composite substrate 7 Joined body 8a Orientation flat 8b Notch
9 Area without pyrolytic carbon layer

Claims (11)

  1. 　黒鉛基材の表面に熱分解炭素層および前記熱分解炭素層の上にＣＶＤ－ＳｉＣ層を有する黒鉛炭化珪素複合基板と、表面に水素イオンが注入されたイオン注入層を有する単結晶ＳｉＣ基板とを準備する工程と、
    　前記黒鉛炭化珪素複合基板のＣＶＤ－ＳｉＣ層と前記単結晶ＳｉＣ基板のイオン注入層とを貼り合せ接合体を得る接合工程と、
    　前記接合体を加熱し、前記イオン注入層を単結晶ＳｉＣ基板から剥離し、単結晶被覆基板を得る第１剥離工程と、
    　前記単結晶被覆基板の熱分解炭素層とＣＶＤ－ＳｉＣ層とを剥離しＳｉＣウェハを得る第２剥離工程と、
    　を備えるＳｉＣウェハの製造方法。     A graphite silicon carbide composite substrate having a pyrolytic carbon layer on the surface of the graphite substrate and a CVD-SiC layer on the pyrolytic carbon layer; and a single crystal SiC substrate having an ion implanted layer in which hydrogen ions are implanted on the surface; The process of preparing
    A bonding step of obtaining a bonded assembly by bonding the CVD-SiC layer of the graphite silicon carbide composite substrate and the ion-implanted layer of the single crystal SiC substrate;
    Heating the joined body, peeling the ion-implanted layer from the single-crystal SiC substrate, and obtaining a single-crystal-coated substrate;
    A second peeling step of peeling the pyrolytic carbon layer and the CVD-SiC layer of the single crystal-coated substrate to obtain a SiC wafer;
    A method of manufacturing a SiC wafer comprising:
  2. 　前記黒鉛炭化珪素複合基板は円盤であってその縁に方向を示すマーキングを有するともに、前記単結晶ＳｉＣ基板は円盤であってその縁に方向を示すマーキングを有し、
    　前記接合工程は前記黒鉛炭化珪素複合基板と前記単結晶ＳｉＣ基板とを、方向を示すマーキングを合わせて接合することを特徴とする請求項１に記載のＳｉＣウェハの製造方法。     The graphite silicon carbide composite substrate is a disc and has a marking indicating a direction on the edge thereof, and the single crystal SiC substrate is a disc and has a marking indicating a direction on the edge,
    2. The method of manufacturing an SiC wafer according to claim 1, wherein the joining step joins the graphite silicon carbide composite substrate and the single crystal SiC substrate together with markings indicating directions.
  3. 　前記マーキングは、オリエンテーションフラットまたは切り欠きであることを特徴とする請求項２に記載のＳｉＣウェハの製造方法。 3. The SiC wafer manufacturing method according to claim 2, wherein the marking is an orientation flat or a notch.
  4. 　前記ＳｉＣウェハの製造方法は、第１剥離工程のあとに、熱処理工程を更に有することを特徴とする請求項１から３のいずれか１項に記載のＳｉＣウェハの製造方法。 4. The method for manufacturing an SiC wafer according to claim 1, wherein the method for manufacturing an SiC wafer further includes a heat treatment step after the first peeling step. 5.
  5. 　前記ＣＶＤ－ＳｉＣ層の厚さは５０～１０００μｍであることを特徴とする請求項１から４のいずれか１項に記載のＳｉＣウェハの製造方法。 The method for producing an SiC wafer according to any one of claims 1 to 4, wherein the CVD-SiC layer has a thickness of 50 to 1000 µm.
  6. 　前記黒鉛炭化珪素複合基板の側壁または縁に熱分解炭素層の無い領域を有し、前記熱分解炭素層の無い領域ではＣＶＤ－ＳｉＣ層が黒鉛基材と接していることを特徴とする請求項１から５のいずれか１項に記載のＳｉＣウェハの製造方法。 The graphite silicon carbide composite substrate has a region having no pyrolytic carbon layer on a side wall or an edge thereof, and the CVD-SiC layer is in contact with the graphite substrate in the region without the pyrolytic carbon layer. The manufacturing method of the SiC wafer of any one of 1 to 5.
  7. 　請求項４から６のいずれか１項に記載のＳｉＣウェハの製造方法と、半導体形成工程とからなるＳｉＣ半導体の製造方法であって、前記半導体形成工程は、前記熱処理工程の後、前記第２剥離工程の前であるＳｉＣ半導体の製造方法。 A SiC semiconductor manufacturing method comprising the SiC wafer manufacturing method according to any one of claims 4 to 6 and a semiconductor forming step, wherein the semiconductor forming step includes the second step after the heat treatment step. A method of manufacturing an SiC semiconductor before the peeling step.
  8. 　縁にマーキングを有する円盤である黒鉛基材の表面に、順に熱分解炭素層、ＣＶＤ－ＳｉＣ層が積層されていることを特徴とする黒鉛炭化珪素複合基板。 A graphite silicon carbide composite substrate in which a pyrolytic carbon layer and a CVD-SiC layer are sequentially laminated on the surface of a graphite base material which is a disc having a marking on an edge.
  9. 　前記マーキングは、オリエンテーションフラットまたは切り欠きであることを特徴とする請求項８に記載の黒鉛炭化珪素複合基板。 The graphite silicon carbide composite substrate according to claim 8, wherein the marking is an orientation flat or a notch.
  10. 　前記ＣＶＤ－ＳｉＣ層の厚さは５０～１０００μｍであることを特徴とする請求項８または９に記載の黒鉛炭化珪素複合基板。 10. The graphite silicon carbide composite substrate according to claim 8, wherein the CVD-SiC layer has a thickness of 50 to 1000 μm.
  11. 　前記黒鉛炭化珪素複合基板の側壁または縁に熱分解炭素層の無い領域を有し、前記熱分解炭素層の無い領域ではＣＶＤ－ＳｉＣ層が黒鉛基材と接していることを特徴とする請求項８から１０のいずれか１項に記載の黒鉛炭化珪素複合基板。 The graphite silicon carbide composite substrate has a region having no pyrolytic carbon layer on a side wall or an edge thereof, and the CVD-SiC layer is in contact with the graphite substrate in the region without the pyrolytic carbon layer. The graphite silicon carbide composite substrate according to any one of 8 to 10.
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