WO2016006640A1

WO2016006640A1 - METHOD FOR PRODUCING SiC WAFER, METHOD FOR PRODUCING SiC SEMICONDUCTOR, AND SILICON CARBIDE COMPOSITE SUBSTRATE

Info

Publication number: WO2016006640A1
Application number: PCT/JP2015/069702
Authority: WO
Inventors: 渉古市; 淳仁長田; 祐樹水向
Original assignee: イビデン株式会社
Priority date: 2014-07-08
Filing date: 2015-07-08
Publication date: 2016-01-14
Also published as: JP2016018890A; JP6371142B2

Abstract

Provided is a method for producing an SiC wafer, said method comprising: a step of preparing a silicon carbide composite substrate that has a vitreous carbon layer on the surface of an SiC substrate and a CVD-SiC layer atop the vitreous carbon layer, and preparing a single-crystal SiC substrate that has on the surface an ion injection layer into which hydrogen ions have been injected; a joining step in which a joined body is obtained by bonding the CVD-SiC layer of the silicon carbide composite substrate and the ion injection layer of the single-crystal SiC substrate; a first separation step in which a single-crystal coated substrate is obtained by heating the joined body and separating the ion injection layer from the single-crystal SiC substrate; and a second separation step in which an SiC wafer is obtained by separating the vitreous carbon layer and CVD-SiC layer of the single-crystal coated substrate.

Description

SiC wafer manufacturing method, SiC semiconductor manufacturing method, and silicon carbide composite substrate

The present invention relates to a method for manufacturing a SiC wafer, a method for manufacturing a SiC semiconductor, and a silicon carbide composite substrate.

SiC (silicon carbide) is a compound semiconductor material composed of silicon and carbon. The dielectric breakdown electric field strength is 10 times that of Si and the band gap is 3 times that of Si. In addition, the p-type and n-type control required for device fabrication can be controlled over a wide range. It is expected as a material for power devices exceeding.
In addition, since SiC has a high withstand voltage even with a thinner thickness, it is characterized that a thin semiconductor can be obtained with a low ON resistance by being made thin.

However, SiC semiconductors are expensive and cannot be mass-produced as compared with Si semiconductors because a large-area wafer cannot be obtained and the process is complicated as compared with widely used Si semiconductors.

Various attempts have been made to reduce the cost of SiC semiconductors.
Patent Document 1 discloses a method for manufacturing a silicon carbide substrate, comprising at least a single crystal silicon carbide substrate and a polycrystalline silicon carbide substrate having a micropipe density of 30 / cm ² or less, and a single crystal silicon carbide substrate. And a step of laminating the polycrystalline silicon carbide substrate and then a step of thinning the single crystal silicon carbide substrate to manufacture a substrate having a single crystal layer formed on the polycrystalline substrate. Yes.

Further, before the step of bonding the single crystal silicon carbide substrate and the polycrystalline silicon carbide substrate, a step of forming a hydrogen ion implanted layer by performing hydrogen ion implantation on the single crystal silicon carbide substrate is performed, And a step of bonding the polycrystalline silicon carbide substrate and a step of thinning the single crystal silicon carbide substrate by performing a heat treatment at a temperature of 350 ° C. or less before the step of thinning the single crystal silicon carbide substrate, A method for manufacturing a silicon carbide substrate is described which is a step of mechanically peeling at a hydrogen ion implanted layer.
By such a method, more SiC wafers can be obtained from one SiC single crystal ingot.

Japanese Unexamined Patent Publication No. 2009-117533

However, in the above-described method for manufacturing an SiC wafer, hydrogen ion implantation is performed and a single crystal SiC substrate on which a thin ion implantation layer is formed and a polycrystalline SiC substrate are bonded together, and then heated and peeled off. In most cases, the SiC wafer is a polycrystalline SiC substrate. For this reason, the SiC wafer uses a polycrystalline SiC substrate having a sufficient thickness so as to have mechanical strength so as not to be damaged during handling such as polishing. Therefore, it is necessary to use a polycrystalline SiC substrate that is thicker than necessary to function as a semiconductor.

If the polycrystalline SiC substrate is thick, the ON resistance increases, and the characteristics of the original SiC semiconductor cannot be exhibited sufficiently.
That is, in order to prevent damage to the substrate in the manufacturing process, it is preferable to increase the thickness of the polycrystalline SiC substrate, and to reduce the ON resistance of the obtained SiC semiconductor, it is preferable to use a thin polycrystalline SiC substrate.

The first problem of the present invention is that a single-crystal SiC substrate and a polycrystalline SiC substrate are bonded together and then peeled off to obtain a SiC wafer, which is less likely to be damaged by handling, and a thinner SiC wafer can be easily obtained. It is to provide a manufacturing method.

The second problem of the present invention is that the SiC semiconductor manufacturing process using the SiC wafer obtained by laminating and bonding the single crystal SiC substrate and the polycrystalline SiC substrate is less likely to be damaged by handling and is thinner. An object of the present invention is to provide a manufacturing method in which a SiC semiconductor can be easily obtained.

A third problem of the present invention is that in a manufacturing process for obtaining a SiC wafer by bonding a single crystal SiC substrate and a polycrystalline SiC substrate and then separating them, it is difficult to damage by handling, and a thinner SiC wafer can be easily obtained. An object of the present invention is to provide a polycrystalline SiC substrate.

The SiC wafer manufacturing method of the present invention for solving the above problems includes a silicon carbide composite substrate having a glassy carbon layer on the surface of a SiC substrate and a CVD-SiC layer on the glassy carbon layer, and a surface. A step of preparing a single-crystal SiC substrate having an ion-implanted layer into which hydrogen ions are implanted, a CVD-SiC layer of the silicon carbide composite substrate, and an ion-implanted layer of the single-crystal SiC substrate are bonded to obtain a joined body. A bonding step, a first peeling step of heating the bonded body and peeling the ion-implanted layer from the single crystal SiC substrate to obtain a single crystal coated substrate, and the glassy carbon layer of the single crystal coated substrate and the CVD- A second peeling step of peeling the SiC layer to obtain a SiC wafer.

In the method for producing a SiC wafer according to the present invention, the CVD-SiC layer and the ion-implanted layer, which will later become a SiC wafer, are handled while being bonded to the SiC substrate together with the glassy carbon layer, so that they are damaged during handling such as polishing. Can be difficult.

Further, since the CVD-SiC layer is supported by the SiC base material, it can be easily handled even if it is thin, and a thin SiC wafer with a small ON resistance can be easily obtained.

And, since the SiC base material having the same material as the CVD-SiC layer is used, the difference in thermal expansion between the layers can be reduced. Furthermore, since the SiC base material is hard and has high bending elasticity, warpage that occurs during manufacturing is suppressed. Since SiC has small variations in characteristics such as thermal expansion due to crystals and is easy to control, the design is easy and the CVD-SiC layer can be made thin.

In addition, by using a glassy carbon layer for adhesion between the SiC substrate and the CVD-SiC layer, it is possible to suppress warpage and improve the flatness of the upper surface of the glassy carbon layer. The glassy carbon constituting the glassy carbon layer can be obtained by carbonizing a solvent containing a resin such as a phenol resin, a furan resin, or an imide resin. Therefore, the flatness of the coated surface after applying the solvent on the SiC substrate is poor, but the solvent applied when carbonizing volatilizes, so the resulting glassy carbon layer does not crack. getting thin. Originally, since the flatness of the SiC base material is good, a flat glassy carbon layer can be obtained.

The SiC wafer manufacturing method of the present invention preferably has the following mode.
(1) The silicon carbide composite substrate is a disk and has a marking indicating a direction at the edge thereof, and the single crystal SiC substrate is a disk and has a marking indicating a direction at the edge, and the bonding step includes The silicon carbide composite substrate and the single crystal SiC substrate are joined together with markings indicating directions.

In order for a SiC semiconductor to function sufficiently, a pattern is formed in a certain direction from a SiC wafer and diced. The silicon carbide composite substrate and the single crystal SiC substrate are discs each having a marking indicating a direction, and the silicon carbide composite substrate and the single crystal SiC substrate are joined together with the marking indicating the direction to thereby align the direction of the single crystal SiC substrate. Can be reflected in the crystal orientation of the SiC wafer, and the crystal orientation of the SiC wafer can be easily confirmed.

(2) The marking is an orientation flat or a notch.
In a general semiconductor manufacturing apparatus, a crystal manufacturing direction is confirmed by an orientation flat or notch, and semiconductor manufacturing processes such as pattern shape and dicing are performed. For this reason, when the SiC wafer of this invention has an orientation flat or a notch, a SiC semiconductor can be manufactured using the semiconductor manufacturing apparatus which prevails widely.

(3) The method for manufacturing the SiC wafer further includes a heat treatment step after the first peeling step.
The ion-implanted layer and the CVD-SiC layer can be diffused and bonded more firmly to each other by a heat treatment process.

(4) The thickness of the CVD-SiC layer is 50 to 1000 μm.
When the thickness of the CVD-SiC layer is 50 μm or more, sufficient mechanical strength can be imparted to the SiC semiconductor obtained from the SiC wafer. When the thickness of the CVD-SiC layer is 1000 μm or less, the ON resistance of the SiC semiconductor obtained from the SiC wafer can be reduced.

(5) The silicon carbide composite substrate has a region without a glassy carbon layer on a side wall or an edge thereof, and the CVD-SiC layer is in contact with the SiC substrate in the region without the glassy carbon layer.
An SiC wafer from which a SiC semiconductor is obtained by having a region without a glassy carbon layer on the side wall or edge of the silicon carbide composite substrate, and the CVD-SiC layer is in contact with the SiC substrate in the region without the glassy carbon layer The central portion of the substrate can be easily peeled from the SiC base material, and the peripheral portion can be made difficult to peel from the SiC base material. The ease of peeling of the SiC wafer from the single crystal-coated substrate can be easily controlled by appropriately setting the area and region where the SiC base material is exposed.

By appropriately forming a region without the glassy carbon layer on the silicon carbide composite substrate, for example, a region where the CVD-SiC layer is not in contact with the SiC substrate at the orientation flat or notch portion can be created. Can be peeled off.

Also, a SiC semiconductor can be obtained by dicing after forming a pattern on the ion-implanted layer of the single crystal-coated substrate. At this time, the CVD-SiC layer constituting the SiC semiconductor is easily peeled off because it is bonded to the SiC substrate via the glassy carbon layer.

The SiC semiconductor manufacturing method of the present invention includes the above-described SiC wafer manufacturing method and a semiconductor forming step, and the semiconductor forming step is after the heat treatment step and before the second peeling step. .

Since the SiC semiconductor is formed on the single crystal coated substrate and then separated, it is not necessary to handle a thin SiC wafer, and it can be made difficult to damage, and a thin CVD-SiC layer can be used as a part of the SiC semiconductor. The ON resistance of the semiconductor can be easily reduced.

Further, in the silicon carbide composite substrate of the present invention, a glassy carbon layer and a CVD-SiC layer are sequentially laminated on the surface of an SiC base material which is a disk having a marking on the edge.

In the silicon carbide composite substrate of the present invention, the CVD-SiC layer and the ion implantation layer, which will later become a SiC wafer, are handled while being bonded to the SiC base material together with the glassy carbon layer, so that they are not easily damaged during handling such as polishing. can do.

In order for a SiC semiconductor to function sufficiently, a pattern is formed in a certain direction from a SiC wafer and diced. The silicon carbide composite substrate and the single crystal SiC substrate have markings, and the direction of the single crystal SiC substrate is made to be the crystal orientation of the SiC wafer by joining the silicon carbide composite substrate and the single crystal SiC substrate in the same direction. The crystal orientation of the SiC wafer can be easily confirmed.

The silicon carbide composite substrate of the present invention is preferably in the following manner.
(6) The marking is an orientation flat or a notch.
In general semiconductor manufacturing apparatuses, semiconductor manufacturing processes such as pattern formability and dicing are performed by confirming crystal orientation by orientation flats or notches. For this reason, when the SiC wafer of this invention has an orientation flat or a notch, a SiC semiconductor can be manufactured using the semiconductor manufacturing apparatus which prevails widely.

(7) The thickness of the CVD-SiC layer is 50 to 1000 μm.
When the thickness of the CVD-SiC layer is 50 μm or more, sufficient mechanical strength can be imparted to the SiC semiconductor obtained from the SiC wafer. When the thickness of the CVD-SiC layer is 1000 μm or less, the ON resistance of the SiC semiconductor obtained from the SiC wafer can be reduced.

(8) The silicon carbide composite substrate has a region without a glassy carbon layer on a side wall or an edge thereof, and the CVD-SiC layer is in contact with the SiC substrate in the region without the glassy carbon layer.

An SiC wafer from which a SiC semiconductor is obtained by having a region without a glassy carbon layer on the side wall or edge of the silicon carbide composite substrate, and the CVD-SiC layer is in contact with the SiC substrate in the region without the glassy carbon layer The central portion of the substrate can be easily peeled from the SiC base material, and the peripheral portion can be made difficult to peel from the SiC base material. The ease of peeling of the SiC wafer from the single crystal-coated substrate can be easily controlled by appropriately setting the area and region where the SiC base material is exposed.

By appropriately forming a region without a glassy carbon layer on the silicon carbide composite substrate, for example, a region where the CVD-SiC layer and the SiC substrate are not in contact with each other at an orientation flat or a notch portion can be formed. It can be easily peeled off.

Also, a SiC semiconductor can be obtained by forming a pattern on the ion implantation layer as a single crystal-coated substrate with the SiC base material bonded and then dicing. At this time, the CVD-SiC layer constituting the SiC semiconductor is easily peeled off because it is bonded to the SiC substrate via the glassy carbon layer.

According to the present invention, since a thin SiC wafer can be handled in a state of being bonded to a SiC substrate, it can be made difficult to damage in the manufacturing process of the SiC wafer, and the obtained SiC wafer can be made thin. A SiC wafer having a small ON resistance can be obtained.

According to the present invention, since a thin SiC wafer can be handled in a state of being bonded to a SiC substrate, it can be made difficult to damage in the manufacturing process of the SiC semiconductor, and the obtained SiC semiconductor can be made thin. A SiC semiconductor having a small ON resistance can be obtained.

According to the silicon carbide composite substrate, which is a polycrystalline SiC substrate of the present invention, a thin SiC wafer can be handled in a state of being bonded to an SiC base material, so that it can be made difficult to be damaged in the manufacturing process of the SiC wafer. Thus, the obtained SiC wafer can be thinned, and a SiC wafer having a small ON resistance can be obtained.

FIG. 1 shows a manufacturing process of the SiC wafer manufacturing method of the present invention, where S1 is a bonding process, S2 is a first peeling process, and S3 is a second peeling process. FIG. 2 is one embodiment of a silicon carbide composite substrate described in the production method of the present invention, in which (a) has an orientation flat and (b) has a notch. FIG. 3 is one embodiment of a silicon carbide composite substrate described in the production method of the present invention, wherein (a) has a region having no glassy carbon layer at the edge, and (b) is glassy on the side wall. This is a modified example having a region without a carbon layer. FIG. 4 shows the observation results of warping for each of the three silicon carbide composite substrate samples, (a) is a sample using the first graphite substrate as the substrate, and (b) is the second substrate as the substrate. A sample using a graphite substrate, (c) shows the results of each sample using the SiC substrate 1 of the present embodiment as the substrate.

The SiC wafer manufacturing method of the present invention includes a silicon carbide composite substrate having a glassy carbon layer on the surface of a SiC substrate and a CVD-SiC layer on the glassy carbon layer, and ions in which hydrogen ions are implanted on the surface. A step of preparing a single crystal SiC substrate having an implantation layer, a bonding step of bonding a CVD-SiC layer of the silicon carbide composite substrate and an ion implantation layer of the single crystal SiC substrate, and obtaining a bonded body; And the ion-implanted layer is peeled from the single crystal SiC substrate to obtain a single crystal coated substrate, and the glassy carbon layer and the CVD-SiC layer of the single crystal coated substrate are peeled off to form SiC. A second peeling step for obtaining a wafer.

By implanting hydrogen into a single crystal SiC substrate, hydrogen ions can reach a depth corresponding to the incident energy. When a single crystal substrate into which hydrogen ions are implanted is heated, hydrogen collects in implantation defects formed at the time of ion implantation, and the crystal bond can be cut. Since the single crystal SiC substrate is bonded to the CVD-SiC layer, the ion-implanted surface can move to the CVD-SiC layer side in the first peeling step.

The single crystal SiC substrate into which hydrogen ions are implanted is brittle while maintaining the surface of the single crystal, and thus can be moved to the CVD-SiC layer while maintaining the single crystal. Since the single-crystal SiC layer is formed on the surface of the CVD-SiC layer after the first peeling step, it is possible to provide an SiC wafer that can be suitably used for an SiC semiconductor by further epitaxially growing the SiC layer. it can.

The bonding step of bonding the CVD-SiC layer and the single crystal SiC substrate can be performed as follows.

Both the CVD-SiC layer and the single crystal SiC substrate are mirror-polished. The mirror-polished surfaces can be brought into close contact with each other to form a joint surface without a gap.

The CVD-SiC layer and the single crystal SiC substrate are preferably cleaned in advance. The cleaning method is not particularly limited, but it is preferable to use, for example, a chemical such as an acid and pure water. For example, as a cleaning method, RCA cleaning widely used in semiconductor cleaning can be used. RCA cleaning is a cleaning method called SC1, which is a cleaning method using a combination of ammonia, hydrogen peroxide and water, and a cleaning method called SC2, which is a combination of hydrochloric acid, hydrogen peroxide and water. It is mainly used to remove particles and organic contaminants, and in SC2, it is used to remove metal contaminants.

It is preferable to perform plasma activation treatment on at least one of the CVD-SiC layer and the single crystal SiC substrate. The plasma-activated surface is easy to bond, and the CVD-SiC layer and the single crystal SiC substrate can be bonded more firmly.
The first peeling step can be peeled by heating the joined body. The ion-implanted layer is fragile because hydrogen ions penetrate inside. When the bonded body is heated, the ion-implanted layer portion that has become brittle due to a difference in thermal expansion between the single crystal SiC substrate and the silicon carbide composite substrate peels off. A single crystal coated substrate is obtained in which about 1 to 10 μm of the surface of the ion implantation layer is attached to the CVD-SiC layer, and a part of the ion implantation layer is attached to the CVD-SiC layer of the silicon carbide composite substrate. That is, the ion-implanted layer is exposed on either side of the peeled surface.

The first peeling step is aimed at separation of the ion implantation layer due to the difference in thermal expansion, so that it can be separated by heating to a temperature of 200 to 1000 ° C., for example, without being involved in a chemical reaction.

The silicon carbide composite substrate is a disk and has a marking indicating the direction at the edge thereof, and the single crystal SiC substrate is a disk and has a marking indicating the direction at the edge, and the bonding step includes the silicon carbide composite The substrate and the single crystal SiC substrate are joined together with markings indicating directions.

In order for a SiC semiconductor to function sufficiently, a pattern is formed in a certain direction from a SiC wafer and diced. The silicon carbide composite substrate and the single crystal SiC substrate are discs each having a marking indicating a direction, and the silicon carbide composite substrate and the single crystal SiC substrate are joined together with the marking indicating the direction. The direction can be reflected in the crystal orientation of the SiC wafer, and the crystal orientation of the SiC wafer can be easily confirmed.

The marking is preferably an orientation flat or a notch.
In a general semiconductor manufacturing apparatus, the crystal orientation is confirmed by an orientation flat or notch, and semiconductor formation and dicing are performed. For this reason, when the SiC wafer of this invention has an orientation flat or a notch, a SiC semiconductor can be manufactured using the semiconductor manufacturing apparatus which prevails widely.

The SiC wafer manufacturing method preferably further includes a heat treatment step after the first peeling step. The ion-implanted layer and the CVD-SiC layer can be diffused and bonded more firmly to each other by a heat treatment process.

The temperature of the heat treatment step is not particularly limited, but is, for example, 1000 to 2000 ° C. When the temperature is 1000 ° C. or higher, the bonding between the ion implantation layer and the CVD-SiC layer can be further strengthened, and when the temperature is 2000 ° C. or lower, crystal defects are less likely to occur in the ion implantation layer that is single crystal SiC. The heating temperature in the heat treatment step is preferably higher than the heating temperature in the first peeling step in order to promote the bonding between the polycrystalline CVD-SiC layer and the single crystal ion implantation layer. Bonding can be further strengthened by heating to a temperature higher than the heating temperature in the first peeling step.

The heat treatment step may be either before the second peeling step or after the second peeling step, and is not particularly limited, but is preferably before the second peeling step. When there is a heat treatment step before the second peeling step, it is possible to make it difficult for warpage to occur in the heat treatment step.

The thickness of the CVD-SiC layer is preferably 50 to 1000 μm.
When the thickness of the CVD-SiC layer is 50 μm or more, sufficient mechanical strength can be imparted to the SiC semiconductor obtained from the SiC wafer. When the thickness of the CVD-SiC layer is 1000 μm or less, the ON resistance of the SiC semiconductor obtained from the SiC wafer can be reduced.

A more desirable CVD-SiC layer thickness is 100 to 500 μm. When the thickness of the CVD-SiC layer is 100 μm or more, the strength of the SiC semiconductor obtained from the SiC wafer can be further increased. When the thickness of the CVD-SiC layer is 500 μm or less, the ON resistance of the SiC semiconductor obtained from the SiC wafer can be further reduced.

The method for producing the SiC wafer has a region without a glassy carbon layer on a side wall or an edge of the silicon carbide composite substrate, and the CVD-SiC layer is in contact with the SiC substrate in the region without the glassy carbon layer. It is preferable.

In this way, by forming a silicon carbide composite substrate by exposing a part of the SiC base material, it is possible to prevent the SiC base material from being separated from the SiC wafer during the manufacturing process of the SiC wafer.

Also, before the second peeling step for separating the SiC wafer, a SiC semiconductor can be formed on the single crystal. Specifically, a SiC semiconductor can be obtained by forming a SiC semiconductor on a single crystal of a single crystal-coated substrate and then dicing. At this time, the CVD-SiC layer constituting the SiC semiconductor is easily peeled off because it is bonded to the SiC substrate via the glassy carbon layer.

The glassy carbon constituting the glassy carbon layer can be obtained by carbonizing a solvent containing a resin such as a phenol resin, a furan resin, or an imide resin. Since it is a solvent, the solvent volatilizes during the carbonization treatment after coating on the substrate to form a glassy carbon layer. Therefore, the glassy carbon layer is thin without causing cracks. Further, since SiC used for the base material has little variation in characteristics, the flatness of the glassy carbon layer forming surface is good, and the flatness of the thinly formed glassy carbon layer is also good. The thickness of the glassy carbon layer is preferably set to 0.1 to 50 μm, more preferably 0.3 to 10 μm, and particularly preferably 0.5 to 5 μm. When the thickness of the glassy carbon layer is smaller than 0.1 μm, the surface state of the glassy carbon layer is greatly affected by the surface state (uneven surface) of the substrate. Therefore, the thickness of the CVD-SiC layer must be increased to such an extent that it is not affected by the surface state. If the surface state is poor, the mirror polishing cannot be performed flatly. If the thickness exceeds 50 μm, the effect of curing shrinkage and linear expansion difference due to the thickness of the glassy carbon layer is increased. Therefore, stress due to curing shrinkage and linear expansion difference is applied to the CVD-SiC layer. -The SiC layer is destroyed.

There are various methods for producing a glassy carbon layer, and the following methods are available. After diluting the raw material (thermosetting resin such as polyimide or phenolic resin) with a dilute solution (dimethylacetamide), apply the solution on the substrate by spin coating, spraying, or dipping, and then at a temperature of 120 ° C. for 10 minutes. dry. Thereafter, baking is performed for 1 hour at a temperature of 1000 ° C. under a vacuum environment of 0.15 Torr or less.

The formation of the SiC semiconductor is appropriately selected according to the desired SiC semiconductor, such as pattern shape, oxidation, diffusion, CVD, ion implantation, CMP, electrode shape, etching, pattern shape, electrode shape, and photoresist coating. can do.

(Example 1)
Next, Example 1 according to the present invention will be described. FIG. 1 shows a manufacturing process of the SiC wafer manufacturing method of the present invention, where S1 is a bonding process, S2 is a first peeling process, and S3 is a second peeling process. FIG. 2 is one embodiment of a silicon carbide composite substrate described in the manufacturing method of the present invention, in which (a) has an orientation flat 8a, and (b) is a notch (notch) 8b which is a modification thereof. have. FIG. 3 is one embodiment of a silicon carbide composite substrate described in the production method of the present invention, wherein (a) has a region having no glassy carbon layer at the edge, and (b) is glass on the side wall. It is a modification which has an area | region without a carbon-like carbon layer. FIG. 3A shows a glassy carbon layer having a diameter smaller than that of the SiC substrate, and the SiC substrate and the CVD-SiC layer are in contact with each other outside the glassy carbon layer. FIG. 3B shows a glassy carbon layer having the same diameter as that of the SiC substrate, but no glassy carbon layer is formed on the side surface of the SiC substrate. And the CVD-SiC layer are in contact with each other.

<Joint process>
SiC base material 1 of silicon carbide composite substrate 6 has a disk shape with a diameter of 150 mm and a thickness of 2 mm, and is provided with an orientation flat 8a serving as a marking at the edge. The length of the side of the orientation flat 8a is 2 cm. On the surface of SiC substrate 1, glassy carbon layer 2 having a thickness of 40 μm and a diameter of 149 mm is provided. That is, the edge 0.5 mm has no glassy carbon layer, and the SiC substrate is in contact with the CVD-SiC layer 3. That is, the outside of the glassy carbon layer 2 is a region 9 without a glassy carbon layer. A CVD-SiC layer 3 having a thickness of 500 μm is provided on the glassy carbon layer. That is, the edge 0.5 mm of the CVD-SiC layer 3 is directly formed on the SiC substrate without interposing a glassy carbon layer. After the surface of the CVD-SiC layer 3 is polished, RCA cleaning is performed. The RCA cleaning can be performed with a commercially available RCA cleaning solution.

Next, a single crystal SiC substrate 4 having an orientation flat is prepared, and hydrogen ions are implanted into one surface thereof. By implanting hydrogen ions, an ion implantation layer 4a is formed. After implanting hydrogen ions, RCA cleaning is performed. The RCA cleaning can be performed with a commercially available RCA cleaning solution. The portion where hydrogen ions are not implanted is an ion non-implanted layer 4d.

Next, the ion-implanted layer 4a of the single crystal SiC substrate 4 and the CVD-SiC layer 3 of the silicon carbide composite substrate are brought into contact with each other and bonded to obtain a bonded body 7. There are no particular limitations on the temperature and pressure for pressure bonding.

<First peeling step>
The obtained bonded body 7 is heated to be separated by the ion implantation layer 4a. Since the ion implantation layer 4a becomes brittle when hydrogen ions are implanted, the surface portion of the ion implantation layer 4a can be peeled off. In FIG. 1, the ion implantation layer left on the single crystal SiC substrate side is 4c, and the ion implantation layer moved to the silicon carbide composite substrate side is 4b. The heating temperature is not particularly limited, but is 400 ° C. The joined body is separated at the ion implantation layer portion due to a difference in thermal expansion generated inside the joined body.

<Heat treatment process>
The single crystal coated substrate 5 composed of the SiC substrate 1, the glassy carbon layer 2, the CVD-SiC layer 3, and the ion implantation layer 4b is heat-treated. The heat treatment is performed at 1200 ° C. for 10 minutes. By this treatment, the bonding between the CVD-SiC layer 3 and the ion implantation layer 4b can be strengthened.

<Second peeling step>
The single crystal SiC wafer is peeled from the orientation flat portion of the heat-treated single crystal coated substrate. The orientation flat portion can be easily peeled off because the glassy carbon layer 2 is present between the SiC substrate 1 and the CVD-SiC layer 3.

(Example 2)
Next, a second embodiment according to the present invention will be described.
Example 2 is a manufacturing method of a SiC semiconductor, and includes a semiconductor formation process between the heat treatment process and the second peeling process of Example 1.

The process up to the first peeling step is performed in the same manner as in Example 1 to obtain a single crystal-coated substrate, and then an SiC single crystal is epitaxially grown to form an SiC epitaxial layer. Furthermore, after obtaining the desired SiC semiconductor by pattern formability, oxidation, diffusion, CVD, ion implantation, CMP, electrode formability, etching, pattern formability, electrode formability, and photoresist coating, the SiC semiconductor is formed by dicing. Disconnect. Since the cut SiC semiconductor is in contact with the SiC substrate 1 via the glassy carbon layer 2, it can be easily separated between the glassy carbon layer 2 and the CVD-SiC layer 3.

FIG. 4 shows the observation results of warpage for each of the three silicon carbide composite substrate samples. 4A is a sample using the first graphite substrate as the substrate, FIG. 4B is a sample using the second graphite substrate as the substrate, and FIG. 4C is the embodiment as the substrate. The result of each sample using this SiC base material 1 is shown.

In this observation, the height of the warp (Z direction) from the height of the surface at the reference point within a range of 50 mm on the left and right (X or Y direction) from the predetermined reference point was measured. For each sample, warp 1 before forming the glassy carbon layer on the substrate (warp of the substrate), warp 2 after forming the glassy carbon layer on the substrate, and further after forming the CVD-SiC layer Warp 3 (warp of the silicon carbide composite substrate) was measured and plotted.

From the results of FIGS. 4A and 4B, the sample using the first graphite substrate as the substrate is more warped (warped) as the silicon carbide composite substrate than the sample using the second graphite substrate. It is understood that 3) is small. That is, at a position 50 mm from the reference point, the warp of the sample using the second graphite base material (silicon carbide composite substrate) is about 400 μm, whereas the sample using the first graphite base material (silicon carbide composite substrate) The warpage is suppressed to 10 μm, and it can be seen that the characteristics greatly change depending on the graphite member. This is a phenomenon caused by variations in characteristics such as thermal expansion of the graphite member because it is difficult to control crystal growth in the manufacturing process of the graphite member. Therefore, when a graphite member is selected as the base material, a design that takes into account large variations in characteristics is required. As a result, the thickness of the glassy carbon layer or the CVD-SiC layer must be increased, resulting in cost and This leads to a decrease in production efficiency.

Moreover, as shown in FIG.4 (c), by using the SiC base material 1 of this embodiment as a base material, the curvature (warpage 3) as a silicon carbide composite substrate is the same as that of a 1st graphite base material. It is suppressed to 10 μm or less. Furthermore, the warp (warp 2) after forming the glassy carbon layer on the base material before forming the CVD-SiC layer is also suppressed to 10 μm, and compared to the warp 2 of the sample of the first graphite member, It is kept small.

This is because, in the sample using the SiC base material 1, the difference in thermal expansion coefficient between the SiC base material 1 and the CVD-SiC layer 3 having the same material is small, and the SiC base material 1 is hard and has high bending elasticity. Thus, it is thought that the warpage is suppressed. In addition, SiC has a smaller variation in characteristics such as thermal expansion due to crystals and is easier to control than a graphite member, so that the design is easy and the CVD-SiC layer can be made thin.

In the SiC wafer manufacturing method of the present disclosure, since a glassy carbon layer having a small surface roughness is used for the silicon carbide composite substrate, the bonding strength with the CVD-SiC layer formed thereon is strong. Become. Further, the warp of the silicon carbide composite substrate is small. As a result, in the manufacturing process of the SiC wafer, the ion implantation layer can be peeled from the single crystal SiC substrate, and the first peeling process for obtaining the single crystal coated substrate can be stably performed, thereby improving the manufacturing efficiency of the SiC wafer. It becomes possible.

This application is based on Japanese Patent Application No. 2014-140564 filed on July 8, 2014, the contents of which are incorporated herein by reference.

DESCRIPTION OF SYMBOLS 1 SiC base material 2 Glassy carbon layer 3 CVD-SiC layer 4 Single

crystal SiC substrate

4a, 4b, 4c Ion implantation layer 5 Single crystal coated substrate 6 Silicon carbide composite substrate 7 Joined body 8a Orientation flat 8b Notch
9 Area without glassy carbon layer

Claims

A silicon carbide composite substrate having a glassy carbon layer on the surface of the SiC substrate and a CVD-SiC layer on the glassy carbon layer, and a single crystal SiC substrate having an ion implantation layer in which hydrogen ions are implanted on the surface. A preparation process;
A bonding step of bonding a CVD-SiC layer of the silicon carbide composite substrate and an ion implantation layer of the single crystal SiC substrate to obtain a bonded body;
Heating the joined body, peeling the ion-implanted layer from the single-crystal SiC substrate, and obtaining a single-crystal-coated substrate;
A second peeling step of peeling the glassy carbon layer and the CVD-SiC layer of the single crystal-coated substrate to obtain a SiC wafer;
A method for producing a SiC wafer comprising:
The silicon carbide composite substrate is a disc and has a marking indicating a direction on the edge thereof, and the single crystal SiC substrate is a disc and has a marking indicating a direction on the edge,
2. The method of manufacturing an SiC wafer according to claim 1, wherein in the bonding step, the silicon carbide composite substrate and the single crystal SiC substrate are bonded together with markings indicating directions.
3. The SiC wafer manufacturing method according to claim 2, wherein the marking is an orientation flat or a notch.
4. The SiC wafer manufacturing method according to claim 1, further comprising a heat treatment step after the first peeling step.
The method for producing an SiC wafer according to any one of claims 1 to 4, wherein the CVD-SiC layer has a thickness of 50 to 1000 µm.
2. The silicon carbide composite substrate has a region without a glassy carbon layer on a side wall or an edge thereof, and the CVD-SiC layer is in contact with the SiC substrate in the region without the glassy carbon layer. The method for producing an SiC wafer according to any one of claims 1 to 5.
5. A SiC semiconductor manufacturing method comprising the SiC wafer manufacturing method according to claim 4 and a semiconductor forming step, wherein the semiconductor forming step is performed after the heat treatment step and before the second peeling step. Semiconductor manufacturing method.
A silicon carbide composite substrate, wherein a glassy carbon layer and a CVD-SiC layer are sequentially laminated on the surface of a SiC base material which is a disk having a marking on an edge.
The silicon carbide composite substrate according to claim 8, wherein the marking is an orientation flat or a notch.
10. The silicon carbide composite substrate according to claim 8, wherein a thickness of the CVD-SiC layer is 50 to 1000 μm.
9. The silicon carbide composite substrate has a region without a glassy carbon layer on a side wall or an edge thereof, and the CVD-SiC layer is in contact with the SiC substrate in the region without the glassy carbon layer. 11. The silicon carbide composite substrate according to any one of 1 to 10.