CN115842790A - Service data flow control method applied to PCle equipment - Google Patents

Service data flow control method applied to PCle equipment Download PDF

Info

Publication number
CN115842790A
CN115842790A CN202211701918.XA CN202211701918A CN115842790A CN 115842790 A CN115842790 A CN 115842790A CN 202211701918 A CN202211701918 A CN 202211701918A CN 115842790 A CN115842790 A CN 115842790A
Authority
CN
China
Prior art keywords
descriptor
module
data
pcle
flow control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202211701918.XA
Other languages
Chinese (zh)
Other versions
CN115842790B (en
Inventor
臧云利
朱彤
李振
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shandong Duofang Semiconductor Co ltd
Sanwei Xin'an Technology Co ltd
Original Assignee
Shandong Duofang Semiconductor Co ltd
Sanwei Xin'an Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shandong Duofang Semiconductor Co ltd, Sanwei Xin'an Technology Co ltd filed Critical Shandong Duofang Semiconductor Co ltd
Priority to CN202211701918.XA priority Critical patent/CN115842790B/en
Publication of CN115842790A publication Critical patent/CN115842790A/en
Application granted granted Critical
Publication of CN115842790B publication Critical patent/CN115842790B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

The invention relates to a business data flow control method applied to PCle equipment, which is realized based on a host terminal and the PCle equipment terminal and comprises the following steps: when a host producer descriptor pointer is updated, a PCle equipment side acquires and combines a current consumer descriptor pointer and the free space of a service processing module to obtain a data entry to be acquired; and the PCle equipment end sends Mwr request to the host end, acquires and processes corresponding producer information from the host end, and updates consumer descriptor pointers of the host end and the PCle equipment end. The flow control method disclosed by the invention can convert the I/O operation of the host end into the memory operation, thereby reducing the I/O operation in data transmission and reducing the time consumption on a data transmission path; and, the idle space of combining the data processing module carries on the data transmission, can prevent the data from losing effectively, and can process a plurality of tasks at the same time, raise the transmission efficiency.

Description

Service data flow control method applied to PCle equipment
Technical Field
The present invention relates to the field of flow control technology, and more particularly, to a method for controlling traffic data flow applied to a PCle device.
Background
In the PCIe system, the processor host is connected to the PCIe device side based on the root node device rc in the root complex mode. And the Host and the PCIe device end carry out high-speed communication, and flow control is needed to avoid data coverage or data loss caused by resource problems of data.
Generally, in a high-performance application scenario, a PCIe device side assumes the responsibility of hardware acceleration application, in such application, data communication is mostly issued and returned by using a queue mechanism, and when a host-issued computation task bandwidth is greater than a PCIe device side processing bandwidth, to ensure reliable data transmission, host-side software is required to participate in flow control, which currently implements the following methods:
1) The host side software issues a read state mode through the RC node through IO operation to obtain the internal working state of the PCIe equipment;
2) The PCIe device side informs the host side through an MSI interruption mode, the mode has functional limitation, and in order to ensure that data communication can reliably obtain comprehensive queue state data, host side software can repeat the operation of the step 1) to confirm state information;
and the host side software reads the working state of the queue of the PCIe device end to be IO operation, and issues a TLP read request (MRd) to a response (CplD) to the PCIe device end through the RC node in the whole process, taking PCIe gen3x8 as an example, the whole process usually takes 700 to 1000nS, and the process mainly consumes time in path delay. In addition, in the transmission service of small data packets (defined as 1Kbyte and below), since the PCIe communication transmission time and the hardware acceleration function processing time of the small data packets are shortened, the transmission time in the acquisition state cannot be ignored in the whole system operation process, and when the data packets are smaller, the transmission performance may be affected.
Therefore, how to provide a new flow control method to overcome the above-mentioned drawbacks is a problem that needs to be solved by those skilled in the art.
It is also noted that the information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art known to a person skilled in the art.
Disclosure of Invention
In view of this, the invention provides a chip-based method for controlling traffic data flow of PCIe devices, and by setting the flow control chip disclosed in the invention at the PCIe device end, PCIe devices can actively write a request (Mwr) to the RC side to complete host-end memory writing of state information such as queues, and finally, the effect of improving the efficiency of flow control and reducing the occupation of host-end CPUs is achieved.
In order to achieve the purpose, the invention adopts the following technical scheme:
a business data flow control method applied to PCle equipment is realized based on a host end and the PCle equipment end, and the method comprises the following steps:
when the host end producer descriptor pointer is updated, writing the producer descriptor pointer into the PCle equipment end;
the PCle device end receives the producer descriptor pointer and acquires the current consumer descriptor pointer of the PCle device end and the free space of the service processing module of the PCle device end,
obtaining a current pending data entry according to the producer descriptor pointer and the consumer descriptor pointer,
obtaining the data items to be obtained according to the obtained data items to be processed and the free space of the service processing module,
according to the data entry to be obtained, the PCle equipment end sends Mwr requests to the host end, corresponding producer information is obtained from the host end, and the Mwr requests carry descriptor addresses consistent with the consumer descriptor pointers; and after the corresponding producer information is acquired, sending the producer information to the service processing module for processing, and updating consumer descriptor pointers of the host end and the PCle equipment end according to the data entry to be acquired.
Preferably, the control method is implemented based on a chip, and the chip is arranged at the PCLe device end.
Preferably, the chip includes a PCIE interface module, and is connected to the PCLe device end through the PCIE interface module.
Preferably, the chip includes a service processing module and a flow control engine, and the service processing module is configured to process the task issued by the host; and the flow control engine is used for starting when the host end producer descriptor pointer is updated and controlling the flow according to the free space of the service processing module.
Preferably, before performing flow control, the host configures a memory space including a memory space for read-write access of the chip, where the memory space includes a descriptor queue memory space and a consumer pointer information memory space.
Preferably, the chip further includes a descriptor cache module and a data cache module, the descriptor cache module is configured to store a base address of the memory space of the descriptor queue and a base address of the memory space of the consumer pointer information, and is provided with a producer descriptor pointer register, and the data cache module corresponds to the descriptor cache module and is configured to store data information corresponding to the consumer pointer.
Preferably, the descriptor caching module is further configured to, when a host-side producer descriptor pointer is updated, obtain a data entry to be processed according to the producer descriptor pointer and the stored consumer pointer information.
Preferably, the flow control engine comprises a flow control preprocessing module, a flow control information calculating module, a flow post-processing module and a MWr sending request module,
the flow control preprocessing module receives the data entry to be processed, the consumer descriptor pointer and the corresponding data information output by the data caching module, which are acquired by the descriptor caching module, and outputs the data entry to the flow control information computing module after merging and latching;
the flow control information calculation module calculates the data items to be acquired by combining with the free space of the service processing module, and sends the calculated data items to be acquired to the flow post-processing module;
the flow post-processing module reads the address of the data entry to be acquired from the descriptor cache module and sends the address to the MWr sending request module;
the MWr sending request module sends a Mwr request to the host end according to the address of the data entry to be obtained, and obtains a corresponding producer message from the host end.
Preferably, the flow engine further includes a descriptor status management module, configured to maintain read-write pointers and descriptor status information of other service function modules at the host end and the PCle device end;
preferably, the traffic engine further includes a configuration module, configured to store configuration information of the host.
Compared with the prior art, the technical scheme has the advantages that the method for controlling the service data flow applied to the PCle equipment can convert IO operation of host side software into memory operation, so that I/O operation in data transmission is reduced, and time consumption on a data transmission path is reduced;
and, the data transmission is carried out in combination with the free space of the data processing module, so that the data loss can be effectively prevented, and a plurality of tasks can be processed simultaneously, thereby improving the transmission efficiency.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flow chart of flow control provided by the present invention;
FIG. 2 is a schematic diagram of a chip structure provided by the present invention;
FIG. 3 is a schematic diagram of a fluidic engine architecture provided by the present invention;
fig. 4 is a flow control process diagram provided by the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses a business data flow control method applied to PCle equipment, which aims to ensure normal data transmission and reduce I/O operation, further reduce time consumption on a path caused by the operation, simultaneously process a plurality of tasks and improve the control efficiency of flow waves.
Specifically, the method is implemented based on a host terminal and a PCle device terminal, and is implemented by the following steps:
when the host end producer descriptor pointer is updated, writing the producer descriptor pointer into a PCle equipment end;
the PCle device end receives the producer descriptor pointer and obtains the consumer descriptor pointer of the current PCle device end and the free space of the PCle end service processing module,
obtaining the current data entry to be processed according to the producer descriptor pointer and the consumer descriptor pointer,
obtaining the data items to be acquired according to the acquired data items to be processed and the free space of the service processing module,
according to the data entry to be obtained, the PCle equipment end sends Mwr requests to the host end, corresponding producer information is obtained from the host end, and Mwr requests to carry descriptor addresses consistent with consumer descriptor pointers; and after acquiring corresponding producer information, sending the producer information to a service processing module for processing, and updating consumer descriptor pointers of a host end and a PCle equipment end according to the data items to be acquired.
In one embodiment, the data entries to be processed are: the difference of the producer descriptor pointer and the consumer descriptor pointer;
obtaining a data item to be obtained according to the obtained data item to be processed and the free space of the service processing module, wherein the process is to compare the obtained data item to be processed with the free space n _ free of the service processing module, and when the obtained data item to be processed is less than or equal to the free space n _ free of the service processing module, the data item obtained from the host is the data item to be processed, namely Pro-device Ptr-custom Ptr; and when the acquired data items to be processed are larger than the free space n _ free of the service processing module, acquiring the number of the data items from the host end as n free. In one embodiment, the flow control process is detailed in fig. 1 and includes:
s1, monitoring whether the product Ptr is updated or not, if not, continuing to monitor, and if so, executing S2;
s2, obtaining the current CustomerPtr;
s3, acquiring an idle state n _ free of the data processing module;
s4, comparing the sizes of the ProducterPtr-OustomerPtr and n _ free,
s5, if the ProducterPtr-OustomerPtr is greater than n _ free, acquiring the number of the data items from the host end as n _ free;
s6, if the ProducterPtr-OustomerPtr is less than or equal to n _ free, acquiring the data item number from the host section as Pro duct Ptr-custom mer Ptr;
s7, sending a Mwr request by the flow control post-processing packet, and synchronizing the local and host end CustomerPtr;
s8, starting the Mwr request sending of the pcie.
The method disclosed by the invention can accurately acquire the data items to be processed based on the producer descriptor pointer and the consumer descriptor pointer, can judge the number of the data items which can be processed by the PCle at one time by combining the free space of the service processing module, and carries out WMr request and data transportation according to the number of the data items, thereby not only avoiding the data from being covered and lost, but also actively judging and asking for the data through the PCle terminal without occupying the memory of a CPU.
On the other hand, the invention also provides a method for controlling the flow of the business data of the PCIe equipment based on the chip, namely, the flow control process is realized through the chip.
In an embodiment, the PCIe device side is provided with a chip 1, as shown in fig. 2, the chip 1 includes a PCIe interface IP module 2, and the PCIe interface IP module 2 is connected to the PCIe device side for communication;
secondly, the chip comprises a service processing module 5 and a flow control engine 3, wherein the service processing module 5 is used for processing a task issued by a host end; and the flow control engine 3 is used for starting when the host end producer descriptor pointer is updated, and controlling the flow according to the free space of the service processing module 5.
Before flow control, the system is powered on, enumeration is performed on the EP peripheral by a host end, and then relevant configuration is performed, including a memory space for which a chip can read and write access is applied, that is, a memory space in a DDR for which a chip can read and write access is applied, where DDR is a memory name, that is, a double-rate synchronous dynamic random access memory, which is one of memories. Generally, a chip cannot access all spaces of a memory, and therefore, a host end needs to be configured and applied in advance so as to facilitate accurate access of the chip.
The applied memory space comprises a descriptor queue memory space and a queue consumer pointer information memory space; the base address of the descriptor queue memory space and the base address of the queue consumer pointer information memory space are written into a register corresponding to the PCIe device end at one time through I/O operation by the host end; in the invention, the corresponding register is a descriptor caching module;
that is to say, the chip further comprises a descriptor caching module 6 and a data caching module 4, wherein the descriptor caching module 6 is used for storing a base address of a memory space of a descriptor queue and a base address of a memory space of queue consumer pointer information, and is provided with a producer descriptor pointer register, and when a Host producer descriptor is updated, the producer descriptor is written into the producer descriptor register through an I/O operation. The data caching module 4 corresponds to the descriptor caching module 6, and is configured to store data information corresponding to the consumer pointer, where the data information includes a length of the data.
In one embodiment, after the PCle device has the consumer pointer, the memory space corresponding to the consumer pointer on the host side is initialized to zero by Mwr operation;
meanwhile, a producer pointer designed in advance at the PCle equipment side is initialized to zero through the I/O operation at the host side.
In addition, the descriptor caching module 6 is further configured to, when the host-side producer descriptor pointer is updated, obtain a to-be-processed data entry according to the producer descriptor pointer and the stored queue consumer pointer information.
Further, the flow control engine 3 performs flow control according to the data entry to be processed, wherein the flow control engine 3 includes a flow control preprocessing module, a flow control information calculating module, a flow post-processing module, and a Mwr sending request module, as shown in fig. 3, specifically,
the flow control preprocessing module is used for receiving the data items to be processed, the consumer descriptor pointer and the corresponding data information output by the data caching module, which are acquired by the descriptor caching module, merging and latching the data items and the corresponding data information, and outputting the merged data information to the flow control information calculating module;
the flow control information calculation module calculates data items to be acquired by combining with the free space of the service processing module, and sends the calculated data items to be acquired to the flow post-processing module;
the flow post-processing module reads the address of the data entry to be acquired from the descriptor cache module and sends the address to the Mwr sending request module;
mwr the request module sends Mwr request to host according to the address of the data entry to be obtained, and obtains the corresponding producer message from host.
In general, a descriptor management module manages pointers of producers and consumers, calculates data space occupied by the data to be sent, namely data items to be processed, through descriptor information, outputs the descriptor information in real time, a data cache management module outputs cache information in real time, the two parts of information are provided for a flow control preprocessing module together, the module combines and latches related descriptor and data cache space information and outputs the combined and latched data to a flow control calculation processing module, the module generates flow control data through descriptor cache state calculation according to the size of a configured safety area, namely the free space of a service processing module, and sends the flow control data to a post-processing module, and the module reads destination address information from the configuration information, combines the destination address information and sends the combined destination address information to a Mwr sending module. At this point, one flow control processing cycle is completed.
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, the present invention is described in further detail with reference to fig. 4; the sequence numbers in fig. 4 represent the order of data processing steps;
firstly, step 1, after the host works normally, the host writes the effective load, namely the data to be processed, into the host buffer, and the information of the effective load buffer, including the original address, the destination address and the length information, forms a producer descriptor (producer ptr);
step 2, the host writes the producer descriptor pointer into a producer pointer register corresponding to the PCIE device through IO operation;
step 3, after the PCIe device receives the producer pointer (ProducterPtr), the flow processing engine is started to obtain the current consumer pointer (CustormerPtr);
step 4, the traffic processing engine acquires an idle statistical state in the data processing module, and calculates producer information required to be acquired from the host by combining the current consumer pointer (CustomerPtr) and producer pointer (ProducerPtr) states in the PCIe device;
step 5, the flow processing engine sends the calculated number of the items of the producer information to be acquired to a post-processing module;
step 6, the post-processing module initiates a Mwr request according to the obtained producer message, and obtains corresponding data from a host end;
step 7, the post-processing module sends the acquired data to the data processing module for data processing;
and 8, simultaneously, the consumer pointer Custormer Ptr) is updated according to the number of the acquired producer information entries, and the current consumer pointer Custormer Ptr) of the PCIe device is synchronously updated to a consumer pointer register corresponding to the host end by the post-processing module.
The flow control method based on the chip can detect and calculate relevant flow control information in time through the descriptor cache module and the data cache module, and actively sends the flow control information to the host memory area in a Mwr mode. The method is superior to the timeliness of a query mode, and the whole process is shorter than the time for querying the flow control information of the EP peripheral by host once. The method is equivalent to the timeliness of the conventional interrupt method, but the conventional interrupt method necessarily needs to be accompanied by one IO read operation. The scheme of the invention can effectively avoid I/O operation, and has more advantages in time consumption.
In addition, in an embodiment, the traffic engine further includes a descriptor status management module, configured to maintain state information of the descriptor and read-write pointers of the host side and other service function modules of the PCle side.
In one embodiment, the traffic engine further comprises a configuration module for configuring all modules with relevant information.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed in the embodiment corresponds to the method disclosed in the embodiment, so that the description is simple, and the relevant points can be referred to the description of the method part.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A business data flow control method applied to PCle equipment is characterized by being realized based on a host end and the PCle equipment end, and the method comprises the following steps:
when the host end producer descriptor pointer is updated, writing the producer descriptor pointer into the PCle equipment end;
the PCle device end receives the producer descriptor pointer and acquires the current consumer descriptor pointer of the PCle device end and the free space of the service processing module of the PCle device end,
obtaining a current pending data entry according to the producer descriptor pointer and the consumer descriptor pointer,
obtaining the data item to be acquired according to the data item to be processed and the free space of the service processing module,
according to the data entry to be obtained, the PCle equipment end sends Mwr requests to the host end, corresponding producer information is obtained from the host end, and the Mwr requests carry descriptor addresses consistent with the consumer descriptor pointer; and after the corresponding producer information is acquired, sending the producer information to the service processing module for processing, and updating consumer descriptor pointers of the host end and the PCle equipment end according to the data entry to be acquired.
2. The method as claimed in claim 1, wherein the control method is implemented based on a chip, and the chip is disposed at the PCle device side.
3. The method as claimed in claim 2, wherein the chip includes a PCIe interface module, and the PCIe interface module is connected to the PCle device side.
4. The method for controlling the traffic data flow applied to the PCle device according to claim 2, wherein the chip includes a traffic processing module and a flow control engine, the traffic processing module is configured to process the task issued by the host; and the flow control engine is used for starting when the host end producer descriptor pointer is updated and controlling flow according to the free space of the service processing module.
5. The method as claimed in claim 4, wherein before performing flow control, the host configures the host, including applying for a memory space accessible by the chip, where the memory space includes a descriptor queue memory space and a consumer pointer information memory space.
6. The traffic data flow control method applied to the PCle device according to claim 5, wherein the chip further includes a descriptor cache module and a data cache module, the descriptor cache module is configured to store a base address of the memory space of the descriptor queue and a base address of the memory space of the consumer pointer information, and is provided with a producer descriptor pointer register, and the data cache module corresponds to the descriptor cache module and is configured to store data information corresponding to a consumer pointer.
7. The method as claimed in claim 6, wherein the descriptor caching module is further configured to obtain the data entry to be processed according to the producer descriptor pointer and the stored consumer pointer information when the host producer descriptor pointer is updated.
8. The traffic data flow control method applied to the PCle equipment according to claim 7, wherein the flow control engine comprises a flow control preprocessing module, a flow control information calculating module, a flow post-processing module and a MWr sending request module,
the flow control preprocessing module receives the data entry to be processed, the consumer descriptor pointer and the corresponding data information output by the data caching module, which are acquired by the descriptor caching module, and outputs the data entry to the flow control information computing module after merging and latching;
the flow control information calculation module calculates the data items to be acquired by combining with the free space of the service processing module, and sends the calculated data items to be acquired to the flow post-processing module;
the flow post-processing module reads the address of the data entry to be acquired from the descriptor cache module and sends the address to the MWr sending request module;
the MWr sending request module sends a Mwr request to the host end according to the address of the data entry to be obtained, and obtains a corresponding producer message from the host end.
9. The method as claimed in claim 4, wherein the flow control engine further includes a descriptor status management module, configured to maintain status information of the descriptor and read/write pointers of the host and other service function modules at the PCle device side.
10. The method as claimed in claim 4, wherein the flow control engine further includes a configuration module, configured to store the information configured at the host side.
CN202211701918.XA 2022-12-29 2022-12-29 Business data flow control method applied to PCIe equipment Active CN115842790B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211701918.XA CN115842790B (en) 2022-12-29 2022-12-29 Business data flow control method applied to PCIe equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211701918.XA CN115842790B (en) 2022-12-29 2022-12-29 Business data flow control method applied to PCIe equipment

Publications (2)

Publication Number Publication Date
CN115842790A true CN115842790A (en) 2023-03-24
CN115842790B CN115842790B (en) 2023-05-02

Family

ID=85579377

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211701918.XA Active CN115842790B (en) 2022-12-29 2022-12-29 Business data flow control method applied to PCIe equipment

Country Status (1)

Country Link
CN (1) CN115842790B (en)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030184548A1 (en) * 2002-03-29 2003-10-02 Emmot Darel N. System and method for passing messages among processing nodes in a distributed system
US20140181340A1 (en) * 2012-02-07 2014-06-26 Balaji Parthasarathy Deterministic method to support multiple producers with multiple consumers in peer or hierarchical systems
US20140281055A1 (en) * 2013-03-15 2014-09-18 Vmware, Inc. Latency reduction for direct memory access operations involving address translation
US20170024568A1 (en) * 2015-07-20 2017-01-26 Pradeep M. Pappachan Technologies for integrity, anti-replay, and authenticity assurance for i/o data
CN107623642A (en) * 2017-08-30 2018-01-23 山东中创软件商用中间件股份有限公司 A kind of message traffic control method and device
US20190044871A1 (en) * 2018-09-27 2019-02-07 Intel Corporation Technologies for managing single-producer and single consumer rings
CN111858413A (en) * 2020-06-29 2020-10-30 牛芯半导体(深圳)有限公司 Data scheduling method and device for PCIE (peripheral component interface express) exchange chip port
CN113535395A (en) * 2021-07-14 2021-10-22 西安电子科技大学 Descriptor queue and memory optimization method, system and application of network storage service
US20220012201A1 (en) * 2020-07-07 2022-01-13 Apple Inc. Scatter and Gather Streaming Data through a Circular FIFO
WO2022016767A1 (en) * 2020-07-20 2022-01-27 北京泽石科技有限公司 Data queue processing method and apparatus

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030184548A1 (en) * 2002-03-29 2003-10-02 Emmot Darel N. System and method for passing messages among processing nodes in a distributed system
US20140181340A1 (en) * 2012-02-07 2014-06-26 Balaji Parthasarathy Deterministic method to support multiple producers with multiple consumers in peer or hierarchical systems
US20140281055A1 (en) * 2013-03-15 2014-09-18 Vmware, Inc. Latency reduction for direct memory access operations involving address translation
US20170024568A1 (en) * 2015-07-20 2017-01-26 Pradeep M. Pappachan Technologies for integrity, anti-replay, and authenticity assurance for i/o data
CN107623642A (en) * 2017-08-30 2018-01-23 山东中创软件商用中间件股份有限公司 A kind of message traffic control method and device
US20190044871A1 (en) * 2018-09-27 2019-02-07 Intel Corporation Technologies for managing single-producer and single consumer rings
CN111858413A (en) * 2020-06-29 2020-10-30 牛芯半导体(深圳)有限公司 Data scheduling method and device for PCIE (peripheral component interface express) exchange chip port
US20220012201A1 (en) * 2020-07-07 2022-01-13 Apple Inc. Scatter and Gather Streaming Data through a Circular FIFO
WO2022016767A1 (en) * 2020-07-20 2022-01-27 北京泽石科技有限公司 Data queue processing method and apparatus
CN113535395A (en) * 2021-07-14 2021-10-22 西安电子科技大学 Descriptor queue and memory optimization method, system and application of network storage service

Also Published As

Publication number Publication date
CN115842790B (en) 2023-05-02

Similar Documents

Publication Publication Date Title
US7526593B2 (en) Packet combiner for a packetized bus with dynamic holdoff time
EP2568389B1 (en) Coherence switch for i/o traffic
US10739836B2 (en) System, apparatus and method for handshaking protocol for low power state transitions
US8825922B2 (en) Arrangement for processing trace data information, integrated circuits and a method for processing trace data information
US9864687B2 (en) Cache coherent system including master-side filter and data processing system including same
CN110858188A (en) Multiprocessor system with distributed mailbox structure and communication method thereof
WO2023124304A1 (en) Chip cache system, data processing method, device, storage medium, and chip
CN116089343A (en) AXI-based data storage method, device, storage medium and equipment
JP3444154B2 (en) Memory access control circuit
US20240021239A1 (en) Hardware Acceleration System for Data Processing, and Chip
US7774513B2 (en) DMA circuit and computer system
US11275707B2 (en) Multi-core processor and inter-core data forwarding method
US10445267B2 (en) Direct memory access (DMA) unit with address alignment
CN115842790A (en) Service data flow control method applied to PCle equipment
US9767054B2 (en) Data transfer control device and memory-containing device
CN116414743A (en) Method for controlling memory, memory controller and chip
JP2002149591A (en) Method and device for optimizing bus in processor local bus system
CN113157628B (en) Storage system, data processing method and device, storage system and electronic equipment
JP5359603B2 (en) Integrated circuit system, data writing method, and data reading method
CN113220608A (en) NVMe command processor and processing method thereof
JPH08212178A (en) Parallel computer
CN116745754A (en) System and method for accessing remote resource
US7930459B2 (en) Coherent input output device
CN111338567A (en) Mirror image caching method based on Protocol Buffer
CN113392604B (en) Dynamic capacity expansion method and system for cache under multi-CPU co-encapsulation architecture based on advanced encapsulation technology

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant