CN113220608A - NVMe command processor and processing method thereof - Google Patents
NVMe command processor and processing method thereof Download PDFInfo
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- CN113220608A CN113220608A CN202110641849.7A CN202110641849A CN113220608A CN 113220608 A CN113220608 A CN 113220608A CN 202110641849 A CN202110641849 A CN 202110641849A CN 113220608 A CN113220608 A CN 113220608A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Abstract
The embodiment of the invention provides an NVMe command processor and a processing method thereof, wherein the NVMe command processor comprises a DMA command storage component, a DMA command control component, a DMA component and a DMA command completion component; the DMA command storage component is connected with the CPU component to store a first combined command issued by the CPU component, wherein the first combined command is a command obtained by combining the DMA command and the firmware command; the DMA command control component is connected with the DMA command storage component; the DMA component is respectively connected with the DMA command control component and the DMA command completion component; the DMA command completion component is connected with the DMA command storage component. The firmware command data structure and the DMA command data structure issued by the CPU component are combined, so that the time for reading the firmware commands corresponding to a plurality of DMA commands for many times is saved, and the processing speed of the NVMe command is improved.
Description
Technical Field
The invention relates to the field of data storage, in particular to an NVMe command processor and a processing method thereof.
Background
With the rapid development of information technology, technologies in the fields of cloud computing, artificial intelligence and the like are further broken through, wherein in the field of data information storage, a Solid State Disk (SSD) has a faster read/write speed than a mechanical hard Disk, most of the existing machines use a Serial ATA (SATA) standard, the actual maximum transmission speed is about 600MB/s, and the existing machines support a Peripheral Component Interconnect Express (PCIe), the actual transmission speed exceeds 1000MB/s, and a Non-Volatile Memory protocol (Non-Volatile Memory Express (NVMe) is a standard interface protocol established for PCIe). Accordingly, the SSD supporting the NVMe protocol gains more and more attention in the data storage field due to its advantages of low latency, low power consumption, and high bandwidth, and becomes a new wind direction for the development of storage devices.
Under the NVMe protocol, generally, an operation command of a host to an SSD is stored according to a commit Queue (SQ), and the NVMe command is often processed in a manner of an NVMe firmware command Queue and a firmware Direct Memory Access (DMA) command Queue, or the NVMe command is divided into a DMA command for transferring write data and a DMA command for transferring read data. If the NVMe command is to be processed, the firmware commands corresponding to a plurality of DMA commands need to be read for many times, the processing time of the NVMe command is increased invisibly, read-write command distinguishing needs to be carried out on a plurality of DMA command queues, the operation is complex, and the utilization efficiency of the DMA commands is reduced.
Disclosure of Invention
Objects of the present invention include, for example, providing an NVMe command processor and a processing method thereof, which can solve at least some of the above problems.
In a first aspect, an embodiment of the present application provides an NVMe command processor, configured to process a DMA command queue issued by a CPU component, where the NVMe command processor includes: the DMA command control system comprises a DMA command storage component, a DMA command control component, a DMA component and a DMA command completion component;
the DMA command storage component is used for being connected with the CPU component and storing a first combination command and a DMA command completion entry which are issued by the CPU component, wherein the first combination command is a command obtained by combining a DMA command and a firmware command;
the DMA command control component is connected with the DMA command storage component and used for reading the first combined command in the DMA command storage component and analyzing the first combined command to obtain a DMA command;
the DMA component is respectively connected with the DMA command control component and the DMA command completion component and is used for analyzing the DMA command and executing corresponding actions;
the DMA command completion component is connected with the DMA command storage component and used for storing the DMA command completion entries and writing the DMA command completion entries into the DMA command storage component.
In one possible implementation, the NVMe command processor further includes a DMA command request arbitration component and a DMA command completion arbitration component;
the DMA command storage component stores at least one DMA command queue, the DMA command queue comprises a read command storage area and a write command storage area, the read command storage area is used for storing DMA read commands, and the write command storage area is used for storing DMA write commands;
under the condition that the DMA command storage component stores a plurality of DMA command queues, the DMA command request arbitration component is respectively connected with the plurality of DMA components and the DMA command control component and is used for arbitrating a plurality of simultaneously initiated DMA requests, wherein the DMA requests are used for requesting to read DMA commands in the DMA command control component;
the DMA command completion arbitration component is respectively connected with the plurality of DMA components and the DMA command completion component and is used for arbitrating the access of the plurality of DMA commands which are completed simultaneously to access the DMA command completion component.
In one possible implementation, the DMA command request arbitration component and the DMA command completion arbitration component are both round robin arbitration components.
In one possible implementation, the NVMe command processor further includes a DMA command register component;
the DMA command register component is used for being connected with the CPU component and is used for carrying out configuration through a CPU register configuration bus;
the DMA command register component is also respectively connected with the DMA command control component and the DMA command completion component and used for updating a read pointer register and a write pointer register corresponding to the DMA command.
In one possible implementation, the NVMe command processor further includes a DMA engine for performing a move of DMA commands.
In a second aspect, an embodiment of the present application provides an NVMe command processing method, which is applied to an NVMe command processor connected to a CPU component, where the processor includes: a DMA command storage component, a DMA command control component, a DMA component, and a DMA command completion component, the method comprising:
the DMA command storage component stores a first combination command issued by the CPU component and a DMA command completion entry, wherein the first combination command is a command obtained by combining a DMA command and a firmware command;
the DMA command control component reads the first combined command in the DMA command storage component and analyzes the first combined command to obtain a DMA command;
the DMA component analyzes the DMA command and executes a corresponding action;
the DMA command completion component stores a DMA command completion entry and writes the DMA command completion entry to the DMA command storage component.
In a third aspect, an embodiment of the present application provides a computer device, where the computer device includes a device body, a memory and a processor, where the memory stores a computer program, and the computer device includes the NVMe command processing method of the second aspect.
In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, where the computer program is used to execute the method of the second aspect.
The beneficial effects of the embodiment of the invention include, for example:
the NVMe command processor provided in the embodiment of the present application is configured to be connected to a CPU component through a DMA command storage component, and store a first combination command and a DMA command completion entry issued by the CPU component, where the first combination command is a command obtained by combining a DMA command and a firmware command, and then is connected to the DMA command storage component according to a DMA command control component, and is configured to read the first combination command in the DMA command storage component and analyze the first combination command to obtain a DMA command, and complete processing of the DMA command.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a computer device according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an NVMe command processor provided in an embodiment of the present application;
fig. 3 is a schematic structural diagram of another NVMe command processor provided in an embodiment of the present application;
fig. 4 is a flowchart of an NVMe command processing method according to an embodiment of the present application.
Icon:
a computer device 100; an apparatus body 110; a memory 120; a processor 130;
a CPU component 300.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a computer device provided in this embodiment. The computer device 100 includes a device body 110, a computer-readable storage medium 120, and a processor 130.
The computer-readable storage medium 120 and the processor 130 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, the components may be electrically connected to each other via one or more communication buses or signal lines. The device body 110 includes at least one software functional module which can be stored in the computer readable storage medium 120 in the form of software or Firmware (Firmware) or solidified in an Operating System (OS) of the computer device 100. The processor 130 is configured to execute executable modules stored in the computer-readable storage medium 120, such as software functional modules and computer programs included in the device body 110, and the device body 110 further includes a device shell, a hardware interface, and the like.
The computer-readable storage medium 120 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), an electrically Erasable Read-Only Memory (EEPROM), and the like. The computer-readable storage medium 120 is used for storing a program, and the processor 130 executes the program after receiving an execution instruction.
The processor 130 may be an integrated circuit chip having signal processing capabilities. The Processor may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
Referring to fig. 2, fig. 2 is a schematic structural diagram of an NVMe command processor, and the NVMe command processor 200 provided may be the processor 130 in fig. 1. The NVMe command processor 200 includes: DMA command storage component 210, DMA command control group 220 component, DMA component 240, and DMA command completion component 260;
the DMA command storage component 210 is configured to be connected to the CPU component 300, and configured to store a first merge command and a DMA command completion entry issued by the CPU component 300, where the first merge command is a command obtained by merging a DMA command and a firmware command;
the DMA command control component 220 is connected to the DMA command storage component 210, and is configured to read the first merged command in the DMA command storage component 210 and parse the first merged command to obtain a DMA command;
the DMA component 240 is respectively connected to the DMA command control component 220 and the DMA command completion component 260, and is configured to parse the DMA command and execute a corresponding action;
the DMA command completion component 260 is coupled to the DMA command storage component 210 and is configured to store a DMA command completion entry and write the DMA command completion entry into the DMA command storage component 210.
Specifically, in order to enable the NVMe SSD to obtain the DMA command generated by the CPU component 300, the DMA command storage component 210 is configured to be connected to the CPU component 300, where the DMA command storage component 210 is used as a storage medium between the CPU component 300 and the NVMe SSD, and may optionally include any one of a Static Random-Access Memory (SRAM), a Dynamic Random-Access Memory (DRAM), and a storage space inside the CPU component 300, and may be selected according to different requirements, which is not limited herein.
In addition, considering that the command data structure of the firmware command issued by the CPU component 300 is relatively simple, the command data structure of the firmware command and the command data structure of the DMA command can be merged to form a new command data structure of the DMA command, and the DMA command storage component 210 can store a first merged command, where the first merged command is a command obtained by merging the DMA command and the firmware command. Then, the subsequent process of reading the DMA command does not need to separately read the firmware command issued by the CPU component 300, so that the operation of reading the firmware command is omitted, the command processing time is saved, and the command processing speed is increased.
After the CPU component 300 issues a DMA command queue entry to the DMA command queue, storing the DMA command queue to the DAM command storage component 210 completes the storing of the DMA command, but the DMA command still needs to be fetched and executed.
Specifically, the DMA command control component 220 reads the first merged command from the DMA command storage component 210 and parses the first merged command to obtain a DMA command. The DMA command control component 220 reads the DMA command according to the DMA command queue stored in the DMA command storage component 210, if the sq _ entry field in the DMA command data structure is 1, reads the I/O command from the I/O command address of the DMA command data structure and writes the required command information into a command storage SRAM inside the DMA command control component 220, where the write address of the SRAM is the cmd _ id field in the DMA command data structure, and writes the non-IO command part of the DMA command into a first-in first-out (FIFO) register of the nf command control component 220.
In addition, the DMA component 240 is connected to the DMA command request arbitration component 230 and the DMA command completion arbitration component 250, respectively, and is configured to parse the DMA command and perform a corresponding action. Alternatively, in the case where there are fewer DMA commands to issue and storage is available through a queue of DMA commands, only one DMA component 240 may be provided for executing the DMA command.
After the DMA command is executed, the execution result needs to be fed back to the CPU component 300, and further, the DMA command storage component 210 stores a DMA command completion entry, and writes the DMA command completion entry into the DMA command storage component 210.
According to the NVMe command processor provided by this embodiment, the DMA command storage component is used for being connected with the CPU component, and stores a first combination command and a DMA command completion entry issued by the CPU component, where the first combination command is a command obtained by combining a DMA command and a firmware command, and the DMA command control component is connected with the DMA command storage component according to the DMA command, and is used to read the first combination command in the DMA command storage component and analyze the first combination command to obtain a DMA command, and complete processing of the DMA command.
Considering that under the condition that a plurality of DMA commands exist, one DMA command queue cannot store all the DMA commands, a plurality of DMA command queues are formed for storing, and accordingly, at least one DMA component is required to execute the plurality of DMA commands.
Specifically, referring to fig. 3, fig. 3 is a schematic structural diagram of another NVMe command processor. In one possible implementation, the NVMe command processor 200 further includes a DMA command request arbitration component 230 and a DMA command completion arbitration component 250 to allocate DMA commands to idle DMA components and execute them.
In a possible implementation, a plurality of DMA command queues may be combined and then stored in the DMA command storage component 210, so that the number of times of reading the NVMe SSD from the DMA command storage component 210 is reduced, and the operation flow of reading the DMA command is also simplified.
Specifically, the DMA command storage component 210 stores at least one DMA command queue, and the merged DMA command queue includes a read command storage area and a write command storage area, where the read command storage area is used to store a DMA read command, and the write command storage area is used to store a DMA write command, so that the read DMA command can support both a read command operation and a write command operation, and the operation flow of command reading is simplified.
In addition, the DMA command request arbitration component 230 is connected to a plurality of the DMA components 240 and the DMA command control component 220, respectively.
In the case where the DMA command storage component 210 stores multiple DMA command queues, the DMA command request arbitration component 230 may arbitrate for multiple simultaneously initiated DMA requests requesting to read DMA commands within the DMA command control component 220.
Wherein a plurality of said DMA components 240 may comprise DMA0Component, DMA1Component … …, DMAnThe number of the DMA components 240 can be selected according to requirements.
The DMA command completion arbitration component 250 is connected to a plurality of the DMA components 240 and the DMA command completion component 260, respectively, and can arbitrate access to the DMA command completion component 260 for a plurality of simultaneously completed DMA commands.
Optionally, the DMA command completion arbitration component 250 and the DMA command request arbitration component 230 may both be configured as round-robin arbitration components to implement round-robin arbitration for DMA commands.
Optionally, the NVMe command processor 200 further includes a DMA command register component 270 connected to the CPU component 300, and after the DMA command is written into the DMA command storage component 210, the CPU component 300 updates the register in the DMA command register component 270. In addition, the DMA command register component 270 is further connected to the DMA command control component 220 and the DMA command completion component 260, respectively, for updating the read pointer register and the write pointer register corresponding to the DMA command.
In order to implement the moving of the DMA command data, optionally, the NVMe command processor 200 further includes a DMA engine, which is responsible for fast transmission of the DMA command data, specifically, for controlling fast data transmission between two main memories, such as DMA command data transmission between an SRAM and a cache chip of the central controller.
Based on the design, the firmware command data structure issued by the CPU component and the DMA command data structure are combined, so that the time for reading the firmware commands corresponding to a plurality of DMA commands for many times is saved, the processing speed of the NVMe commands is improved, in addition, a plurality of DMA command queues are combined and then stored in the DMA command storage component, the reading times of the NVMe SSD from the DMA command storage component are reduced, and the operation flow for reading the DMA commands is also simplified.
The command data structure of the DMA command issued by the CPU component 300 in the present application and the command data structure of the firmware command are merged to obtain a new DMA command data structure, and table 1 below is a structure analysis table of the new DMA command data structure.
TABLE 1
Where DW represents a field segment in the DMA command data structure, the interpretation of each field segment is as follows:
dma _ id: for identifying the DMA command, to which DMA _ id in the DMA completion queue entry corresponds;
cmd _ id: used for showing which firmware command the DMA command belongs to, and the cmd _ id in the DMA completion queue entry corresponds to;
cq _ id: indicating which CQ entry to reply to a CQ entry when auto _ CQ _ en of the dma _ ctrl field is 1;
trans _ length: the data length required to be transmitted by the DMA is represented in unit of multiple bits;
host _ offset _ addr: the starting offset address of the DMA host end is represented;
sgl _ base _ addr: representing the starting address of the SGL of the DMA device end;
sgl _ length: represents the length of the SGL in unit of times of tex;
sq _ entry _ addr: indicating that the SQ command holds a start address that is valid only if the SQ _ entry bit of the dma _ ctrl field is 1.
Wherein, the specific information of each bit of dma _ ctrl is shown in table 2 below.
TABLE 2
The data structure of the DMA command completion information of the present application is shown in table 3 below.
TABLE 3
The description of the various fields in table 3 is as follows:
dma _ id: the DMA completion entry information is associated with the DMA corresponding to the DMA _ id field of the DMA command data structure;
cmd _ id: indicating which firmware command the DMA belongs to, corresponding to the cmd _ id field of the DMA command data structure;
dma _ err _ status: reporting error information of the execution result of the DMA command, such as DMA _ length _ err (trans _ length invalid of DMA command data structure), DMA _ cmd _ invalid (DMA command invalid, i.e. cmd _ id invalid of DMA), PRP related protocol error, SGL related protocol error, etc.;
cmd _ err _ status: error reporting information of the firmware command execution result is valid only when the cmd _ done bit of the DMA _ status field is 1, such as DMA _ length _ err (trans _ length invalid of the DMA command data structure), DMA _ cmd _ invalid (DMA command invalid, i.e. cmd _ id invalid of the DMA), PRP related protocol error, SGL related protocol error, etc.;
the bit information of the dma _ status field in table 4 is described as follows:
TABLE 4
Referring to fig. 4, fig. 4 is a flowchart of an NVMe command processing method, and the method including various steps will be described in detail below.
S410, the DMA command storage component 210 stores a first merge command issued by the CPU component 300 and a DMA command completion entry, where the first merge command is a command obtained by merging a DMA command and a firmware command.
The command data structure of the firmware command issued by the CPU component 300 is relatively simple, the command data structure of the firmware command and the command data structure of the DMA command may be merged, and the DMA command storage component 210 may store a first merged command, where the first merged command is a command obtained by merging the DMA command and the firmware command. In the subsequent reading process of the DMA command, the firmware command issued by the CPU component 300 does not need to be read independently, so that the operation of reading the firmware command is omitted, the command processing time is saved, and the command processing speed is increased.
S420, the DMA command control component 220 reads the first merge command in the DMA command storage component 210 and parses the first merge command to obtain the DMA command.
S430, the DMA component 240 parses the DMA command and performs a corresponding action.
S440, the DMA command completion component 260 stores a DMA command completion entry and writes the DMA command completion entry to the DMA command storage component 210.
After the DMA command execution is completed, the DMA command completion entry needs to be written into the DMA command storage component 210, and the CPU component 300 may then look at the DMA command completion entry to process the DMA command execution result therein.
In one possible implementation, the NVMe command processor 200 further includes a DMA command request arbitration component 230 and a DMA command completion arbitration component 250.
The DMA command storage component 210 stores at least one DMA command queue comprising a read command storage area for storing DMA read commands and a write command storage area for storing DMA write commands.
In the case where the DMA command storage component 210 stores multiple DMA command queues, the DMA command request arbitration component 230 arbitrates for multiple simultaneously-initiated DMA requests requesting to read DMA commands within the DMA command control component 220.
The DMA command completion arbitration component 250 arbitrates for access by multiple concurrently completed DMA commands to the DMA command completion component 260.
Specifically, considering that when there are a plurality of DMA commands, one DMA command queue cannot store all the DMA commands, a plurality of DMA command queues are formed for storing, and accordingly, at least one DMA component is also required to execute a plurality of DMA commands, so a scheme of selecting by adding a plurality of DMA components 240 is provided. The DMA command storage component 210 stores at least one DMA command queue, where the DMA command queue includes a read command storage area for storing DMA read commands and a write command storage area for storing DMA write commands.
In addition, for the situation that each DMA command is provided with one DMA command queue and the DMA command queue is divided into a read DMA command queue and a write DMA command queue, the operation process is complex, and multiple times of reading and writing of DMA commands and reading of DMA commands are required, and in this situation, multiple DMA command queues can be combined and then stored in the DMA command storage component 210, so that the number of times of reading the NVMe SSD from the DMA command storage component 210 is reduced, and the operation flow of reading DMA commands is also simplified.
Optionally, the NVMe command processor 200 further includes a DMA command register component 270 to update read and write pointer registers corresponding to DMA commands.
In one possible embodiment, the DMA component 240 is configured to parse the DMA command and perform a corresponding action, specifically, if the DMA command is a read command, the DMA command is read from a device side and written into the CPU component 300, and if the DMA command is a write command, the DMA command is read from the CPU component 300 and written into a device side buffer, where the device side buffer includes SRAM and DRAM.
Secondly, under the condition of reading the DMA commands in the DMA command queue, whether the DMA command queue is empty needs to be detected, if the DMA command queue is not empty, the operation of reading the DMA commands in the DMA command queue is skipped to be executed, if the DMA command queue is empty, whether the DMA command queue is empty is continuously detected until the DMA command queue stops when a preset stop condition is met, wherein the preset stop condition comprises that the DMA command queue is not empty, optionally, the preset stop condition can also comprise a preset time length, and if a command is generated but the command cannot be read after the preset time, at this time, a warning message can be generated to remind of possible equipment faults.
The specific implementation process of the NVMe command processing method provided in this embodiment may also refer to the specific implementation process in the NVMe command processor.
The embodiment also provides a computer device, which includes a device body, a memory and a processor, wherein the processor executes computer instructions stored in the memory, so that the computer device implements the NVMe command processing method when executing the computer instructions.
The present embodiment also provides a computer-readable storage medium on which a computer program is stored, which, when executed by a processor, implements the NVMe command processing method.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (12)
1. An NVMe command processor for processing a DMA command queue issued by a CPU component, the NVMe command processor comprising: the DMA command control system comprises a DMA command storage component, a DMA command control component, a DMA component and a DMA command completion component;
the DMA command storage component is used for being connected with the CPU component and storing a first combination command and a DMA command completion entry which are issued by the CPU component, wherein the first combination command is a command obtained by combining a DMA command and a firmware command;
the DMA command control component is connected with the DMA command storage component and used for reading the first combined command in the DMA command storage component and analyzing the first combined command to obtain a DMA command;
the DMA component is respectively connected with the DMA command control component and the DMA command completion component and is used for analyzing the DMA command and executing corresponding actions;
the DMA command completion component is connected with the DMA command storage component and used for storing the DMA command completion entries and writing the DMA command completion entries into the DMA command storage component.
2. The NVMe command processor of claim 1, further comprising a DMA command request arbitration component and a DMA command completion arbitration component;
the DMA command storage component stores at least one DMA command queue, the DMA command queue comprises a read command storage area and a write command storage area, the read command storage area is used for storing DMA read commands, and the write command storage area is used for storing DMA write commands;
under the condition that the DMA command storage component stores a plurality of DMA command queues, the DMA command request arbitration component is respectively connected with the plurality of DMA components and the DMA command control component and is used for arbitrating a plurality of simultaneously initiated DMA requests, wherein the DMA requests are used for requesting to read DMA commands in the DMA command control component;
the DMA command completion arbitration component is respectively connected with the plurality of DMA components and the DMA command completion component and is used for arbitrating the access of the plurality of DMA commands which are completed simultaneously to access the DMA command completion component.
3. The NVMe command processor of claim 2, wherein the DMA command request arbitration component and the DMA command completion arbitration component are both round robin arbitration components.
4. The NVMe command processor of claim 1, further comprising a DMA command register component;
the DMA command register component is used for being connected with the CPU component and is used for carrying out configuration through a CPU register configuration bus;
the DMA command register component is also respectively connected with the DMA command control component and the DMA command completion component and used for updating a read pointer register and a write pointer register corresponding to the DMA command.
5. The NVMe command processor of claim 1, further comprising a DMA engine to perform a move of DMA commands.
6. The NVMe command processing method is applied to an NVMe command processor connected with a CPU component, and the processor comprises the following steps: a DMA command storage component, a DMA command control component, a DMA component, and a DMA command completion component, the method comprising:
the DMA command storage component stores a first combination command issued by the CPU component and a DMA command completion entry, wherein the first combination command is a command obtained by combining a DMA command and a firmware command;
the DMA command control component reads the first combined command in the DMA command storage component and analyzes the first combined command to obtain a DMA command;
the DMA component analyzes the DMA command and executes a corresponding action;
the DMA command completion component stores a DMA command completion entry and writes the DMA command completion entry to the DMA command storage component.
7. The NVMe command processing method of claim 6, wherein the NVMe command processor further comprises a DMA command request arbitration component and a DMA command completion arbitration component, the DMA component parsing the DMA command and performing the corresponding action comprising:
the DMA command storage component stores at least one DMA command queue, the DMA command queue comprises a read command storage area and a write command storage area, the read command storage area is used for storing DMA read commands, and the write command storage area is used for storing DMA write commands;
in the case that the DMA command storage component stores a plurality of DMA command queues, the DMA command request arbitration component arbitrates for a plurality of DMA requests initiated simultaneously, wherein the DMA requests are used for requesting to read DMA commands in the DMA command control component;
the DMA command completion arbitration component arbitrates for access by multiple concurrently completed DMA commands to the DMA command completion component.
8. The NVMe command processing method of claim 6, further comprising a DMA command register component, the DMA component following the step of parsing the DMA command and performing the corresponding action, the method further comprising:
the read pointer register and write pointer register corresponding to the DMA command are updated.
9. The NVMe command processing method of claim 6, wherein the step of the DMA component parsing the DMA command and performing the corresponding action comprises:
if the DMA command is a read command, reading the DMA command from a device end and writing the DMA command into the CPU component;
and if the DMA command is a write command, reading the DMA command from the CPU component and writing the DMA command into an equipment side buffer, wherein the equipment side buffer comprises a static random access memory and a dynamic random access memory.
10. The NVMe command processing method of claim 6, wherein the step of reading the DMA commands in the DMA command queue comprises:
detecting whether the DMA command queue is empty;
if the DMA command queue is not empty, skipping to execute the operation of reading the DMA command in the DMA command queue;
and if the DMA command queue is empty, continuously detecting whether the DMA command queue is empty or not until the DMA command queue stops when a preset stop condition is met, wherein the preset stop condition comprises that the DMA command queue is not empty.
11. A computer device, comprising a device body, a memory, and a processor, wherein the processor executes computer instructions stored in the memory, causing the computer device to perform the steps of the NVMe command processing method of claims 6-10.
12. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the NVMe command processing method according to claims 6 to 10.
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