CN115835722A - Display panel and method for manufacturing the same - Google Patents

Abstract

The invention discloses a display panel and a manufacturing method thereof, and belongs to the field of display panels. The display panel is provided with a non-display area, the non-display area comprises a first area, a second area and a third area which are sequentially connected, a first conductive layer comprises a first conductive part and a second conductive part which are respectively arranged in the first area and the third area, a second conductive layer comprises a third conductive part and a fourth conductive part which are respectively arranged in the first area and the third area, the fourth conductive part is separated from the second conductive part through a first planarization layer, the third conductive part is stacked on the first conductive part, and one side surface of the first conductive part facing the second conductive part is contacted with the third conductive part and/or the second planarization layer; the second area is provided with a groove; in the second region, at least a portion of the third conductive layer is in contact with the substrate. In the application, the second conductive layer is not warped upwards during film formation, the distance between the second conductive layer and the third conductive layer is increased, and short circuit is not easy to occur.

Description

Display panel and method for manufacturing the same

Technical Field

The present invention relates to the field of display panels, and in particular, to a display panel and a method for manufacturing the same.

Background

At present, the ultra-narrow frame is a great trend of mobile phone product design. Because the frame is reduced, the wiring space of the mobile phone frame is more and more tense. Because the wiring space is reduced, the metal line width and line distance is continuously reduced, the distance between adjacent grooves is reduced, the distance between the metal wiring and the conductive layer on the surface is shortened, and residual materials are arranged between the two grooves of the planarization layer, so that the metal wiring layer can be upwarped when encountering the residual materials of the planarization layer in the process of forming the film by the metal wiring. Therefore, in the aging process of the display panel, two metal lines (such as an anode and a metal trace) with different signals are easily shorted together, so that a blast occurs, and the display of the display panel is abnormal.

Disclosure of Invention

The embodiment of the application provides a display panel on the one hand to reduce the probability of explosion injury caused by short circuit between two conducting layers. The display panel comprises a substrate, a first conducting layer, a first planarization layer, a second conducting layer, a second planarization layer and a third conducting layer, wherein the first conducting layer, the first planarization layer, the second conducting layer, the second planarization layer and the third conducting layer are sequentially arranged on the substrate, the display panel is provided with a display area and a non-display area, the non-display area comprises a first area, a second area and a third area which are sequentially connected, the first conducting layer comprises a first conducting part and a second conducting part which are respectively arranged in the first area and the third area, the second conducting layer comprises a third conducting part and a fourth conducting part which are respectively arranged in the first area and the third area, the fourth conducting part and the second conducting part are separated through the first planarization layer, the third conducting part is arranged on the first conducting part in a stacking mode, and one side surface, facing the second conducting part, of the first conducting part is in contact with the third conducting part and/or the second planarization layer; the second area is provided with a groove; in the second region, at least a part of the third conductive layer is in contact with the substrate.

In some embodiments, the first conductive layer is provided with a first through groove, and the first through groove is partially located in the second region and partially extends into the first region and the third region; and/or the surface of one side of the second conductive part facing the first conductive part is in contact with the first planarization layer; and/or in the third area, at least part of the second planarization layer covers the first planarization layer.

In some embodiments, the first planarization layer defines a second channel, the second channel being located in the first and second regions; and/or the second planarization layer is provided with a third through groove, and the third through groove is positioned in the second area.

In some embodiments, in the first region, a side surface of the first conductive portion facing the second conductive portion is in contact with the third conductive portion, and a side surface of the third conductive portion facing the second conductive portion is in contact with the second planarization layer.

In some embodiments, within the first region, the second planarization layer is over the third conductive portion, and the second planarization layer also has a portion of a structure in contact with the substrate.

In some embodiments, the second region has a width in the direction from the first region to the third region of 5-7 μm; and/or the width of the first conductive layer in the first region along the direction from the first region to the third region is 5-7 μm; and/or the maximum distance between the second conductive layer and the substrate in the first region is 2-4 μm.

In some embodiments, the third conductive layer is a continuous layer within the first region, the second region, and the third region; in the first region and the third region, the third conductive layer covers the second planarization layer.

In another aspect, the present invention provides a method for manufacturing a display panel, in the non-display region, the method including: providing a substrate, and forming a first conductive film layer on the substrate; patterning the first conductive film layer to form a first conductive part and a second conductive part separated by a first through groove; forming a first planarization film layer on the substrate and the first and second conductive portions; patterning the first planarization film layer to remove at least a first portion of the first planarization film layer located in the first through groove and at least a second portion connected to the first portion and located on the first conductive portion, thereby forming a first planarization layer located at least partially on the second conductive portion; and forming a second conductive film layer on the substrate, the first planarization layer, and the first conductive portion.

In some embodiments, further comprising: patterning the second conductive film layer to form a third conductive portion on the first conductive portion and a fourth conductive portion on the first planarization layer, wherein the fourth conductive portion is isolated from the second conductive portion by the first planarization layer; forming a second planarizing film layer on the substrate, the first planarizing layer, the third conductive portion, and the fourth conductive portion; patterning the second planarization film layer to expose a part of the substrate corresponding to the first through groove, so as to form a second planarization layer; a first portion of the second planarization layer is on the third conductive portion and a second portion of the second planarization layer is on the fourth conductive portion; wherein a side surface of the first conductive portion facing the second conductive portion is in contact with the third conductive portion and/or the second planarization layer; and forming a third conducting layer on the substrate and the second planarization layer, wherein at least part of the third conducting layer is in contact with a part of the substrate corresponding to the first through groove.

In some embodiments, in the step of patterning the first planarizing film layer, a side surface of the second conductive portion facing the first conductive portion is brought into contact with the first planarizing layer.

In some embodiments, in the step of patterning the second planarizing film layer, at least a portion of the structure of the second planarizing layer is overlaid on the first planarizing layer; and/or in the step of patterning the second planarization film layer, a side surface of the first conductive part facing the second conductive part is in contact with the third conductive part, and a side surface of the third conductive part facing the second conductive part is in contact with the second planarization layer; and/or in the step of patterning the second planarization film layer, the first part of the second planarization layer is positioned above the third conductive part, and the first part of the second planarization layer is also in contact with the substrate.

The application provides a display panel and a manufacturing method thereof, and the display panel is provided with a groove in a second area, so that a third conductive layer covering the surface of the groove is close to a third conductive part, and a short circuit is easily generated to cause explosion injury. The third conductive part is formed on the first conductive part and is not easy to warp upwards when the third conductive part is prepared, so that the situation that the third conductive part and the third conductive part are too close to each other is avoided, and the probability of short circuit and explosion damage of the third conductive part and the third conductive part is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive effort, wherein:

fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present application;

FIG. 2 is a schematic cross-sectional view illustrating a position of a frame of a display panel according to an embodiment of the present disclosure;

FIG. 3 is a schematic cross-sectional view illustrating a frame of a display panel according to a comparative example of the present application;

FIG. 4 is a schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure;

FIGS. 5a to 5e are schematic structural diagrams illustrating steps of a method for manufacturing a display panel according to an embodiment of the present disclosure;

FIG. 6 is a schematic flow chart illustrating a method for fabricating a display panel according to another embodiment of the present disclosure;

fig. 7a to 7d are schematic structural diagrams of steps of a method for manufacturing a display panel according to another embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

At present, in the process of increasing the screen occupation ratio of a display panel such as an OLED (Organic Light-Emitting Diode), a frame area of the display panel is smaller and smaller, so that the distance between metal wires is also smaller and smaller, and therefore, a short circuit phenomenon is easily generated between the metal wires with the closer distance, and an explosion occurs.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present application. The display device 10 according to the embodiment of the present invention includes a display panel 100. The display device 10 provided in the embodiment of the present invention may be: the display device comprises products or parts with display functions, such as a mobile phone, a tablet computer, a notebook computer, a television, a digital camera, an intelligent watch, a navigator and the like.

Referring to fig. 2, fig. 2 is a schematic cross-sectional view illustrating a frame position of a display panel according to an embodiment of the present disclosure. The invention provides a display panel, the display panel 100 includes a substrate 101, a first conductive layer 102, a first planarization layer 103, a second conductive layer 104, a second planarization layer 105 and a third conductive layer 106 which are sequentially disposed on the substrate 101, the display panel 100 has a display area (not shown) and a non-display area, the non-display area includes a first area a, a second area B and a third area C which are sequentially connected, the first conductive layer 102 includes a first conductive part 1021 and a second conductive part 1022 which are respectively disposed in the first area a and the third area C, the second conductive layer 104 includes a third conductive part 1041 and a fourth conductive part 1042 which are respectively disposed in the first area a and the third area C, the fourth conductive part 1042 is isolated from the second conductive part 1022 through the first planarization layer 103, the third conductive part 1041 is stacked on the first conductive part 1021, and the first conductive part 1021 is in contact with the third conductive part 1041 toward one side surface of the second conductive part 1022; the second area B is provided with a groove; in the second region B, at least a part of the third conductive layer 106 is in contact with the substrate 101. In other embodiments, a side surface of the first conductive portion 1021 facing the second conductive portion 1022 may also be in contact with the second planarization layer 105, or in contact with the third conductive portion 1041 and the second planarization layer 105 at the same time.

Specifically, the surface of the display panel 100 on the side away from the substrate 101 is provided with a third conductive layer 106, and the third conductive layer 106 is used for grounding, can be connected with other structures, and is commonly connected to a grounding terminal. Since the display panel 100 is provided with the groove 107 in the second region B, the third conductive layer 106 covering the surface of the groove 107 is close to the third conductive portion 1041, which may cause a short circuit and an explosion. According to the present invention, one side (left side in fig. 2) of the first conductive part 1021 in the first area a, which is close to the third area C, is directly contacted with the third conductive part 1041 (or the second planarization layer 105), and because the third conductive part 1041 is formed on the first conductive part 1021 on the left side of the third conductive part 1041 during the preparation of the third conductive part 1041, upward warping is not easily generated, so that the third conductive part 1041 is prevented from being too close to the third conductive layer 106, and the probability of short circuit and explosion damage of the third conductive part 1041 and the third conductive layer 106 is reduced.

Specifically, the first conductive layer 102 and the second conductive layer 104 are metal traces. The first conductive layer 102 and the second conductive layer 104 may be made of aluminum wire, copper wire, silver wire, gold-clad wire, or other suitable materials, and are not limited herein.

Specifically, the substrate 101 may be formed of any insulating material. For example, the substrate 101 may be formed of Polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyarylate (PAR), glass Fiber Reinforced Plastic (FRP), or a combination of these polymer materials. In addition, the substrate 101 may be a transparent, translucent or opaque substrate 101, and is not particularly limited herein. It is understood that, in consideration of the general structure of the substrate 101 in the OLED form of the display panel, in an alternative embodiment, the substrate 101 may include a substrate, a buffer layer, an active layer, a gate insulating layer, a gate electrode, and an insulating layer, which are sequentially stacked; the first conductive layer 102 is formed on the surface of the insulating layer facing away from the gate. In the present embodiment, the substrate 101 includes a substrate, and a thin film transistor for driving the OLED, the thin film transistor includes functional layers, such as an active layer, a gate insulating layer, a gate electrode, and an insulating layer, the first conductive layer 102 in the above embodiment is a source electrode or a drain electrode of the thin film transistor, and the source electrode and the drain electrode are formed on the interlayer insulating layer. It should be noted that the film structure of the substrate 101 is not limited in the present application, and those skilled in the art should select an appropriate film structure according to the actual application requirement, which is not described herein again.

Specifically, the material of each of the first planarizing layer 103 and the second planarizing layer 105 may be polyimide. The first planarizing layer 103 and the second planarizing layer 105 function to align the thicknesses of the first conductive layer 102 and the second conductive layer 104 with the difference in the thicknesses thereof, so that the third conductive layer 106 formed over the second planarizing layer 105 has flatness. That is, the third conductive layer 106 does not have unevenness due to the first conductive layer 102 and the second conductive layer 104 corresponding to the bottom thereof, and therefore, the problem of uneven brightness of each pixel of the substrate 101 due to the unevenness of the third conductive layer 106 corresponding to the bottom thereof is avoided, so that the color shift problem of the display device in the prior art is avoided, and the display effect of the display device is improved.

Optionally, in this embodiment, the first conductive layer 102 is provided with a first through groove 102a, and the first through groove 102a is partially located in the second region B and partially extends into the first region a and the third region C. That is, the range of the first through groove 102a is larger than the range of the second region B, and the first through groove 102a is provided in the first conductive layer 102, so that the first conductive layer 102 can be divided into the first conductive part 1021 and the second conductive part 1022 which are located in the first region a and the third region C, respectively. Specifically, the first conductive layer 102 may be formed by film formation on the substrate 101, and the first through groove 102a may be formed by etching on the first conductive layer 102.

Optionally, in this embodiment, a surface of the second conductive part 1022 facing the first conductive part 1021 is in contact with the first planarization layer 103. Since the groove 107 is formed in the second area B of the display panel 100, the third conductive layer 106 covering the surface of the groove 107 is closer to the side of the second conductive part 1022 facing the first conductive part 1021, which is likely to cause a short circuit and cause an explosion, and the first planarization layer 103 is in contact with the side of the second conductive part 1022 facing the first conductive part 1021, which avoids the second conductive part 1022 and the third conductive layer 106 from being too close to each other, and reduces the probability of the short circuit and the explosion. Specifically, the first planarizing layer 103 fills the first through recesses 102a partially located in the third region C.

Optionally, in the third region C, at least a part of the structure of the second planarization layer 105 covers the first planarization layer 103. So that the first planarization layer 103 and the second planarization layer 105 are simultaneously disposed between the second conductive portion 1022 and the third conductive layer 106, thereby avoiding short circuit.

Optionally, in this embodiment, the first planarization layer 103 is provided with a second through groove 103a, and the second through groove 103a is located in the first area a and the second area B. Specifically, the first planarizing layer 103 may be formed on the first conductive layer 102, and then the first planarizing layer 103 is patterned by etching, in this embodiment, the first planarizing layer 103 on the side of the second region B and the first region a close to the second region B is removed, so that the first conductive portion 1021 left side does not have the first planarizing layer 103, and thus the first conductive portion 1021 left side can directly contact with the third conductive portion 1041 or the second planarizing layer 105, and the formation of upward warpage on the third conductive portion 1041 left side is avoided, so that the probability of short circuit with the third conductive layer 106 is reduced.

Optionally, the second planarization layer 105 is opened with a third through groove 105a, and the third through groove 105a is located in the second region B. Further, in the first region a, a side surface of the first conductive portion 1021 facing the second conductive portion 1022 is in contact with the third conductive portion 1041, and a side surface of the third conductive portion 1041 facing the second conductive portion 1022 is in contact with the second planarization layer 105. The third through grooves 105a are used to form the grooves 107, and specifically, during the process of forming the second planarizing layer 105 on the surface of the second conductive layer 104, the second planarizing layer 105 may be patterned by etching to remove the second planarizing layer 105 in the second region B.

Optionally, in the first region a, the second planarization layer 105 is located above the third conductive portion 1041, and a part of the second planarization layer 105 is in contact with the substrate 101. So that the second planarization layer 105 is insulated between the left side of the third conductive portion 1041 and the third conductive layer 106 to avoid short circuit therebetween.

Specifically, the width of the second region B in the direction from the first region A to the third region C is 5 to 7 μm; the width of the first conductive layer 102 located in the first region a in the direction pointing to the third region C along the first region a is 5 to 7 μm; the maximum distance between the second conductive layer 104 and the substrate 101 in the first area a is 2-4 μm.

Optionally, the third conductive layer 106 is a continuous layer within the first region a, the second region B, and the third region C; in the first region a and the third region C, the third conductive layer 106 covers the second planarization layer 105. The continuous third conductive layer 106 can be formed by film formation on the surfaces of the second planarizing layer 105 and the groove 107.

Referring to fig. 3, fig. 3 is a schematic cross-sectional view illustrating a position of a frame of the display panel 200 according to the comparative embodiment of the present application. In this comparative embodiment, the display panel 200 is provided with a first conductive layer 202 and a first planarizing layer 203 side by side on a substrate 201 in a first region a, a second conductive layer 204 is stacked on the first conductive layer 202 and the first planarizing layer 203, a second planarizing layer 205 is disposed on the second conductive layer 204 and the first planarizing layer 203, and a third conductive layer 206 is provided on the second planarizing layer 205. In the second region B and the third region C, other structures of the display panel 200 of the comparative embodiment and the display panel 100 of the embodiment of the present application may be the same, and are not described herein again.

It is understood that the first planarization layer 203 has a residue on the side of the first region a close to the second region B, the residue being located in the first through groove of the first conductive layer 202 and connected to the substrate 201. In the process of forming the first planarization layer 203, the first planarization layer 203 may be patterned by etching, so that two grooves are formed in the first planarization layer 203, one of the grooves is located in the second region B, and the other groove is located in the first region a. Thereafter, in the process of forming the second conductive layer 204, the first planarizing layer 203 has a residue in the first region a, and the height of the residue is higher than that of the first conductive layer 202. Therefore, the side of the second conductive layer 204 close to the first planarizing layer 203 warps upward when film formation is performed, and thus the distance between the second conductive layer 204 and the third conductive layer 206 is relatively short. After a long period of use, a blast may occur between second conductive layer 204 and third conductive layer 206, causing the two signals to short together, indicating an anomaly.

Referring to fig. 4, fig. 4 is a schematic flow chart illustrating a manufacturing method of a display panel according to an embodiment of the present application. Referring to fig. 5a to 5e, fig. 5a to 5e are schematic structural diagrams of steps of a manufacturing method of a display panel according to an embodiment of the present application. The application provides a manufacturing method of a display panel, which comprises the following steps:

step S101: a substrate 301 is provided and a first conductive film layer 302 is formed on the substrate 301, as shown in fig. 5 a.

Step S102: the first conductive film layer 302 is patterned to form a first conductive portion 3021 and a second conductive portion 3022 separated by a first through trench 302a, as shown in fig. 5b, two separate conductive portions may be formed by etching the first through trench 302a on the first conductive film layer 302.

Step S103: a first planarizing film layer 303a is formed over the substrate 301 and the first and second conductive portions 3021 and 3022, as shown in fig. 5 c.

Step S104: the first planarization film layer 303a is patterned to remove at least a first portion of the first planarization film layer 303a located in the first through trench 302a and at least a second portion connected to the first portion and located on the first conductive portion 3021, so as to form the first planarization layer 303 at least partially located on the second conductive portion 3022, as shown in fig. 5d, a portion of the first planarization film layer 303a may be removed by etching, and the first planarization film layer on the side of the first conductive portion 3021 close to the second conductive portion 3022 may be removed in this step.

Step S105: the second conductive film layer 304 is formed on the substrate 301, the first planarizing layer 303 and the first conductive portion 3021, and as shown in fig. 5e, by removing the first planarizing film layer on the side of the first conductive portion 3021 close to the second conductive portion 3022 in the previous step, the second conductive film layer 304 is prevented from warping upward on the side close to the second conductive portion 3022 when the second conductive film layer 304 is formed on the first conductive portion 3021.

Therefore, by the manufacturing method of the display panel according to the embodiment, it is possible to provide an advantage for preventing the further conductive layer from being too close to the second conductive film layer 304 during the subsequent manufacturing of the display panel. Therefore, the probability of short circuit and explosion damage of the two conductive layers in the finally manufactured display panel can be reduced.

Further, referring to fig. 6, fig. 6 is a schematic flow chart illustrating a manufacturing method of a display panel according to another embodiment of the present application. Referring to fig. 7a to 7d, fig. 7a to 7d are schematic structural views of steps of a manufacturing method of a display panel according to another embodiment of the present disclosure. Steps S201 to S205 in this embodiment are the same as steps S101 to S105 in the previous embodiment, and after step S205, the method further includes:

step S206: on the basis of fig. 5e, the second conductive film 304 is patterned to form a third conductive part 3041 on the first conductive part 3021 and a fourth conductive part 3042 on the first planarization layer 303, wherein the fourth conductive part 3042 is separated from the second conductive part 3022 by the first planarization layer 303, and as shown in fig. 7a, the second conductive film can be divided into two conductive parts by etching.

Step S207: a second planarization film 305a is formed on the substrate 301, the first planarization layer 303, the third conductive part 3041 and the fourth conductive part 3042, as shown in fig. 7 b.

Step S208: patterning the second planarization film layer 305a to expose a portion of the substrate 301 corresponding to the first through groove 302a, thereby forming a second planarization layer 305; a first portion of the second planarization layer 305 is located on the third conductive part 3041, and a second portion of the second planarization layer 305 is located on the fourth conductive part 3042; as shown in fig. 7c, a side surface of the first conductive portion 3021 facing the second conductive portion 3022 and the third conductive portion 3041 may be divided into two parts by etching the second planarization film layer 305a, and the two parts respectively cover the third conductive portion 3041 and the fourth conductive portion 3042. In other embodiments, a side surface of the first conductive part 3021 facing the second conductive part 3022 may be in contact with the second planarizing layer 305.

Step S209: a third conductive layer 306 is formed on the substrate 301 and the second planarization layer 305, wherein at least a portion of the third conductive layer 306 is in contact with a portion of the substrate 301 corresponding to the first through groove 302a, as shown in fig. 7d, the third conductive layer 306 is prevented from being too close to the third conductive portion 3041 and the fourth conductive portion 3042, thereby preventing the display panel from being damaged by explosion due to short circuit.

Optionally, in step S104, a surface of the second conductive part 3022 facing the first conductive part 3021 is contacted with the first planarization layer 303, so as to avoid short circuit caused by too close distance between the second conductive part 3022 and the third conductive layer 306.

Optionally, in step S208, at least a portion of the second planarization layer 305 covers the first planarization layer 303, so as to avoid short circuit caused by the close distance between the second conductive part 3022 and the third conductive layer 306.

Alternatively, in step S208, a surface of the first conductive portion 3021 facing the second conductive portion 3022 is brought into contact with the third conductive portion 3041, and a surface of the third conductive portion 3041 facing the second conductive portion 3022 is brought into contact with the second planarization layer 305, that is, the first conductive portion 3021, the third conductive portion 3041 and the second planarization layer 305 are formed on a side facing the second conductive portion 3022 in a stacked manner in this order, so that the third conductive portion 3041 is prevented from warping upward facing the second conductive portion 3022, and is separated from the third conductive layer 306 by the second planarization layer 305, so that the third conductive portion 3041 is not easily shorted with the third conductive layer 306.

Optionally, in step S208, a first portion of the second planarization layer 305 is located above the third conductive portion 3041, and the first portion of the second planarization layer 305 is further in contact with the substrate 301, so as to ensure that the second planarization layer 305 covers the third conductive portion 3041 and the first conductive portion 3021, and the third conductive portion 3041 has a sufficient distance from the third conductive layer 306.

It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.

Claims (10)

1. A display panel comprises a substrate, a first conductive layer, a first planarization layer, a second conductive layer, a second planarization layer and a third conductive layer, wherein the first conductive layer, the first planarization layer, the second conductive layer, the second planarization layer and the third conductive layer are sequentially arranged on the substrate, the display panel is provided with a display area and a non-display area, and the display panel is characterized in that,

the non-display area comprises a first area, a second area and a third area which are sequentially connected, the first conducting layer comprises a first conducting part and a second conducting part which are respectively arranged in the first area and the third area, the second conducting layer comprises a third conducting part and a fourth conducting part which are respectively arranged in the first area and the third area, the fourth conducting part and the second conducting part are isolated by the first planarization layer, the third conducting part is stacked on the first conducting part, and one side surface of the first conducting part facing the second conducting part is in contact with the third conducting part and/or the second planarization layer;

the second area is provided with a groove; in the second region, at least a part of the third conductive layer is in contact with the substrate.

2. The display panel according to claim 1, wherein the first conductive layer has a first through-slot formed therein, and the first through-slot is partially located in the second region and partially extends into the first region and the third region; and/or

The surface of one side, facing the first conductive part, of the second conductive part is in contact with the first planarization layer; and/or

In the third area, at least part of the second planarization layer covers the first planarization layer.

3. The display panel according to claim 1, wherein the first planarization layer defines a second through groove, and the second through groove is located in the first region and the second region; and/or

A third through groove is formed in the second planarization layer and is located in the second area; preferably, in the first region, a side surface of the first conductive portion facing the second conductive portion is in contact with the third conductive portion, and a side surface of the third conductive portion facing the second conductive portion is in contact with the second planarization layer.

4. The display panel according to claim 1, wherein in the first region, the second planarization layer is located over the third conductive portion, and the second planarization layer further has a part of a structure in contact with the substrate.

5. The display panel according to claim 1, wherein the second region has a width of 5 to 7 μm in a direction along the first region toward the third region; and/or

The width of the first conducting layer in the first region along the direction from the first region to the third region is 5-7 μm; and/or

The maximum distance between the second conductive layer and the substrate in the first region is 2-4 μm.

6. The display panel according to any one of claims 1 to 5, wherein the third conductive layer is a continuous layer in the first region, the second region, and the third region; in the first region and the third region, the third conductive layer covers the second planarization layer.

7. A method for manufacturing a display panel having a display area and a non-display area, the method comprising:

providing a substrate, and forming a first conductive film layer on the substrate;

patterning the first conductive film layer to form a first conductive part and a second conductive part separated by a first through groove;

forming a first planarization film layer on the substrate and the first and second conductive portions;

patterning the first planarization film layer to remove at least a first portion of the first planarization film layer located in the first through groove and at least a second portion connected to the first portion and located on the first conductive portion, thereby forming a first planarization layer located at least partially on the second conductive portion; and

and forming a second conductive film layer on the substrate, the first planarization layer and the first conductive part.

8. The method for manufacturing a display panel according to claim 7, further comprising:

patterning the second conductive film layer to form a third conductive portion on the first conductive portion and a fourth conductive portion on the first planarization layer, wherein the fourth conductive portion is isolated from the second conductive portion by the first planarization layer;

forming a second planarizing film layer on the substrate, the first planarizing layer, the third conductive portion, and the fourth conductive portion;

patterning the second planarization film layer to expose a part of the substrate corresponding to the first through groove, so as to form a second planarization layer; a first portion of the second planarization layer is on the third conductive portion and a second portion of the second planarization layer is on the fourth conductive portion; wherein a side surface of the first conductive portion facing the second conductive portion is in contact with the third conductive portion and/or the second planarization layer; and

and forming a third conducting layer on the substrate and the second planarization layer, wherein at least part of the third conducting layer is in contact with a part of the substrate corresponding to the first through groove.

9. The method for manufacturing a display panel according to claim 7,

in the step of patterning the first planarization film layer, a side surface of the second conductive part facing the first conductive part is in contact with the first planarization layer.

10. The method for manufacturing a display panel according to claim 8,

in the step of patterning the second planarization film layer, at least part of the structure of the second planarization layer covers the first planarization layer; and/or

In the step of patterning the second planarization film layer, a side surface of the first conductive portion facing the second conductive portion is brought into contact with the third conductive portion, and a side surface of the third conductive portion facing the second conductive portion is brought into contact with the second planarization layer; and/or

In the step of patterning the second planarization film layer, the first portion of the second planarization layer is located above the third conductive portion, and the first portion of the second planarization layer is also in contact with the substrate.

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