CN115834277B - Airborne isolation RS485 communication board card based on MiniVPX architecture - Google Patents
Airborne isolation RS485 communication board card based on MiniVPX architecture Download PDFInfo
- Publication number
- CN115834277B CN115834277B CN202211126309.6A CN202211126309A CN115834277B CN 115834277 B CN115834277 B CN 115834277B CN 202211126309 A CN202211126309 A CN 202211126309A CN 115834277 B CN115834277 B CN 115834277B
- Authority
- CN
- China
- Prior art keywords
- communication
- data
- state
- module
- board card
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides an onboard isolation RS485 communication board card based on a MiniVPX framework, belongs to the field of RS485 bus communication under an onboard test environment, and aims to solve the problems of miniaturization, high integration, configurable communication protocol and the like of an onboard test system, and the technical scheme provided by the invention is as follows: an onboard isolated RS485 communication board card based on MiniVPX architecture, the board card comprising: front panel, FPGA module, power module, a plurality of RS485 communication chips, flash memory, E 2 PROM memory, J20J bus connector, JTAG interface, power backplane connector, at least one MiniVPX backplane data connector; the FPGA module controls the RS485 module to realize the function of configuring the communication protocol; the power module supplies power for the whole communication board card; the RS485 communication chip adopts an RS485 communication chip with an isolated power supply; the invention is suitable for the research field of the airborne isolation RS485 bus communication board card based on the MiniVPX framework and the application field of RS485 bus communication.
Description
Technical Field
The invention relates to the field of RS485 bus communication under an airborne test environment, in particular to an airborne isolation RS485 bus communication board card based on a MiniVPX architecture.
Background
With the rapid development of the aviation industry in China, the test flight detection of an aircraft in the process of aircraft research and development and manufacturing is an irreplaceable important means for aircraft design and performance index verification. The airborne test system is an important means for acquiring test flight data, and the problems of high volume occupation ratio, few test parameter types, insufficient data processing workload and the like of the existing airborne test system technology still need to be solved, so that the technical field needs to save the construction cost of the system, and the efficient and reliable test system for providing powerful test guarantee for the test flight progress and the efficiency thereof is also needed.
At present, domestic miniaturized airborne equipment mostly adopts foreign import, products related to MiniVPX architecture design are few, and even if imported miniaturized test equipment such as miniR700 of Ampex company in the United states does not make relevant standards, the universality is poor and the universality is not strong. The MiniVPX can provide a standard modularized electronic system hardware solution for platforms such as missile-borne, unmanned aerial vehicles, small satellites and the like by virtue of the superior characteristics of higher integration level, higher universality, smaller volume and the like. At present, the technology of the MiniVPX standard embedded system is not applied to high-speed airborne test equipment at home.
The field buses currently used internationally are numerous in names, such as PROFIBUS, INTERBUS, CAN buses, but the system has relatively high manufacturing cost and is inconvenient to maintain, and the RS485 bus is used as a data bus commonly used in the field of airborne testing, so that the system has the characteristics of simple structure, mature technology, low manufacturing cost, convenient maintenance and the like, and is widely applied.
A new technology is needed to overcome the problems of miniaturization, high integration, configurable communication protocol and the like of an airborne test system based on an RS485 bus communication board card of a MiniVPX architecture.
Disclosure of Invention
In order to solve the defects in the prior art, the invention provides an airborne isolation RS485 communication board card based on a MiniVPX architecture.
The method is realized by the following technical scheme:
an on-board isolation RS485 communication board card based on MiniVPX framework, which is characterized in that the RS485 communication board card comprises: front panel, FPGA module, power module, a plurality of RS485 communication chips, flash memory, E 2 PROM memory, J20J bus connector, JTAG interface, power backplane connector, at least one MiniVPX backplane data connector;
the MiniVPX backboard data connector is connected with a PCIe bus;
the front panel is positioned at the front end of the communication board, and the J20J bus connector and the JTAG interface are both fixed on the front panel;
the power back board connector and the at least one MiniVPX back board data connector are fixed at the rear end of the board card;
the power module is fixed at the upper right corner of the board card and is adjacent to the power backboard connector; the power supply module is used for converting the power supply output by the power supply backboard connector into a working power supply and providing the working power supply for the FPGA module, the plurality of RS485 communication chips, the Flash memory and the E 2 The PROM memory provides a working power supply;
the FPGA module is positioned at the central position of the board, and is used for controlling the working states of a plurality of RS485 communication chips, and also used for controlling the Flash memory and the E 2 Reading and writing data by the PROM memory;
the plurality of RS485 communication chips are located on one side, close to the front panel, of the board card, the plurality of RS485 communication chips are connected with an external RS485 bus through a J20J bus connector, and the plurality of RS485 communication chips are connected with the FPGA.
Further, a preferred embodiment is provided, wherein the width of the RS485 communication board card is 7.62cm, the depth is 10.16cm, and the height is 1.10cm.
Further, a preferred implementation manner is provided, the RS485 communication chips are provided with the RS485 communication chips with isolated power supplies, each RS485 communication chip is further provided with an operating state indicator lamp for displaying the operating state of the RS485 communication chip, and the operating state indicator lamps are embedded and fixed on the front panel.
Further, there is provided a preferred embodiment, the communication board further includes a temperature sensor, and the temperature sensor is configured to detect an operating temperature of the communication board, and send the temperature information to the FPGA module.
Further, there is provided a preferred embodiment, the power module includes a primary power source and two secondary power sources, the primary power source is used for converting a power signal input by the power backplane connector into an RS485 communication chip and an E 2 The working power supply of the PROM memory comprises a secondary power supply for converting the power supply of the primary power supply output end into working power supplies of 1.0V and 1.8V, and a secondary power supply for converting the power supply of the primary power supply output end into working power supplies of 3.3V and 2.5V.
Further, a preferred implementation manner is provided, the FPGA realizes RS485 communication logic design through an RS485 communication chip, and the RS485 communication logic comprises a DMA-peripheral interface module, a peripheral-DMA module, an AXI Stream bus, a Tx FIFO buffer area, a serial transmission module, a timeout judging module and an Rx FIFO buffer area;
the RS485 communication logic is controlled by the FPGA module to realize the receiving and transmitting of data, the whole communication flow follows a serial bus protocol, wherein one frame of a communication signal comprises a frame head, data and CRC check sum frame tail, in the RS485 communication logic, a DMA-peripheral interface module and a peripheral-DMA module are connected with an AXI DMA, the communication signal is converted into a universal peripheral interface form from an AXI Stream bus form and is transmitted to a Tx FIFO, a serial transmitting module converts 8-bit parallel data in the Tx FIFO into serial data, then the serial data is output and transmitted to a board card, a serial receiving module detects the received data in a set time, a timing module is used for timing, a logic timeout judging module is a module for judging the set time, the serial data is converted into 8-bit parallel data through the serial receiving module and is transmitted to the Rx FIFO, and then the communication signal is transmitted to the AXI DMA through the peripheral-DMA interface module, so that the receiving and transmitting and receiving of primary data are completed.
Further, a preferred embodiment is provided, wherein a status parameter register, a register interface and a timing module are also arranged in the logic of the RS485 communication module;
the state parameter register is configured by the FPGA through a register interface and comprises transmission rate, frame length and timing time;
the timing module is interconnected with the register interface for specifying data transmission times.
Further, a preferred embodiment is provided, where the RS485 communication logic further includes a protocol configuration register, the FPGA writes configuration parameters of an upper layer protocol into the register, and performs corresponding operations of frame de-framing and framing according to a protocol transmission format in the register, so as to implement a function of editing and outputting content in a signal source output mode.
Further, a preferred embodiment is provided, wherein the working state of the serial sending module in the RS485 communication logic is as follows:
an idle state, detecting a data storage state of the Tx FIFO, and jumping to a frame header sending state when the Tx FIFO is full of one frame of data;
the frame header sending state is used for sending frame header data, and after the sending is completed, the frame header sending state is skipped to the data sending state;
a data sending state for sending data until the sending quantity condition is met, and jumping to a CRC (cyclic redundancy check) sending state;
a CRC check state is sent and used for sending CRC check data, and if the check fails, the idle state is skipped; if the verification is successful, jumping to a transmitting frame tail state;
and the frame tail state is used for transmitting frame tail data, and after the transmission is completed, the frame tail state is jumped to the idle state.
Further, a preferred embodiment is provided, wherein the working state of the serial receiving module in the RS485 communication logic is as follows:
an idle state, i.e., a skip to a frame header judgment state when the start bit "0" of the received data is detected and not timed out;
the frame head judging state is used for judging the frame head state, if the frame head is not detected, the frame head is jumped to the data discarding state, and if the frame head is detected, the frame head is jumped to the data receiving state of the first byte;
the method comprises the steps of receiving a first byte data state, wherein the first byte data state is used for receiving first byte data, and jumping to the data receiving state after the first byte data is received;
a received data state for receiving data, if the received data quantity is satisfied, jumping to a frame tail judging state;
the frame tail judging state is used for detecting frame tail data, if the frame tail is not detected, jumping to the data discarding state, and if the frame tail is detected, jumping to the idle state;
and the data discarding state is used for clearing the data, and the data discarding state is skipped to the idle state after the data discarding is finished.
The beneficial effects of the invention are as follows:
1. the invention is based on MiniVPX framework, the board has the characteristic of small size, adopts 8-channel design, and has the characteristic of high integration;
2. the invention adopts the RS485 communication chip integrated with the isolation power supply, and the design is used on the board card of the MiniVPX framework, so that the design of the isolation power supply can be avoided, and the space is saved;
each channel of the RS485 communication board card can be independently acquired, and the self-checking function of the communication board card can be completed by switching the acquisition/signal source modes;
the RS485 communication board card adopts an FPGA as a control module core to complete framing bottom logic, and the function of configuring a communication protocol is completed through logic design;
the RS485 communication board card is provided with a temperature sensor, so that temperature monitoring can be performed in real time for evaluating the working health state of the whole system;
and PCIe high-speed communication is adopted for the data interaction of the back plate of the RS485 communication board card, so that the transmission efficiency is higher.
Drawings
Fig. 1 is a schematic diagram of a communication signal design of a back board of an RS485 communication board according to the eleventh embodiment;
fig. 2 is a schematic diagram of the connection relationship of the RS485 communication board card according to the eleventh embodiment;
fig. 3 is a schematic diagram of an RS485 communication board layout according to the eleventh embodiment;
FIG. 4 is a schematic diagram of a power tree structure in a power module according to an eleventh embodiment;
fig. 5 is a schematic diagram of an RS485 communication module according to the eleventh embodiment;
FIG. 6 is a block diagram of a PCIe DMA core referred to in embodiment eleven;
fig. 7 is a schematic diagram of a front panel of an RS485 communication board according to the eleventh embodiment;
fig. 8 is a logic block diagram of an RS485 communication module according to the eleventh embodiment;
fig. 9 is a state transition diagram of a serial transmission module mentioned in the eleventh embodiment;
fig. 10 is a state transition diagram of a serial reception module mentioned in the eleventh embodiment.
Detailed Description
In order to make the advantages and benefits of the technical solution provided by the present invention more apparent, the technical solution provided by the present invention will now be described in further detail with reference to the accompanying drawings, in which:
embodiment one: the embodiment provides an on-board isolation RS485 communication board card based on MiniVPX framework, RS485 communication board card includes: front panel, FPGA module, power module, a plurality of RS485 communication chips, flash memory, E 2 PROM memory, J20J bus connector, JTAG interface, power backplane connector, at least one MiniVPX backplane data connector;
the MiniVPX backboard data connector is connected with a PCIe bus;
the front panel is positioned at the front end of the communication board, and the J20J bus connector and the JTAG interface are both fixed on the front panel;
the power back board connector and the at least one MiniVPX back board data connector are fixed at the rear end of the board card;
the power module is fixed at the upper right corner of the board card and is adjacent to the power backboard connector; the power supply module is used for converting the power supply output by the power supply backboard connector into a working power supply and providing the working power supply for the FPGA module, the plurality of RS485 communication chips, the Flash memory and the E 2 The PROM memory provides a working power supply;
the FPGA module is positioned at the central position of the board, and is used for controlling the working states of a plurality of RS485 communication chips, and also used for controlling the Flash memory and the E 2 Reading and writing data by the PROM memory;
the plurality of RS485 communication chips are located on one side, close to the front panel, of the board card, the plurality of RS485 communication chips are connected with an external RS485 bus through a J20J bus connector, and the plurality of RS485 communication chips are connected with the FPGA.
Embodiment two: the embodiment is further defined on the airborne isolation RS485 communication board card based on the MiniVPX architecture provided in the first embodiment, wherein the width of the RS485 communication board card is 7.62cm, the depth is 10.16cm, and the height is 1.1cm.
Embodiment III: the present embodiment is a further limitation of the airborne isolation RS485 communication board card based on the MiniVPX architecture provided in the first embodiment, the RS485 communication chip is an RS485 communication chip with an isolated power supply, each RS485 communication chip is further provided with a working status indicator lamp, and the working status indicator lamps are used for displaying the working status of the RS485 communication chip and are embedded and fixed on the front panel.
Embodiment four: the embodiment is further defined by the on-board isolation RS485 communication board card based on the MiniVPX architecture provided in the first embodiment, where the communication board card further includes a temperature sensor, and the temperature sensor is configured to detect an operating temperature of the communication board card and send the temperature information to the FPGA module.
Fifth embodiment: the present embodiment is further defined by the on-board isolated RS485 communication board card based on the MiniVPX architecture provided in the first embodiment, where the power module includes a primary power supply and two secondary power supplies, where the primary power supply is configured to convert a power signal input by a power backplane connector into an RS485 communication chip and an E 2 The working power supply of the PROM memory comprises a secondary power supply for converting the power supply of the primary power supply output end into working power supplies of 1.0V and 1.8V, and a secondary power supply for converting the power supply of the primary power supply output end into working power supplies of 3.3V and 2.5V.
Embodiment six: the implementation manner is further defined on the airborne isolation RS485 communication board card based on the MiniVPX architecture, the FPGA realizes RS485 communication logic design through an RS485 communication chip, and the RS485 communication logic comprises a DMA-peripheral interface module, a peripheral-DMA module, an AXI Stream bus, a Tx FIFO buffer area, a serial transmission module, a timeout judgment module and an Rx FIFO buffer area;
the RS485 communication logic is controlled by the FPGA module to realize the receiving and transmitting of data, the whole communication flow follows a serial bus protocol, wherein one frame of a communication signal comprises a frame head, data and CRC check sum frame tail, in the RS485 communication logic, a DMA-peripheral interface module and a peripheral-DMA module are connected with an AXI DMA, the communication signal is converted into a universal peripheral interface form from an AXI Stream bus form and is transmitted to a Tx FIFO, a serial transmitting module converts 8-bit parallel data in the Tx FIFO into serial data, then the serial data is output and transmitted to a board card, a serial receiving module detects the received data in a set time, a timing module is used for timing, a logic timeout judging module is a module for judging the set time, the serial data is converted into 8-bit parallel data through the serial receiving module and is transmitted to the Rx FIFO, and then the communication signal is transmitted to the AXI DMA through the peripheral-DMA interface module, so that the receiving and transmitting and receiving of primary data are completed.
Embodiment seven: the implementation manner is further defined on the airborne isolation RS485 communication board card based on the MiniVPX architecture provided in the sixth implementation manner, and a status parameter register, a register interface and a timing period timing module are further provided in the RS485 communication module logic;
the state parameter register is configured by the FPGA through a register interface and comprises transmission rate and frame length timing time setting;
the timing module is interconnected with the register interface for specifying data transmission times.
Embodiment eight: the present embodiment is further defined by the airborne isolation RS485 communication board card based on the MiniVPX architecture provided in the sixth or seventh embodiment, where the RS485 communication logic further includes a protocol configuration register, the FPGA writes configuration parameters of an upper layer protocol into the register, and performs corresponding frame-removing and framing operations according to a protocol transmission format in the register, so as to implement a function of editing output content in a signal source output mode.
Embodiment nine: the present embodiment is further defined on the airborne isolation RS485 communication board card based on the MiniVPX architecture provided in the seventh embodiment, and the working state of the serial sending module in the RS485 communication logic is as follows:
an idle state, detecting a data storage state of the Tx FIFO, and jumping to a frame header sending state when the Tx FIFO is full of one frame of data;
the frame header sending state is used for sending frame header data, and after the sending is completed, the frame header sending state is skipped to the data sending state;
a data sending state for sending data until the sending quantity condition is met, and jumping to a CRC (cyclic redundancy check) sending state;
a CRC check state is sent and used for sending CRC check data, and if the check fails, the idle state is skipped; if the verification is successful, jumping to a transmitting frame tail state;
and the frame tail state is used for transmitting frame tail data, and after the transmission is completed, the frame tail state is jumped to the idle state.
Embodiment ten: the present embodiment is further defined on the airborne isolation RS485 communication board card based on the MiniVPX architecture provided in the seventh embodiment, and the working state of the serial receiving module in the RS485 communication logic is as follows:
an idle state, i.e., a skip to a frame header judgment state when the start bit "0" of the received data is detected and not timed out;
the frame head judging state is used for judging the frame head state, if the frame head is not detected, the frame head is jumped to the data discarding state, and if the frame head is detected, the frame head is jumped to the data receiving state of the first byte;
the method comprises the steps of receiving a first byte data state, wherein the first byte data state is used for receiving first byte data, and jumping to the data receiving state after the first byte data is received;
a received data state for receiving data, if the received data quantity is satisfied, jumping to a frame tail judging state;
the frame tail judging state is used for detecting frame tail data, if the frame tail is not detected, jumping to the data discarding state, and if the frame tail is detected, jumping to the idle state;
and the data discarding state is used for clearing the data, and the data discarding state is skipped to the idle state after the data discarding is finished.
Embodiment eleven: the embodiment provides a specific embodiment for the airborne isolation RS485 communication board card based on the MiniVPX architecture, and is also used for explaining the second embodiment to the tenth embodiment, specifically:
the invention provides an onboard isolation RS485 communication board card based on a MiniVPX framework, which is suitable for a test system of the MiniVPX framework, and is used as a functional board card of the system to complete the receiving and transmitting functions of RS485 bus data.
The onboard isolation RS485 communication board card comprises the following modules: the device comprises a control module taking an FPGA as a core, a power module, an RS485 communication module taking an RS485 communication chip as a core and a PCIe communication backboard module taking XDMA as a base. The front panel portion of the communication board provides 8 indicator lights for indicating the operational status of each bus lane. The method is characterized in that a J20J connector is adopted as an RS485 bus connector to realize connection with an RS485 bus, the front end of a board card is an interface for interaction between a communication board card and the outside, a backboard is connected with an onboard test equipment chassis through a specific data connector, a power module is designed at the upper right corner of the communication board card and is connected with the power backboard connector, an FPGA is designed at the center of the communication board card and is used as a core controller, a DS18B20 temperature sensor can be controlled to monitor the temperature of the board card in real time, initializing configuration information in Flash can be read to configure the board card after the communication board card is electrified and started, and ID and working state information of the board card can be stored in E when the board card begins working 2 In the PROM, the upper computer software can conveniently perform board card identification and management operation, the connection relation of the RS485 communication board card is shown in figure 2, and the board card layout is shown in figure 3.
(1) The FPGA control module mainly performs the functions of controlling the RS485 communication transceiver chip, enabling each channel to independently realize the functions of sampling bit rate of RS485 signals, editing synchronous signals, switching acquisition modes and signal source output modes, realizing the function of configuring a communication protocol, and simultaneously enabling the FPGA to provide physical acquisition for the RS485 communication chipClock, completing control of collection rate of each channel, realizing function of editing content of each physical channel under signal source output mode and mode switching of each physical channel supporting synchronous and asynchronous, flash storing initialization file of FPGA, E 2 The PROM stores the ID and configuration information of the board card so as to inquire the working state of the board card by the upper computer, is connected with the DS18B20 digital temperature sensor, monitors the temperature condition of the communication board card in real time, has the measuring range of-55-125 ℃ and the measuring precision of 0.5 ℃, can monitor the environmental temperature of the case, and is convenient for evaluating the working health state of the whole system.
The RS485 communication board card realizes the receiving and sending of RS485 signals, each channel independently realizes the functions of sampling bit rate and editing synchronous signals of the RS485 signals, each physical channel edits output contents in a signal source output mode, the editing range comprises a self-defined Label domain, a data length domain and a data segment, and the rest data contents support automatic filling. The FPGA is used as a core of the main control module to realize the function of configuring the communication protocol, and the FPGA is used for realizing framing and de-framing bottom layer to realize logic, thus completing the function of configuring the communication protocol.
(2) The power module is mainly used for supplying power to each chip and PCIe high-speed data transmission port on the communication board card, in the design process of the board card, the voltage types involved are more, meanwhile, the voltage ripple noise requirement of the high-speed receiving and transmitting port is higher, the height of the board card is limited, so that the occupied area of the power module on the board card is larger, and the 1210-packaging-type large capacitor is used for filtering so as to provide a better power supply environment for keeping the voltage stable. The power module is responsible for providing the voltage required by each chip on the whole board card and mainly comprises an FPGA chip and an E 2 PROM, flash, RS485 communication chip, the power supply voltage required by the FPGA on the board card is 1.8V, 1.2V, 1.0V and 3.3V, and the power supply voltage adopted by flash is 3.3V.
The power supply system of the RS485 communication board card consists of one LTM4600, two LTMs 4616 and two TPS74401, wherein the LTM4600 is used for converting 12V voltage of the backboard into 5V voltage and is used as a primary power supply of the communication board card; LTM4616 is a single-input and double-output power chip, and respectively completes the functions of converting 5V into 1.8V, 2.5V,5V into 3.3V and 1.0V, and is used as a secondary power supply of the RS485 communication board card; TPS74401 provides a better ripple power supply for powering PCIe high speed data transfer ports. As shown in fig. 4, the power tree structure of the RS485 bus communication board card is shown.
In the power tree structure diagram, four primary power supplies, namely LTM4600 power supply parts, are RS485 communication voltage VDD, E2PROM voltage and input voltage of two LTM4616, two secondary power supplies, namely two LTM4616, are mainly powered by special pins of an FPGA, flash and a clock chip, power quality is improved by TPS74401, and power is supplied to a high-speed transmission port of the FPGA.
(3) The RS485 communication module is composed of 8 RS485 communication chips, an isolation power supply is required to be designed for the common RS485 chip, the design for miniaturization is extremely unfavorable, and in the invention, because the size of a board card is small, the power supply system is complex, the channel number integration level is high, and the like, an isolation power supply module which works independently is difficult to design, so that the TD (H) 541S485S chip is adopted, and the chip is a half-duplex enhanced RS485 isolation transceiver with the isolation power supply, the conversion between an acquisition mode and a signal source mode can be realized, and the communication rate is up to 20Mbps. Besides the self-contained isolation power supply, the internal part of the device also comprises a signal isolator which can inhibit interference to a greater extent, and the isolated signal is converted into an RS485 signal meeting the specification through a signal converter and then is sent out.
When the bus is in an idle state, the A is pulled up by an isolation power supply provided by a VISOIN pin of the RS485 transceiver chip, the B end is connected with the ground, and a pull-down resistor is added, so that the continuous output of high level can be ensured when the bus is idle, and in UART communication, if a receiving end receives an output low level, the UART communication is started. And a diode is added between A, B, so that the surge resistance of the circuit is improved, the stability of a bus is effectively maintained through the design of the circuit outside the chip, the chip is protected from being burnt out by overcurrent TD (H) 5414855, and the design schematic diagram of the RS485 communication module is shown in figure 5.
Because each RS485 communication chip channel is mutually independent, each RS485 communication chip independently completes the receiving and transmitting function, adopts one path of RS485 channel as a signal source to test whether the receiving of other RS485 channels is normal, and conversely, can also test whether the transmitting function of the RS485 channel can work normally to complete the self-checking function of the RS485 communication board card.
(4) The data communication of the RS485 communication board card and the main control board card adopts an SMBus bus and a PCIe bus, wherein the data acquisition and the data transmission are mainly completed through XDMA-based PCIe communication, the control instruction and the rest auxiliary data transmission adopt SMBus for communication, and the RS485 communication board card introduces PCIe signals and SMBus signals into a CPU of the main control board card through a connecting slot of a backboard for data analysis, transfer and storage operation.
As shown in FIG. 6, a block diagram of the architecture of a PCIe DMA core is presented. After the FPGA is configured in an instantiating way, the FPGA only needs to perform interrupt triggering operation on the HOST HOST, all DMA operations are completely realized by the HOST HOST through PCIe configuration of an XDMA register, further data communication between an RS485 communication board card and a main control module is performed, the RS485 communication board card converts acquired data information into PCIe through an XDMA core and transmits the PCIe to the main control module through a backboard, and meanwhile, the main control board card transmits data to be transmitted to the communication board card through the XDMA core.
In the transmission process, the DMA needs to know the data flow direction, the PCIe maps the address space of the RS485 communication board card to a section of address space in the main control board card through the BAR space, so that the corresponding BAR space is directly operated in the main control board card, and the mapping relation needs a host to configure the BAR space register of the RS485 communication board card to allocate the address space and the length.
In addition, ports of the RS485 bus communication board card, which are interacted with the outside, are all arranged in a front panel of the board card, and the board card comprises a double-color LED indicator lamp for indicating the working state of each channel, a JTAG interface and a J20J type connector connected with the RS485 bus, and the specific layout is shown in FIG. 7.
The LED double-color indicator lamp is arranged above the board card, corresponds to the indicator lamp positions of other board cards in the case, is powered by 2.5V voltage, and is a double-seat indicator lamp, each LED corresponds to the working state of one channel, and each LED is controlled by an FPGA pin. The connector with the model J20J below the LED meets the standard of a space connector, adopts a twist needle structure, has a distance of 0.95mm and a row spacing of 1.01mm, is a head-mounted needle, and adopts the model J20J-25TJW-TH.
(5) The logic control of the RS485 communication module realizes the receiving and transmitting of data, the communication flow follows a serial bus protocol, a frame head, data and CRC check sum frame tail are contained in one frame, in the logic of the RS485 communication module, the DMA-peripheral interface module and the peripheral-DMA module are responsible for connecting AXI DMA, the communication signal is converted into a universal peripheral interface form from an AXI Stream bus form, the data interaction is carried out with Tx FIFO and Rx FIFO, and the logic block diagram of the RS485 communication module is shown as 8.
In the logic of the RS485 communication module, the DMA-peripheral interface module and the peripheral-DMA module are responsible for connecting AXI DMA, converting communication signals from an AXI Stream bus form into a universal peripheral interface form, and carrying out data interaction with Tx FIFO and Rx FIFO. The serial transmitting module converts 8-bit parallel data in the Tx FIFO into serial data and outputs the serial data, the serial receiving module needs to detect the received data in a specified time, and converts the serial data into 8-bit parallel data and transmits the 8-bit parallel data to the Rx FIFO, and the overtime judging module is a module for judging the specified time. Status parameter registers in the RS485 communication logic module, such as timing time, frame length, transmission rate and FIFO data volume, are set by the FPGA through a register interface. Fig. 9 and 10 show state transition flows of the serial transmitting module and the serial receiving module, respectively.
In the signal source output mode, the RS485 communication module supports the function of editing output content, the editing range comprises a custom Label domain, a data length domain and a data segment, other data content supports automatic replenishment, a protocol configuration register is required to be designed for completing the function, the FPGA writes configuration parameters of an upper layer protocol into the register, and then corresponding frame-decoding and framing operations are carried out according to a protocol transmission format in the register, so that the function of editing output content in the signal source output mode is realized.
Claims (10)
1. An on-board isolation RS485 communication board card based on MiniVPX framework, which is characterized in that the RS485 communication board card comprises: front panel, FPGA module, power module, a plurality of RS485 communication chips, flash memory, E 2 PROM memory, J20J bus connector, JTAG interface, power backplane connector, at least one MiniVPX backplane data connector;
the MiniVPX backboard data connector is connected with a PCIe bus;
the front panel is positioned at the front end of the communication board, and the J20J bus connector and the JTAG interface are both fixed on the front panel;
the power back board connector and the at least one MiniVPX back board data connector are fixed at the rear end of the board card;
the power module is fixed at the upper right corner of the board card and is adjacent to the power backboard connector; the power supply module is used for converting the power supply output by the power supply backboard connector into a working power supply and providing the working power supply for the FPGA module, the plurality of RS485 communication chips, the Flash memory and the E 2 The PROM memory provides a working power supply;
the FPGA module is positioned at the central position of the board, and is used for controlling the working states of a plurality of RS485 communication chips, and also used for controlling the Flash memory and the E 2 Reading and writing data by the PROM memory;
the plurality of RS485 communication chips are located on one side, close to the front panel, of the board card, the plurality of RS485 communication chips are connected with an external RS485 bus through a J20J bus connector, and the plurality of RS485 communication chips are connected with the FPGA.
2. The airborne isolation RS485 communication board card based on the MiniVPX framework of claim 1, wherein the width of the RS485 communication board card is 7.62cm, the depth is 10.16cm, and the height is 1.10cm.
3. The airborne isolation RS485 communication board card based on the MiniVPX framework according to claim 1 or 2, wherein the RS485 communication chip is an RS485 communication chip with an isolated power supply, each RS485 communication chip is further provided with a working state indicator lamp for displaying the working state of the RS485 communication chip, and the working state indicator lamp is embedded and fixed on the front panel.
4. The airborne isolated RS485 communication board card based on the MiniVPX architecture according to claim 1, wherein the communication board card further comprises a temperature sensor, and the temperature sensor is configured to detect an operating temperature of the communication board card and send the temperature information to the FPGA module.
5. The invention relates to an on-board isolated RS485 communication board card based on MiniVPX architecture, which is characterized in that the power module comprises a primary power supply and two secondary power supplies, wherein the primary power supply is used for converting a power supply signal input by a power supply backboard connector into an RS485 communication chip and E 2 The working power supply of the PROM memory comprises a secondary power supply for converting the power supply of the primary power supply output end into working power supplies of 1.0V and 1.8V, and a secondary power supply for converting the power supply of the primary power supply output end into working power supplies of 3.3V and 2.5V.
6. The airborne isolation RS485 communication board card based on the MiniVPX framework according to claim 1, wherein the FPGA realizes RS485 communication logic design through an RS485 communication chip, and the RS485 communication logic comprises a DMA-peripheral interface module, a peripheral-DMA module, an AXIStream bus, a TxFIFO buffer area, a serial transmission module, a timeout judgment module and an RxFIFO buffer area;
the RS485 communication logic is controlled by the FPGA module to realize data transmission and reception, the whole communication flow follows a serial bus protocol, one frame of a communication signal comprises a frame header, data and CRC check sum frame tail, in the RS485 communication logic, a DMA-peripheral interface module and a peripheral-DMA module are connected with AXIDMA, the communication signal is converted into a universal peripheral interface form from an AXIStream bus form and is transmitted to TxFIFO, a serial transmission module converts 8-bit parallel data in the TxFIFO into serial data and then outputs the serial data to be transmitted to a board card, a serial receiving module detects the received data in a set time, a timing module is used for timing, a timeout judging module in logic is a module for judging the set time, the serial data is converted into 8-bit parallel data through the serial receiving module and is transmitted to the RxFIFO, and the communication signal is transmitted to the AXIDMA through the peripheral-DMA module, so that primary data transmission and reception are completed.
7. The airborne isolated RS485 communication board card based on the MiniVPX framework according to claim 6, wherein a state parameter register, a register interface and a timing period timing module are further arranged in the RS485 communication logic;
the state parameter register is configured by the FPGA through a register interface and comprises transmission rate, frame length and timing time;
the timing module is interconnected with the register interface for specifying data transmission times.
8. The invention discloses an onboard isolated RS485 communication board card based on a MiniVPX architecture as claimed in claim 6 or 7, wherein the RS485 communication logic includes a protocol configuration register, the FPGA writes configuration parameters of an upper layer protocol into the register, and then performs corresponding frame-removing and framing operations according to a protocol transmission format in the register, so as to implement a function of editing output contents in a signal source output mode.
9. The airborne isolated RS485 communication board card based on the MiniVPX architecture according to claim 7, wherein the serial transmission module in the RS485 communication logic has the working state that:
the method comprises the steps of in an idle state, detecting a TxFIFO storage data state, and jumping to a frame header sending state when the TxFIFO is full of one frame of data;
the frame header sending state is used for sending frame header data, and after the sending is completed, the frame header sending state is skipped to the data sending state;
a data sending state for sending data until the sending quantity condition is met, and jumping to a CRC (cyclic redundancy check) sending state;
a CRC check state is sent and used for sending CRC check data, and if the check fails, the idle state is skipped; if the verification is successful, jumping to a transmitting frame tail state;
and the frame tail state is used for transmitting frame tail data, and after the transmission is completed, the frame tail state is jumped to the idle state.
10. The airborne isolated RS485 communication board card based on the MiniVPX architecture according to claim 7, wherein the serial receiving module in the RS485 communication logic has a working state as follows:
an idle state, i.e., a skip to a frame header judgment state when the start bit "0" of the received data is detected and not timed out;
the frame head judging state is used for judging the frame head state, if the frame head is not detected, the frame head is jumped to the data discarding state, and if the frame head is detected, the frame head is jumped to the data receiving state of the first byte;
the method comprises the steps of receiving a first byte data state, wherein the first byte data state is used for receiving first byte data, and jumping to the data receiving state after the first byte data is received;
a received data state for receiving data, if the received data quantity is satisfied, jumping to a frame tail judging state;
the frame tail judging state is used for detecting frame tail data, if the frame tail is not detected, jumping to the data discarding state, and if the frame tail is detected, jumping to the idle state;
and the data discarding state is used for clearing the data, and the data discarding state is skipped to the idle state after the data discarding is finished.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211126309.6A CN115834277B (en) | 2022-09-16 | 2022-09-16 | Airborne isolation RS485 communication board card based on MiniVPX architecture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211126309.6A CN115834277B (en) | 2022-09-16 | 2022-09-16 | Airborne isolation RS485 communication board card based on MiniVPX architecture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115834277A CN115834277A (en) | 2023-03-21 |
| CN115834277B true CN115834277B (en) | 2023-08-11 |
Family
ID=85523647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211126309.6A Active CN115834277B (en) | 2022-09-16 | 2022-09-16 | Airborne isolation RS485 communication board card based on MiniVPX architecture |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115834277B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110118955A (en) * | 2019-04-26 | 2019-08-13 | 西安电子科技大学 | Radar signal acquisition processing device based on MiniVPX |
| CN113391589A (en) * | 2021-06-29 | 2021-09-14 | 西北工业大学 | Unified access and protocol conversion integrated circuit board for heterogeneous equipment of unmanned aerial vehicle |
-
2022
- 2022-09-16 CN CN202211126309.6A patent/CN115834277B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110118955A (en) * | 2019-04-26 | 2019-08-13 | 西安电子科技大学 | Radar signal acquisition processing device based on MiniVPX |
| CN113391589A (en) * | 2021-06-29 | 2021-09-14 | 西北工业大学 | Unified access and protocol conversion integrated circuit board for heterogeneous equipment of unmanned aerial vehicle |
Non-Patent Citations (1)
| Title |
|---|
| RS485高速数据传输协议的设计与实现;耿立中;王鹏;马骋;贾惠波;;清华大学学报(自然科学版)网络.预览(第08期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115834277A (en) | 2023-03-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101571842B (en) | PCI integrated circuit board device used for ARINC429 communication | |
| CN103136138B (en) | Chip, chip debugging method and communication method for chip and external devices | |
| CN202838664U (en) | Multi-signal and multi-communication protocol data acquisition equipment based on STM32 | |
| CN101839969B (en) | Satellite communication 1553B ground detection system and detection method thereof | |
| CN105515673B (en) | A kind of optical-fibre channel node card | |
| CN101419582B (en) | MVB/USB adapter based on SOPC technology and communication method thereof | |
| CN206962829U (en) | A kind of mainboard of vehicle peace control Internet of things access equipment | |
| CN105118441A (en) | LED display screen control card for asynchronous control system | |
| CN115834277B (en) | Airborne isolation RS485 communication board card based on MiniVPX architecture | |
| CN114124609B (en) | Communication device and communication method based on 1553B bus | |
| CN110069435A (en) | Turn the more camera module configuration devices and method of SCCB based on USB3.0 | |
| CN103218334A (en) | Computer peripheral cascade device based on USB (Universal Serial Bus) and RS485 bus | |
| CN114660383A (en) | Universal ground detection test board card for load manager | |
| Li et al. | UART Controller with FIFO Buffer Function Based on APB Bus | |
| CN115096351A (en) | Array distributed multi-parameter measurement system with high space-time resolution | |
| CN219958220U (en) | Electronic system based on SPI bus and integrated electronic system of micro-nano satellite | |
| CN204667082U (en) | A kind of mainboard of bus Internet of Things peace control terminal device | |
| CN220087304U (en) | Vehicle-mounted Ethernet communication plug-in unit | |
| CN209460753U (en) | A kind of usb data real-time monitoring apparatus based on FPGA | |
| CN214225949U (en) | Remote workload metering device for engineering truck | |
| CN217116111U (en) | Extensible integrated control module suitable for power conversion system | |
| CN116192716B (en) | ZYNQ-based avionics multi-protocol bus test platform | |
| CN213094226U (en) | CAN communication device based on CPCI bus | |
| CN219266537U (en) | Highway positioning system integrating GPS and UWB wireless communication | |
| CN220315006U (en) | On-vehicle wiFi communication plug-in components of EMUs |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |