CN115834277A - Machine-mounted isolation RS485 communication board card based on MiniVPX framework - Google Patents
Machine-mounted isolation RS485 communication board card based on MiniVPX framework Download PDFInfo
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Abstract
The invention provides an airborne isolation RS485 communication board card based on a MiniVPX framework, belongs to the field of RS485 bus communication under an airborne test environment, and solves the problems of miniaturization, high integration, configurable communication protocol and the like of an airborne test system, and the technical scheme provided by the invention is as follows: the utility model provides an airborne isolation RS485 communication board card based on MiniVPX framework, the integrated circuit board includes: front panel, FPGA module, power module, multiple RS485 communication chips, flash memory, E 2 PROM memorizer, J20J bus connector, JTAG interface, power supply backplane connector, at least one MiniVPX backplane data connector; the FPGA module controls the RS485 module to realize the function of configuring a communication protocol; the power supply module supplies power to the whole communication board card; the RS485 communication chip adopts an RS485 communication chip with an isolation power supply; the invention is suitable for being applied toThe research field of the MiniVPX-based airborne isolation RS485 bus communication board card and the RS485 bus communication application field.
Description
Technical Field
The invention relates to the field of RS485 bus communication under an airborne test environment, in particular to an airborne isolation RS485 bus communication board card based on a MiniVPX framework.
Background
With the rapid development of the aviation industry in China, the test flight detection of the airplane in the research and development and manufacturing processes of the airplane is an irreplaceable important means for the design and performance index verification of the airplane. The airborne test system is an important means for acquiring test flight data, the problems of high volume occupation ratio, few types of test parameters, insufficient data processing workload and the like of the existing airborne test system technology are still urgently needed to be solved, and an efficient and reliable test system which saves system construction cost and can provide powerful test guarantee for test flight progress and efficiency is urgently needed in the field.
At present, domestic miniaturized airborne equipment is mostly imported from foreign countries, products related to MiniVPX architecture design are few, even if relevant standards are not established for imported miniaturized testing equipment such as miniR700 of America Ampex corporation, the generalization is poor, and the universality is not strong. And the MiniVPX can provide a standard modularized electronic system hardware solution for the platforms such as missile-borne, unmanned aerial vehicles and small satellites by virtue of superior characteristics such as higher integration level, higher generalization and smaller size. At present, the technology of the MiniVPX standard embedded system is not applied to high-speed airborne test equipment in China.
At present, the field buses in use internationally have various names, such as PROFIBUS, INTERBUS and CAN buses, but the system cost is relatively high and is inconvenient to maintain, and the RS485 bus is used as a common data bus in the field of airborne test and has the characteristics of simple structure, mature technology, low cost, convenience in maintenance and the like, so that the application is wider.
Nowadays, a new technology based on the RS485 bus communication board of the MiniVPX architecture is urgently needed to overcome the difficulties in the aspects of miniaturization, high integration, configurable communication protocol and the like of an airborne test system.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides an airborne isolation RS485 communication board card based on a MiniVPX framework.
The method is realized by the following technical scheme:
the utility model provides an airborne isolation RS485 communication board based on MiniVPX framework which characterized in that, RS485 communication board includes: front panel, FPGA module, power module, multiple RS485 communication chips, flash memory, E 2 PROM memorizer, J20J bus connector, JTAG interface, power supply backplane connector, at least one MiniVPX backplane data connector;
the MiniVPX back plate data connector is connected with a PCIe bus;
the front panel is positioned at the front end of the communication board card, and the J20J bus connector and the JTAG interface are fixed on the front panel;
the power supply backplane connector and the at least one MiniVPX backplane data connector are fixed at the rear end of the board card;
the power supply module is fixed at the upper right corner of the board card and is close to the power supply backplane connector; the power supply module is used for converting the power supply output by the power supply backplane connector into a working power supply and providing the working power supply for the FPGA module, the RS485 communication chips, the Flash memory and the E 2 The PROM memory provides a working power supply;
the FPGA module is located at the center of the board card and used for controlling the working states of the RS485 communication chips and controlling the Flash memory and the E 2 The PROM reads and writes the data;
the RS485 communication chips are located on one side, close to the front panel, of the board card, the RS485 communication chips are connected with an external RS485 bus through a J20J bus connector, and the RS485 communication chips are connected with the FPGA.
Further, a preferred embodiment is provided, wherein the width of the RS485 communication board card is 7.62cm, the depth of the RS485 communication board card is 10.16cm, and the height of the RS485 communication board card is 1.10cm.
Further, a preferred embodiment is provided, the RS485 communication chip adopts an RS485 communication chip with a self-contained isolation power supply, each RS485 communication chip is further provided with a working state indicator light for displaying the working state of the RS485 communication chip, and the working state indicator light is embedded and fixed on the front panel.
Further, a preferred embodiment is provided, and the communication board further comprises a temperature sensor, wherein the temperature sensor is used for detecting the working temperature of the communication board and sending the temperature information to the FPGA module.
Further, a preferred embodiment is provided, wherein the power module comprises a primary power supply and two secondary power supplies, the primary power supply is used for converting a power signal input by the power backplane connector into an RS485 communication chip and an E 2 The PROM memory comprises a PROM memory working power supply, a secondary power supply, a first-stage power supply output end power supply, a second-stage power supply, a third-stage power supply output end power supply and a fourth-stage power supply output end power supply, wherein the second-stage power supply is used for converting the first-stage power supply output end power supply into 1.0V and 1.8V working power supplies, and the third-stage power supply is used for converting the first-stage power supply output end power supply into 3.3V and 2.5V working power supplies.
Further, a preferred embodiment is provided, the FPGA implements an RS485 communication logic design through an RS485 communication chip, and the RS485 communication logic includes a DMA-peripheral interface module, a peripheral-DMA module, an AXI Stream bus, a Tx FIFO buffer, a serial transmission module, an timeout determination module, and an Rx FIFO buffer;
the RS485 communication logic realizes the receiving and sending of data through the control of an FPGA module, the whole communication process follows a serial bus protocol, wherein one frame of a communication signal comprises a frame header, data, CRC check and a frame tail, in the RS485 communication logic, a DMA-peripheral interface module and a peripheral-DMA module are connected with AXI DMA, the communication signal is converted into a universal peripheral interface form from an AXI Stream bus form and is sent to Tx FIFO, a serial sending module converts 8-bit parallel data in the Tx FIFO into serial data and then outputs the serial data to a board card, a serial receiving module detects the received data within a specified time, a timing period timing module times, an overtime judging module in the logic is a module for judging the specified time, the serial data is converted into 8-bit parallel data through a serial receiving module and is transmitted to the Rx FIFO, the communication signal is transmitted to the AXI DMA through the peripheral-DMA interface module, and the receiving and sending of primary data are completed.
Further, a preferred embodiment is provided, and a state parameter register, a register interface and a timing cycle timing module are further arranged in the logic of the RS485 communication module;
the state parameter register is used for carrying out state parameter configuration by the FPGA through a register interface, and comprises transmission rate, frame length and timing time setting;
the timing cycle timing module is interconnected with the register interface and used for stipulating data sending time.
Further, a preferred embodiment is provided, wherein the RS485 communication logic further includes a protocol configuration register, and the FPGA writes configuration parameters of an upper layer protocol into the register, and performs corresponding operations of deframing and framing according to a protocol transmission format in the register, so as to implement a function of editing and outputting content in a signal source output mode.
Further, a preferred embodiment is provided, and the working state of the serial transmission module in the RS485 communication logic is:
the method comprises the steps that an idle state is detected, a Tx FIFO storage data state is detected, and when the Tx FIFO is full of one frame of data, a frame head sending state is jumped to;
sending frame header state, used for sending frame header data, and skipping to sending data state after sending is completed;
a data sending state, which is used for sending data until the data sending amount condition is met, and skipping to a CRC (cyclic redundancy check) sending state;
sending a CRC check state, wherein the CRC check state is used for sending CRC check data, and if the check fails, jumping to an idle state; if the verification is successful, jumping to a frame tail sending state;
and sending the frame tail state, wherein the frame tail state is used for sending frame tail data, and after the sending is finished, jumping to the idle state.
Further, a preferred embodiment is provided, and the operating states of the serial receiving module in the RS485 communication logic are:
in the idle state, when the start bit '0' of the received data is detected and the time is not exceeded, the frame head is jumped to the frame head judgment state;
a frame header judging state, which is used for judging the frame header state, if the frame header is not detected, skipping to a data abandoning state, and if the frame header is detected, skipping to a state of receiving the first byte data;
receiving a first byte data state, wherein the first byte data state is used for receiving first byte data, and after the first byte data is received, jumping to a data receiving state;
the data receiving state is used for receiving data, and if the data receiving amount is met, the frame end judging state is jumped to;
the frame tail judging state is used for detecting frame tail data, jumping to a data abandoning state if the frame tail is not detected, and jumping to an idle state after the detection is finished if the frame tail is detected;
and the data abandoning state is used for clearing data, and after the data abandoning is finished, the data jumping to the idle state is carried out.
The beneficial effects of the invention are as follows:
1. based on the MiniVPX framework, the board card has the characteristic of small size, adopts 8-channel design and has the characteristic of high integration;
2. the RS485 communication chip integrated with the isolation power supply is adopted, and the design is used for a board card of a MiniVPX framework, so that the isolation power supply can be prevented from being designed, and the space is saved;
each channel of the RS485 communication board card can be independently collected, and the self-checking function of the communication board card can be completed by switching the collection/signal source modes;
the RS485 communication board card adopts an FPGA as a control module core to complete framing bottom layer logic, and the communication protocol configuration function is completed through logic design;
the RS485 communication board is provided with a temperature sensor, so that temperature monitoring can be carried out in real time for evaluating the working health state of the whole system;
and 6, PCIe high-speed communication is adopted for data interaction of the RS485 communication board backboard, so that the transmission efficiency is higher.
Drawings
Fig. 1 is a schematic diagram of a backplane communication signal design of an RS485 communication board mentioned in the eleventh embodiment;
fig. 2 is a schematic diagram of the connection relationship of the RS485 communication board card according to the eleventh embodiment;
fig. 3 is a schematic layout diagram of an RS485 communication board mentioned in the eleventh embodiment;
FIG. 4 is a schematic diagram of a power tree structure in a power module according to an eleventh embodiment;
FIG. 5 is a schematic diagram of an RS485 communication module according to an eleventh embodiment;
FIG. 6 is a block diagram showing the structure of a PCIe DMA core according to the eleventh embodiment;
fig. 7 is a schematic view of a front panel of an RS485 communication board according to an eleventh embodiment;
fig. 8 is a logic block diagram of an RS485 communication module according to an eleventh embodiment;
FIG. 9 is a state transition diagram of a serial transmission module according to an eleventh embodiment;
fig. 10 is a state transition diagram of the serial reception module according to the eleventh embodiment.
Detailed Description
In order to make the advantages and benefits of the technical solutions provided by the present invention more clear, the technical solutions provided by the present invention will be further described in detail with reference to the accompanying drawings, specifically:
the first implementation mode comprises the following steps: this embodiment provides an airborne isolation RS485 communication integrated circuit board based on MiniVPX framework, RS485 communication integrated circuit board includes: front panel, FPGA module, power module, multiple RS485 communication chips, flash memory, E 2 PROM memorizer, J20J bus connector, JTAG interface, power supply backplane connector, at least one MiniVPX backplane data connector;
the MiniVPX back plate data connector is connected with a PCIe bus;
the front panel is positioned at the front end of the communication board card, and the J20J bus connector and the JTAG interface are fixed on the front panel;
the power supply backplane connector and the at least one MiniVPX backplane data connector are fixed at the rear end of the board card;
the power supply module is fixed at the upper right corner of the board card and is close to the power supply backplane connector; for the power moduleThe power supply output by the power supply backplane connector is converted into a working power supply to be provided for the FPGA module, the RS485 communication chips, the Flash memory and the E 2 The PROM memory provides a working power supply;
the FPGA module is located at the center of the board card and used for controlling the working states of the RS485 communication chips and controlling the Flash memory and the E 2 The PROM memory reads and writes the data;
the RS485 communication chips are located on one side, close to the front panel, of the board card, the RS485 communication chips are connected with an external RS485 bus through a J20J bus connector, and the RS485 communication chips are connected with the FPGA.
The second embodiment: the present embodiment is further limited to the first embodiment, wherein the width of the RS485 communication board is 7.62cm, the depth is 10.16cm, and the height is 1.1cm.
The third embodiment is as follows: the embodiment further defines the onboard isolation RS485 communication board card based on the MiniVPX framework, the RS485 communication chip adopts an RS485 communication chip with an isolation power supply, each RS485 communication chip is also provided with a working state indicator lamp for displaying the working state of the RS485 communication chip, and the working state indicator lamp is embedded and fixed on the front panel.
The fourth embodiment: the communication board card further comprises a temperature sensor, and the temperature sensor is used for detecting the working temperature of the communication board card and sending the temperature information to the FPGA module.
The fifth embodiment: the power module comprises a primary power supply and two secondary power supplies, wherein the primary power supply is used for converting a power signal input by the power backplane connector into an RS485 communication chip and an E communication chip 2 Working power supply of PROM memoryOne secondary power supply is used for converting the power supply at the output end of the primary power supply into working power supplies of 1.0V and 1.8V, and the other secondary power supply is used for converting the power supply at the output end of the primary power supply into working power supplies of 3.3V and 2.5V.
Embodiment six: the embodiment further defines the onboard isolation RS485 communication board card based on the MiniVPX architecture, the FPGA realizes RS485 communication logic design through an RS485 communication chip, and the RS485 communication logic comprises a DMA-peripheral interface module, a peripheral-DMA module, an AXI Stream bus, a Tx FIFO buffer area, a serial transmission module, an overtime judgment module and an Rx FIFO buffer area;
the RS485 communication logic realizes the receiving and sending of data through the control of an FPGA module, the whole communication process follows a serial bus protocol, wherein one frame of a communication signal comprises a frame head, data, CRC check and a frame tail, in the RS485 communication logic, a DMA-peripheral interface module and a peripheral-DMA module are connected with AXI DMA, the communication signal is converted into a universal peripheral interface form from an AXI Stream bus form and is sent to Tx FIFO, a serial sending module converts 8-bit parallel data in the Tx FIFO into serial data and then outputs the serial data to a board card, a serial receiving module detects the received data within a specified time, a timing period timing module times, an overtime judging module in the logic is a module for judging the specified time, the serial data is converted into 8-bit parallel data through the serial receiving module and is transmitted to the Rx FIFO, the communication signal is transmitted to the AXI DMA through the peripheral-DMA interface module, and the receiving and sending of primary data are completed.
Embodiment seven: in the sixth embodiment, the MiniVPX architecture-based airborne isolated RS485 communication board is further limited, and a state parameter register, a register interface and a timing cycle timing module are further arranged in the RS485 communication module logic;
the state parameter register is used for configuring state parameters through a register interface by the FPGA, and the state parameters comprise transmission rate and frame length timing time setting;
the timing cycle timing module is interconnected with the register interface and used for stipulating data sending time.
The eighth embodiment: the present embodiment further defines an onboard isolation RS485 communication board card based on the MiniVPX architecture according to the sixth or seventh embodiment, where the RS485 communication logic further includes a protocol configuration register, and the FPGA writes configuration parameters of an upper layer protocol into the register, and then performs corresponding deframing and framing operations according to a protocol transmission format in the register, so as to implement a function of editing and outputting content in a signal source output mode.
The ninth embodiment: the present embodiment is further limited to the seventh embodiment, in which the on-board isolation RS485 communication board card based on the MiniVPX architecture is provided, and the operating state of the serial transmission module in the RS485 communication logic is as follows:
the method comprises the steps that an idle state is detected, a Tx FIFO storage data state is detected, and when the Tx FIFO is full of one frame of data, a frame head sending state is jumped to;
sending frame header state, used for sending frame header data, and skipping to sending data state after sending is completed;
a data sending state, which is used for sending data until the data sending amount condition is met, and skipping to a CRC (cyclic redundancy check) sending state;
sending a CRC check state, wherein the CRC check state is used for sending CRC check data, and if the check fails, jumping to an idle state; if the verification is successful, skipping to a sending frame tail state;
and sending the frame tail state, wherein the frame tail state is used for sending frame tail data, and after the sending is finished, jumping to the idle state.
Embodiment ten: the present embodiment is further limited to the seventh embodiment, in which the on-board isolation RS485 communication board card based on the MiniVPX architecture is provided, and the operating state of the serial receiving module in the RS485 communication logic is as follows:
in the idle state, when the start bit '0' of the received data is detected and the time is not exceeded, the frame head is jumped to the frame head judgment state;
a frame header judging state, which is used for judging the state of the frame header, if the frame header is not detected, jumping to a data abandoning state, and if the frame header is detected, jumping to a state of receiving first byte data;
receiving a first byte data state, wherein the first byte data state is used for receiving first byte data, and after the first byte data is received, jumping to a data receiving state;
the data receiving state is used for receiving data, and if the data receiving amount is met, the frame end judging state is jumped to;
the frame tail judging state is used for detecting frame tail data, jumping to a data abandoning state if the frame tail is not detected, and jumping to an idle state after the detection is finished if the frame tail is detected;
and the data abandoning state is used for clearing data, and after the data abandoning is finished, the data jumping to the idle state is carried out.
Embodiment eleven: the present embodiment provides a specific embodiment for the MiniVPX architecture-based onboard isolation RS485 communication board card provided in the first embodiment, and is also used to explain the second embodiment to the tenth embodiment, specifically:
the invention provides an onboard isolation RS485 communication board card based on a MiniVPX framework, which is suitable for a testing system of the MiniVPX framework, and is used as a function board card of the system to complete the receiving and sending functions of RS485 bus data, the testing system of the MiniVPX framework usually comprises a main control card, a storage card, a power supply card and a function card, the function card adopts PCIe (peripheral component interconnect express) to carry out data interaction with the main control card, low-capacity data (such as board card configuration information) interaction is carried out through an SMBus bus, the function board card comprises 8 RS485 communication channels, each channel carries out independent receiving and sending, and FIG. 1 is a design schematic diagram of a backboard communication signal of the RS485 communication board card.
The airborne isolation RS485 communication board card comprises the following modules: the system comprises a control module taking an FPGA as a core, a power supply module, an RS485 communication module taking an RS485 communication chip as a core and a PCIe communication back panel module taking an XDMA as a base. 8 indicator lamps are provided on the front panel part of the communication board card and used for indicating the working state of each bus channel. Adopt J20J connector to realize being connected with the RS485 bus as RS485 bus connector, the integrated circuit board front end is the interface of communication integrated circuit board and external interaction, the backplate is connected with airborne test equipment machine case through specific data connector, power module designs in communicationThe upper right corner of the board card is connected with a power supply backplane connector, the FPGA is designed in the center of the communication board card to serve as a core controller, the temperature of the board card can be monitored by the DS18B20 temperature sensor in real time, initialization configuration information in Flash can be read to configure the communication board card after the communication board card is powered on and started, and ID and working state information of the board card can be stored in E when the communication board card starts to work 2 In the PROM, the upper computer software performs board card identification and management operations, the connection relationship of the RS485 communication board is shown in fig. 2, and the layout of the board cards is shown in fig. 3.
(1) The FPGA control module mainly completes the functions of controlling an RS485 communication transceiving chip, enabling the FPGA control module to complete the functions of independently realizing the sampling bit rate of an RS485 signal, editing a synchronous signal and switching an acquisition mode and a signal source output mode of each channel, realizing the function of configuring a communication protocol, simultaneously providing a physical acquisition clock for the RS485 communication chip by the FPGA, completing the control of the acquisition rate of each channel, realizing the function of editing contents of each physical channel in the signal source output mode and supporting the synchronous and asynchronous mode switching of each physical channel, and storing an initialization file of the FPGA by Flash, and E 2 The PROM stores the ID and configuration information of the board card so that an upper computer can inquire the working state of the board card, is interconnected with the DS18B20 digital temperature sensor, monitors the temperature condition of the communication board card in real time, has the measurement range of-55-125 ℃ and the measurement precision of 0.5 ℃, can monitor the environment temperature of the case, and is convenient for evaluating the working health state of the whole system.
The RS485 communication board card receives and sends RS485 signals, each channel independently realizes the functions of RS485 signal sampling bit rate and synchronous signal editing, each physical channel edits output content in a signal source output mode, the editing range comprises a custom Label field, a data length field and a data section, and the rest data content supports automatic completion. The FPGA is used as the core of the main control module to realize the function of configuring the communication protocol, and the FPGA is used for realizing the logic of the bottom layer of framing and unframing, namely the function of configuring the communication protocol is completed.
(2) The power module mainly supplies power for each chip on the communication board card and the PCIe high-speed data transmission port, and the board card is designedIn the process, the related voltage types are more, the voltage ripple noise requirement of the high-speed transceiving port is higher, and the height of the board card is limited, so that the area occupied by the power module on the board card is larger, and the 1210 packaging type large capacitor is adopted for filtering for keeping the voltage stable so as to provide a better power supply environment. The power module is responsible for providing the voltage required by each chip on the whole board card and mainly comprises an FPGA chip and an E 2 The FPGA on the board card needs 1.8V, 1.2V, 1.0V and 3.3V of power supply voltage, and the Flash adopts 3.3V of power supply voltage.
The power supply system of the RS485 communication board card consists of one LTM4600, two LTMs 4616 and two TPS74401, wherein the LTM4600 completes the function of converting 12V voltage of the back plate into 5V and is used as a primary power supply of the communication board card; the LTM4616 is a single-input double-output power supply chip, and is used as a secondary power supply of the RS485 communication board card for respectively completing the functions of converting 5V into 1.8V, converting 2.5V, converting 5V into 3.3V and converting 1.0V; the TPS74401 can provide better ripple power for powering the PCIe high speed data transmission ports. As shown in fig. 4, the power tree structure of the RS485 bus communication board is shown.
In the structure diagram of the power supply tree, four parts of a primary power supply, namely the LTM4600, are used for supplying power for an RS485 communication voltage VDD, an E2PROM voltage and input voltages of two LTMs 4616, and a secondary power supply, namely the two LTMs 4616, is mainly used for supplying power for a special pin of an FPGA and a Flash and a clock chip, and the TPS74401 is adopted for improving the quality of the power supply and supplying power for a high-speed transmission port of the FPGA.
(3) The RS485 communication module is composed of 8 RS485 communication chips, an isolation power supply needs to be designed for a common RS485 chip, miniaturization design is extremely disadvantageous, in the invention, due to the reasons that the size of a board card is small, a power supply system is complex, the integration level of the number of channels is high and the like, an isolation power supply module which works independently is difficult to design, a TD (H) 541S485 chip is adopted, the chip is a half-duplex enhanced RS485 isolation transceiver with the isolation power supply, the conversion between an acquisition mode and a signal source mode can be realized, and the communication speed is up to 20Mbps. Except that the self-contained isolation power supply, the inside still contains signal isolator, can suppress the interference to a great extent, and the signal after the isolation passes through signal converter, converts into the RS485 signal transmission that accords with the standard.
When the bus is in an idle state, the A is pulled up through an isolation power supply provided by a VISION pin of the RS485 transceiver chip, the B end is connected with the ground, a pull-down resistor is added, the high level can be continuously output when the bus is idle, and in UART communication, if a receiving end receives an output low level, the communication starts. A diode is added between A and B, the anti-surge of the circuit is improved, the stability of a bus is effectively maintained through the circuit design outside a chip, the chip is protected from overcurrent and burning TD (H) 5414855, and a design schematic diagram of an RS485 communication module is shown in FIG. 5.
Because each RS485 communication chip channel is independent, each RS485 communication chip accomplishes the send-receiver function alone, adopts RS485 channel of the same kind as the signal source, whether the receipt of other RS485 channels is normal to go the test, and the sending function that also can test the RS485 channel in return can normally work, accomplishes RS485 communication integrated circuit board self-checking function.
(4) Data communication between the RS485 communication board and the main control board adopts an SMBus bus and a PCIe bus, wherein data acquisition, receiving and sending are mainly completed through PCIe communication based on XDMA, control instructions and other auxiliary data transmission adopt SMBus for communication, and the RS485 communication board introduces PCIe signals and SMBus signals into a CPU of the main control board through a connecting groove of a back board to perform data analysis, transfer and storage operations.
As shown in FIG. 6, a block diagram of the structure of a PCIe DMA core is presented. After the FPGA exemplary configuration is finished, the FPGA only needs to perform interrupt triggering operation on the HOST HOST, all DMA operation is completely realized by the HOST HOST through a register of PCIe configuration XDMA, then data communication between the RS485 communication board and the main control module is performed, the RS485 communication board converts acquired data information into PCIe through an XDMA kernel and transmits the PCIe information to the main control module through a backboard, and meanwhile, the main control board transmits data to be sent to the communication board through the XDMA kernel.
In the transmission process, the DMA needs to know the data flow direction, address space management of PCIe is involved, PCIe maps the address space of the RS485 communication board card to a section of address space in the master control board card through BAR space mapping, thus the BAR space directly corresponding to the direct operation of the master control board card is the address space directly inside the RS485 communication board card, and the mapping relation needs the host to configure a BAR space register of the RS485 communication board card to distribute the address space and the length.
In addition, the ports of the RS485 bus communication board interacting with the outside are all placed in the front panel of the board, and include a dual-color LED indicator light for indicating the working state of each channel, a JTAG interface, and a J20J type connector connected to the RS485 bus, and the specific layout is as shown in fig. 7.
The LED double-color indicator lamp is arranged above the board card, corresponds to the position of the indicator lamps of other board cards in the case, is powered by 2.5V voltage, and is a double-seat indicator lamp, each LED corresponds to the working state of one channel, and is controlled by an FPGA pin. The connector is of a J20J type and meets the standard of an aerospace connector, the connector is of a twist needle structure, the distance between every two adjacent connectors is 0.95mm, the row spacing is 1.01mm, the connector is a head-mounted needle, and the connector is of a J20J-25TJW-TH type.
(5) The logic control of the RS485 communication module realizes the receiving and sending of data, the communication flow follows a serial bus protocol, one frame comprises a frame head, data, CRC check and a frame tail, in the RS485 communication module logic, the DMA-peripheral interface module and the peripheral-DMA module are responsible for connecting AXI DMA, communication signals are converted into a universal peripheral interface form from an AXI Stream bus form, and carry out data interaction with Tx FIFO and Rx FIFO, and a logic block diagram of the RS485 communication module is shown as 8.
In the RS485 communication module logic, the DMA-peripheral interface module and the peripheral-DMA module are responsible for connecting AXI DMA, converting a communication signal from an AXI Stream bus form into a universal peripheral interface form, and performing data interaction with Tx FIFO and Rx FIFO. The serial sending module converts the 8-bit parallel data in the Tx FIFO into serial data and then outputs the serial data, the serial receiving module detects the received data within a specified time and converts the serial data into the 8-bit parallel data to transmit to the Rx FIFO, and the overtime judging module is a module for judging the specified time. The state parameter registers in the RS485 communication logic module, such as timing time, frame length, transmission rate and FIFO data volume, are subjected to parameter setting by the FPGA through a register interface. Fig. 9 and 10 show the state transition flows of the serial transmission module and the serial reception module, respectively.
Under the signal source output mode, the RS485 communication module supports the function of editing output content, the editing range comprises a user-defined Label field, a data length field and a data section, and the rest data content supports automatic completion.
Claims (10)
1. The utility model provides an airborne isolation RS485 communication board based on MiniVPX framework which characterized in that, RS485 communication board includes: front panel, FPGA module, power module, multiple RS485 communication chips, flash memory, E 2 PROM memorizer, J20J bus connector, JTAG interface, power supply backplane connector, at least one MiniVPX backplane data connector;
the MiniVPX back plate data connector is connected with a PCIe bus;
the front panel is positioned at the front end of the communication board card, and the J20J bus connector and the JTAG interface are fixed on the front panel;
the power supply backplane connector and the at least one MiniVPX backplane data connector are fixed at the rear end of the board card;
the power supply module is fixed at the upper right corner of the board card and is close to the power supply backplane connector; the power supply module is used for converting the power supply output by the power supply backplane connector into a working power supply and providing the working power supply for the FPGA module, the RS485 communication chips, the Flash memory and the E 2 The PROM memory provides a working power supply;
the FPGA module is located at the central position of the board card and is used for controlling the working states of the RS485 communication chipsAnd also for controlling Flash memory and E 2 The PROM memory reads and writes the data;
the RS485 communication chips are located on one side, close to the front panel, of the board card, the RS485 communication chips are connected with an external RS485 bus through a J20J bus connector, and the RS485 communication chips are connected with the FPGA.
2. The MiniVPX architecture-based airborne isolated RS485 communication board of claim 1, wherein the RS485 communication board has a width of 7.62cm, a depth of 10.16cm and a height of 1.10cm.
3. The MiniVPX-architecture-based airborne isolated RS485 communication board card of claim 1 or 2, wherein the RS485 communication chip is an RS485 communication chip with an isolated power supply, each RS485 communication chip is further provided with a working state indicator lamp for displaying the working state of the RS485 communication chip, and the working state indicator lamp is embedded and fixed on the front panel.
4. The MiniVPX-architecture-based airborne isolation RS485 communication board of claim 1, wherein the communication board further comprises a temperature sensor, the temperature sensor is configured to detect a working temperature of the communication board and send the temperature information to the FPGA module.
5. The MiniVPX-architecture-based airborne isolated RS485 communication board card of claim 1, wherein the power module comprises a primary power supply and two secondary power supplies, the primary power supply is used for converting a power signal input by the power backplane connector into an RS485 communication chip and an E 2 The PROM memory comprises a PROM memory working power supply, a secondary power supply, a first-stage power supply output end power supply, a second-stage power supply, a third-stage power supply output end power supply and a fourth-stage power supply output end power supply, wherein the second-stage power supply is used for converting the first-stage power supply output end power supply into 1.0V and 1.8V working power supplies, and the third-stage power supply is used for converting the first-stage power supply output end power supply into 3.3V and 2.5V working power supplies.
6. The MiniVPX architecture-based airborne isolated RS485 communication board card of claim 1, wherein the FPGA implements RS485 communication logic design through an RS485 communication chip, and the RS485 communication logic comprises a DMA-peripheral interface module, a peripheral-DMA module, an AXI Stream bus, a Tx FIFO buffer, a serial transmission module, a timeout determination module, and an Rx FIFO buffer;
the RS485 communication logic realizes the receiving and sending of data through the control of an FPGA module, the whole communication process follows a serial bus protocol, wherein one frame of a communication signal comprises a frame head, data, CRC check and a frame tail, in the RS485 communication logic, a DMA-peripheral interface module and a peripheral-DMA module are connected with AXIDMA, the communication signal is converted into a universal peripheral interface form from an AXI Stream bus form and is sent to Tx FIFO, a serial sending module converts 8-bit parallel data in the Tx FIFO into serial data and then outputs the serial data to a board card, a serial receiving module detects the received data within a specified time, a timing period timing module times, an overtime judging module in the logic is a module for judging the specified time, the serial data is converted into 8-bit parallel data through the serial receiving module and is transmitted to the Rx FIFO, the communication signal is transmitted to the AXIDMA through the peripheral-DMA interface module, and the receiving and sending of primary data are completed.
7. The MiniVPX-architecture-based airborne isolated RS485 communication board card of claim 6, wherein a status parameter register, a register interface and a timing cycle timing module are further arranged in the RS485 communication logic;
the state parameter register is used for carrying out state parameter configuration by the FPGA through a register interface, and comprises transmission rate, frame length and timing time setting;
the timing cycle timing module is interconnected with the register interface and used for stipulating data sending time.
8. The airborne isolated RS485 communication board based on the MiniVPX architecture of claim 6 or 7, wherein the RS485 communication logic includes a protocol configuration register, the FPGA writes configuration parameters of an upper layer protocol into the register, and performs corresponding deframing and framing operations according to a protocol transmission format in the register, so as to implement a function of editing and outputting content in a signal source output mode.
9. The MiniVPX-architecture-based airborne isolated RS485 communication board card of claim 7, wherein a serial transmission module in the RS485 communication logic operates in the following states:
the method comprises the steps that an idle state is detected, a Tx FIFO storage data state is detected, and when the Tx FIFO is full of one frame of data, a frame head sending state is jumped to;
sending frame header state, used for sending frame header data, and skipping to sending data state after sending;
a data sending state, which is used for sending data until the data sending amount condition is met, and skipping to a CRC (cyclic redundancy check) sending state;
sending a CRC check state, wherein the CRC check state is used for sending CRC check data, and if the check fails, jumping to an idle state; if the verification is successful, jumping to a frame tail sending state;
and sending the frame tail state, wherein the frame tail state is used for sending frame tail data, and after the sending is finished, jumping to the idle state.
10. The MiniVPX-architecture-based airborne isolated RS485 communication board card of claim 7, wherein the working state of a serial receiving module in the RS485 communication logic is:
in the idle state, when the start bit '0' of the received data is detected and the time is not exceeded, the frame head is jumped to the frame head judgment state;
a frame header judging state, which is used for judging the frame header state, if the frame header is not detected, skipping to a data abandoning state, and if the frame header is detected, skipping to a state of receiving the first byte data;
receiving a first byte data state, wherein the first byte data state is used for receiving first byte data, and after the first byte data is received, jumping to a data receiving state;
a data receiving state, which is used for receiving data, and jumping to a frame end judging state if the data receiving amount is met;
the frame tail judging state is used for detecting frame tail data, jumping to a data abandoning state if the frame tail is not detected, and jumping to an idle state after the detection is finished if the frame tail is detected;
and the data abandoning state is used for clearing data, and after the data abandoning is finished, the data jumping to the idle state is carried out.
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| CN110118955A (en) * | 2019-04-26 | 2019-08-13 | 西安电子科技大学 | Radar signal acquisition processing device based on MiniVPX |
| CN113391589A (en) * | 2021-06-29 | 2021-09-14 | 西北工业大学 | Unified access and protocol conversion integrated circuit board for heterogeneous equipment of unmanned aerial vehicle |
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| CN110118955A (en) * | 2019-04-26 | 2019-08-13 | 西安电子科技大学 | Radar signal acquisition processing device based on MiniVPX |
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