CN115833576A - Low-power consumption control circuit and micro-processing chip - Google Patents
Low-power consumption control circuit and micro-processing chip Download PDFInfo
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Abstract
The embodiment of the invention provides a low-power-consumption control circuit and a micro-processing chip. The low power consumption control circuit comprises: the charge pump circuit comprises a processor, a charge pump circuit and a level shifter, wherein the processor is connected with the input end of the charge pump circuit, and the level shifter is connected with the output end of the charge pump circuit; the processor is used for outputting the first voltage to the charge pump circuit; the charge pump circuit is used for boosting the first voltage to a second voltage and outputting the second voltage to the level shifter; the level shifter is used for working under the driving of the second voltage. According to the embodiment of the invention, the first voltage output by the processor is boosted to the second voltage through the charge pump circuit, and when the chip is converted into the working mode from the low power consumption mode, the charge pump circuit can boost the first voltage to different second voltages, so that the requirements of different IP modules on voltage domains with different sizes under the condition that the chip is converted into the working mode from the low power consumption mode are met, and the requirement of low power consumption is further met.
Description
[ technical field ] A method for producing a semiconductor device
The embodiment of the invention relates to the technical field of chips, in particular to a low-power-consumption control circuit and a micro-processing chip.
[ background of the invention ]
With the development of Integrated Circuit (Integrated Circuit) technology, the application of micro-processing chips is becoming more and more widespread. The low power design of microprocessor chips is an important issue for chip design. Under the low-power design, the low-power kernel of the micro-processing chip has a low-power mode and a working mode. In the related art, switching between a low power consumption mode and an operating mode of a low power consumption core is realized by providing a switch circuit. The switching circuit may connect a power supply and a level shifter. And controlling the switch circuit to be conducted according to the comparison result so as to control the power supply to be connected with the level shifter, so that the effect of boosting the level shifter is achieved.
However, in the related art, the power supply needs to be kept continuously to meet the switching between the low power consumption mode and the operating mode, and power loss inevitably occurs, so that the requirement of low power consumption cannot be met.
[ summary of the invention ]
In view of this, embodiments of the present invention provide a low power consumption control circuit and a microprocessor chip, so as to meet the requirements of different modules for different voltage domains when a chip is switched from a low power consumption mode to a working mode, thereby implementing the requirement for low power consumption, and more specifically, the requirement that the voltage cannot be raised to 1.2V or 3.3V in different voltage states when the low power consumption mode in which the core voltage is less than 0.85V is switched to the working mode can be solved. For example, the threshold of the differential NMOS transistor of 3.3V under the partial corner is very high, reaching more than 1V, so if the turn-on voltage does not exceed 1V, the differential NMOS transistor of 3.3V cannot be turned on; for another example, for a conventional temperature sensor or an Analog-to-Digital Converter (ADC), it usually needs a voltage of 3.3V to operate normally.
In one aspect, an embodiment of the present invention provides a low power consumption control circuit, including: the charge pump circuit comprises a processor, a charge pump circuit and a level shifter, wherein the processor is connected with the input end of the charge pump circuit, and the level shifter is connected with the output end of the charge pump circuit;
the processor is used for outputting a first voltage to the charge pump circuit;
the charge pump circuit is used for boosting the first voltage to a second voltage and outputting the second voltage to a level shifter;
the level shifter is used for working under the driving of the second voltage.
In the embodiment of the invention, the design of the charge pump circuit avoids the power supply design of the traditional charge pump in the continuous working voltage domain under the condition that the low power consumption mode is converted into the working mode, thereby greatly reducing the power consumption.
Optionally, the charge pump circuit comprises a clock generator and a plurality of charge pumps, the clock generator being connected to each of the charge pumps;
the clock generator is used for outputting a clock signal to each charge pump so as to control the plurality of charge pumps to boost the first voltage to the second voltage.
In the embodiment of the invention, the charge pump circuit adopts a plurality of charge pumps, so that the requirements of different IP modules on voltage domains with different sizes under the condition that the chip is converted from a low power consumption mode to a working mode are met, and the optimization of power consumption is more flexible.
Optionally, the charge pump comprises a charge switch, a discharge switch and a capacitor;
the clock generator is used for controlling the charging switch to be switched on or switched off and controlling the discharging switch to be switched on or switched off;
the capacitor is used for charging when the charging switch is turned on and the discharging switch is turned off;
the capacitor is used for discharging when the discharging switch is turned on and the charging switch is turned off.
Optionally, the charge switch includes a first NMOS transistor, a second NMOS transistor, and a third PMOS transistor, and the discharge switch includes a first PMOS transistor and a second PMOS transistor;
the grid electrode of the first NMOS tube is connected to the clock generator, the source electrode of the first NMOS tube is connected to the first end of the capacitor, and the drain electrode of the first NMOS tube is grounded;
the grid electrode of the second NMOS tube is connected to the clock generator, the source electrode of the second NMOS tube is connected to the signal output end, and the drain electrode of the second NMOS tube is grounded;
the grid electrode of the third PMOS tube is connected to the signal output end, the source electrode of the third PMOS tube is connected to the signal input end, and the drain electrode of the third PMOS tube is connected to the second end of the capacitor;
the grid electrode of the first PMOS tube is connected to the clock generator, the source electrode of the first PMOS tube is connected to the signal input end, and the drain electrode of the first PMOS tube is connected to the first end of the capacitor;
the grid electrode of the second PMOS tube is connected to the clock generator, the source electrode of the second PMOS tube is connected to the second end of the capacitor, and the drain electrode of the second PMOS tube is connected to the signal output end.
Optionally, when the clock signal output by the clock generator is a high level signal, the first NMOS transistor, the second NMOS transistor, and the third PMOS transistor are turned on, the first PMOS transistor and the second PMOS transistor are turned off, and the signal output end outputs a low level signal.
Optionally, when the clock signal output by the clock generator is a low level signal, the first NMOS transistor, the second NMOS transistor, and the third PMOS transistor are turned off, the first PMOS transistor and the second PMOS transistor are turned on, and the signal output end outputs a high level signal.
Optionally, the plurality of charge pumps comprises a first charge pump and a second charge pump, the processor is connected to the first charge pump and the second charge pump, an output of the first charge pump is connected to the second charge pump, and an output of the second charge pump is connected to the level shifter;
the processor is configured to output the first voltage to the first charge pump;
the first charge pump is used for outputting a third voltage to the second charge pump under the control of the clock signal and under the driving of the first voltage;
the second charge pump is used for outputting the second voltage to the level shifter under the control of the clock signal and under the driving of the third voltage.
In the embodiment of the invention, the charge pump circuit adopts two charge pumps with the same structure, can meet voltage domains with different sizes, and is simple and convenient to operate and simple to control.
Optionally, the first charge pump or the second charge pump comprises: the charge switch comprises a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube and a third PMOS tube, and the discharge switch comprises a first PMOS tube and a second PMOS tube;
the grid electrode of the first NMOS tube is connected to the clock generator, the source electrode of the first NMOS tube is connected to the first end of the capacitor, and the drain electrode of the first NMOS tube is grounded;
the grid electrode of the second NMOS tube is connected to the clock generator, the source electrode of the second NMOS tube is connected to the signal output end, and the drain electrode of the second NMOS tube is grounded;
the grid electrode of the third PMOS tube is connected to the signal output end, the source electrode of the third PMOS tube is connected to the signal input end, and the drain electrode of the third PMOS tube is connected to the second end of the capacitor;
the grid electrode of the first PMOS tube is connected to the clock generator, the source electrode of the first PMOS tube is connected to the signal input end, and the drain electrode of the first PMOS tube is connected to the first end of the capacitor;
the grid electrode of the second PMOS tube is connected to the clock generator, the source electrode of the second PMOS tube is connected to the second end of the capacitor, and the drain electrode of the second PMOS tube is connected to the signal output end;
the signal output end of the first charge pump is connected to the signal input end of the second charge pump.
Optionally, the level shifter further comprises: a differential NMOS tube;
the differential NMOS tube is connected to the signal output end of the charge pump circuit.
The output end of the charge pump circuit in the embodiment of the invention is connected to the differential NMOS tube, so that the problem that the differential NMOS tube with 3.3V cannot be started if the starting voltage does not exceed 1V because the threshold value under part of corner is very high and reaches more than 1V when the low-power-consumption mode is converted into the working mode is solved.
On the other hand, the embodiment of the invention provides a micro-processing chip, which comprises the low-power consumption control circuit.
In the technical scheme provided by the embodiment of the invention, the low-power-consumption control circuit comprises a processor, a charge pump circuit and a level shifter, wherein the processor outputs a first voltage to the charge pump circuit, and the charge pump circuit boosts the first voltage to a second voltage and outputs the second voltage to the level shifter so as to enable the level shifter to work under the drive of the second voltage.
[ description of the drawings ]
Fig. 1 is a schematic structural diagram of a low power consumption control circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the charge pump circuit of FIG. 1;
fig. 3 is a schematic structural diagram of another low power consumption control circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a microprocessor chip according to an embodiment of the present invention.
[ detailed description ] embodiments
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of associative relationship that describes an associated object, meaning that three types of relationships may exist, e.g., A and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
Fig. 1 is a schematic structural diagram of a low power consumption control circuit according to an embodiment of the present invention, and as shown in fig. 1, the low power consumption control circuit includes: a processor 11, a charge pump circuit 12 and a level shifter 13. The processor 11 is connected to an input of the charge pump circuit 12, and the level shifter 13 is connected to an output of the charge pump circuit 12. The processor 11 is configured to output the first voltage to the charge pump circuit 12; the charge pump circuit 12 is configured to boost the first voltage to a second voltage, and output the second voltage to the level shifter 13; the level shifter 13 is configured to operate under the driving of the second voltage.
The low-power-consumption control circuit provided by the embodiment of the invention comprises a processor, a charge pump circuit and a level shifter, wherein the processor outputs a first voltage to the charge pump circuit, and the charge pump circuit boosts the first voltage to a second voltage and outputs the second voltage to the level shifter so as to enable the level shifter to work under the driving of the second voltage.
In an embodiment of the present invention, the charge pump circuit may include a clock generator and a plurality of charge pumps, the clock generator being connected to each of the charge pumps, the clock generator being configured to output a clock signal to each of the charge pumps to control the plurality of charge pumps to boost the first voltage to the second voltage. The charge pump circuit of the embodiment of the invention adopts a multi-stage charge pump to boost the first voltage to the second voltage. In the charge pump circuit, a first stage of charge pumps in the plurality of charge pumps are connected with the processor, a last stage of charge pumps are connected with the level shifter, and the plurality of charge pumps are connected with one another. In the embodiment of the invention, the charge pump circuit adopts a plurality of charge pumps, so that the requirements of different IP modules on voltage domains with different sizes under the condition that the chip is converted from a low power consumption mode to a working mode are met, and the optimization of power consumption is more flexible.
As an alternative, the plurality of charge pumps includes a first charge pump and a second charge pump. Fig. 2 is a schematic structural diagram of the charge pump circuit in fig. 1, and as shown in fig. 1 and fig. 2, the charge pump circuit 12 includes a first charge pump and a second charge pump, the processor 11 is connected to the first charge pump and the second charge pump, an output terminal of the first charge pump is connected to the second charge pump, and an output terminal of the second charge pump is connected to the level shifter 13. The processor 11 is configured to output the first voltage VDD1 to the first charge pump. The first charge pump is used for outputting a third voltage VDD2 to the second charge pump under the control of a clock signal and under the driving of a first voltage VDD1. The second charge pump is used for outputting the second voltage VOUT to the level shifter 13 under the control of the clock signal and driven by the third voltage VDD2.
In the embodiment of the invention, the charge pump comprises a charging switch, a discharging switch and a capacitor. The clock generator is used for controlling the charging switch to be switched on or switched off and controlling the discharging switch to be switched on or switched off. The capacitor is used for charging when the charging switch is switched on and the discharging switch is switched off; the capacitor is used for discharging when the discharging switch is turned on and the charging switch is turned off. The plurality of charge pumps comprise a first charge pump and a second charge pump, the first charge pump and the second charge pump can both adopt charge pump structures, the first charge pump and the second charge pump can have the same structure, namely the first charge pump or the second charge pump comprises a charge switch, a discharge switch and a capacitor, and the clock generator is used for outputting a clock signal Vin to the first charge pump and the second charge pump, controlling the charge switch to be turned on or off and controlling the discharge switch to be turned on or off through the clock signal Vin. In the embodiment of the invention, the charge pump circuit adopts two charge pumps with the same structure, can meet voltage domains with different sizes, and is simple and convenient to operate and simple to control.
In the embodiment of the invention, the charging switch comprises a first NMOS transistor, a second NMOS transistor and a third PMOS transistor. The grid electrode of the first NMOS tube is connected to the clock generator, the source electrode of the first NMOS tube is connected to the first end of the capacitor, and the drain electrode of the first NMOS tube is grounded; the grid electrode of the second NMOS tube is connected to the clock generator, the source electrode of the second NMOS tube is connected to the signal output end, and the drain electrode of the second NMOS tube is grounded; the grid electrode of the third PMOS tube is connected to the signal output end, the source electrode of the third PMOS tube is connected to the signal input end, and the drain electrode of the third PMOS tube is connected to the second end of the capacitor.
As shown in fig. 2, in the first charge pump, the charge switch includes a first NMOS transistor NMOS1, a second NMOS transistor NMOS2, and a third PMOS transistor PMOS3. The gate of the Nmos1 is connected to the clock generator, the source of the Nmos1 is connected to the first end a of the capacitor C1, and the drain of the Nmos1 is grounded GND1; the gate of the Nmos2 is connected to the clock generator, the source of the Nmos2 is connected to the signal output end D, and the drain of the Nmos2 is grounded GND1; the gate of Pmos3 is connected to the signal output terminal D, the source of Pmos3 is connected to the signal input terminal C, and the drain of Pmos3 is connected to the second terminal B of the capacitor C1.
As shown in fig. 2, in the second charge pump, the charge switch includes a first NMOS transistor NMOS1', a second NMOS transistor NMOS2', and a third PMOS transistor PMOS3'. The grid electrode of the Nmos1 'is connected to the clock generator, the source electrode of the Nmos1' is connected to the first end A 'of the capacitor, and the drain electrode of the Nmos1' is grounded GND1; the gate of the Nmos2 'is connected to the clock generator, the source of the Nmos2' is connected to the signal output end D ', and the drain of the Nmos2' is grounded GND1; the gate of Pmos3 'is connected to the signal output terminal D', the source of Pmos3 'is connected to the signal input terminal C', and the drain of Pmos3 'is connected to the second terminal B' of the capacitor C2.
In the embodiment of the invention, the discharge switch comprises a first PMOS tube and a second PMOS tube. The grid electrode of the first PMOS tube is connected to the clock generator, the source electrode of the first PMOS tube is connected to the signal input end, and the drain electrode of the first PMOS tube is connected to the first end of the capacitor; the grid electrode of the second PMOS tube is connected to the clock generator, the source electrode of the second PMOS tube is connected to the second end of the capacitor, and the drain electrode of the second PMOS tube is connected to the signal output end.
As shown in fig. 2, in the first charge pump, the discharge switch includes a first PMOS transistor PMOS1 and a second PMOS transistor PMOS2. The grid electrode of the Pmos1 is connected to the clock generator, the source electrode of the Pmos1 is connected to the signal input end C, and the drain electrode of the Pmos1 is connected to the first end A of the capacitor C1; the gate of Pmos2 is connected to the clock generator, the source of Pmos2 is connected to the second terminal B of the capacitor C1, and the drain of Pmos2 is connected to the signal output terminal D.
As shown in fig. 2, in the second charge pump, the discharge switch includes a first PMOS transistor PMOS1 'and a second PMOS transistor PMOS2'. The gate of Pmos1' is connected to the clock generator, the source of Pmos1' is connected to the signal input terminal C ', and the drain of Pmos1' is connected to the second terminal a ' of the capacitor C2; the gate of Pmos2' is connected to the clock generator, the source of Pmos2' is connected to the second terminal B ' of the capacitor, and the drain of Pmos2' is connected to the signal output terminal D '.
As shown in fig. 2, the clock generator is configured to output a clock signal Vin to Nmos1, nmos2, pmos1, pmos2, nmos1', nmos2', pmos1', and Pmos2'. The clock signal may be a high level signal or a low level signal.
As shown in fig. 1 and fig. 2, in the first charge pump, the signal input terminal C is connected to the processor 11, and the signal input terminal C is an input terminal of the first charge pump and is also an input terminal of the charge pump circuit, so that the processor 11 can output the first voltage VDD1 to the first charge pump through the signal input terminal C. In the first charge pump, the signal output terminal D is connected to the second charge pump, and the signal output terminal D is an output terminal of the first charge pump, so that the first charge pump can output the third voltage VDD2 to the second charge pump through the signal output terminal D.
As shown in fig. 1 and fig. 2, in the second charge pump, the signal input terminal C 'is connected to the first charge pump, and the signal input terminal C' is an input terminal of the second charge pump, the second charge pump can receive the third voltage VDD2 output by the first charge pump through the signal input terminal C ', wherein the signal output terminal D of the first charge pump is connected to the signal input terminal C' of the second charge pump. In the second charge pump, the signal output terminal D ' is connected to the level shifter 13, and the signal output terminal D ' is an output terminal of the second charge pump and is also an output terminal of the charge pump circuit, so that the second charge pump can output the second voltage VOUT to the level shifter 13 through the signal output terminal D '.
The operation principle of the charge pump circuit 12 provided by the embodiment of the present invention is described below with reference to fig. 1 and fig. 2.
When the clock signal Vin output from the clock generator is a high level signal, nmos1, nmos2, nmos1', and Nmos2' are turned on, and Pmos1, pmos2, pmos1', and Pmos2' are turned off. In the first charge pump, since Nmos2 is turned on, the voltage of the signal output end D is a low level signal, and at this time Pmos3 is turned on; in the second charge pump, since Nmos2' is turned on, the voltage at the signal output terminal D ' is a low level signal, and at this time Pmos3' is turned on. In the first charge pump, nmos1 is turned on, so that the voltage at the first end a of the capacitor C1 is a low level signal, pmos3 is turned on, and the processor 11 outputs the first voltage VDD1 through the turned-on Pmos3, so that the voltage at the second end B of the capacitor C1 is a high level signal, and therefore, the voltage difference across the capacitor C1 is approximately the first voltage VDD1, for example, when VDD1 is 0.70V-0.85V, the voltage at the first end a of the capacitor C1 is 0V, and the voltage at the second end B of the capacitor C1 is 0.70V-0.85V. Similarly, in the second charge pump, the voltage difference across the capacitor C2 is approximately the first voltage VDD1.
When the clock signal Vin output by the clock generator is a low level signal, pmos1, pmos2, pmos1 'and Pmos2' are turned on, and Nmos1, nmos2, nmos1 'and Nmos2' are turned off, so that the voltage of the signal output terminal D of the first charge pump is a high level signal, at which time Pmos3 is turned off, and the voltage of the signal output terminal D 'of the second charge pump is a high level signal, at which time Pmos3' is turned off. In the first charge pump, pmos1 is turned on, so that the voltage at the first end a of the capacitor C1 is the first voltage VDD1 output by the processor 11, and since the voltage difference of VDD1 exists between the two ends of the capacitor C1, the voltage at the second end B of the capacitor C1 is 2 times VDD1, for example, VDD1 is 0.70V-0.85V, the voltage at the first end a of the capacitor C1 is 0.70V-0.85V, and since the voltage at the two ends of the capacitor C1 is 0.70V-0.85V, the voltage at the second end B of the capacitor C1 is 1.4V-1.7V. In the first charge pump, the voltage VDD2 output by the signal output terminal D is 1.4V to 1.7V because Pmos2 is turned on. As shown in fig. 2, as seen from the dashed path from the first charge pump to the second charge pump, pmos1, pmos2, pmos1' and Pmos2' are all turned on, and the capacitor C1 is connected in series with the capacitor C2, since the two terminals of the capacitor C2 have a voltage difference of 1.4V-1.7V, the voltage at the first terminal a ' of the capacitor C2 is 1.4V-1.7V, and the voltage at the second terminal B ' of the capacitor C2 is 2.8V-3.4V, so that the second voltage VOUT output by the signal output terminal D ' of the second charge pump is 2.8V-3.4V.
In the embodiment of the invention, the voltage pump circuit can boost the first voltage output by the processor to the second voltage through the first voltage pump and the second voltage pump, the second voltage can drive the level shifter to work, and when the chip is converted from the low power consumption mode to the working mode, the first voltage can be boosted to different second voltages through the first charge pump and the second charge pump, so that the requirements of different IP modules on different voltage domains under the condition that the chip is converted from the low power consumption mode to the working mode are met.
Fig. 3 is a schematic structural diagram of another low power consumption control circuit according to an embodiment of the present invention, and as shown in fig. 3, on the basis of the low power consumption control circuits shown in fig. 1 and fig. 2, the level shifter further includes a differential NMOS transistor, and the differential NMOS transistor is connected to a signal output terminal D of the charge pump circuit. As shown in fig. 3, specifically, the differential NMOS transistor is connected to the signal output terminal D of the first charge pump, and the processor and the level shifter are not specifically shown in fig. 3.
The differential NMOS tube is a 3.3V NMOS tube, and the starting voltage is required to be more than 1V for starting the differential NMOS tube. As shown in fig. 3, the signal output terminal D of the first charge pump outputs a turn-on voltage to the differential NMOS transistor, where the turn-on voltage is a third voltage VDD2, for example, VDD2 is 1.4V-1.7V, and the turn-on voltage output from the signal output terminal D of the first charge pump to the differential NMOS transistor is 1.4V-1.7V, and the turn-on voltage is greater than 1V, so that the purpose of turning on the differential NMOS transistor can be achieved.
In the low power consumption control circuit provided by the embodiment of the invention, the differential NMOS transistor is connected to the signal output end of the first charge pump, the signal output end of the first charge pump can output a starting voltage larger than 1V to the differential NMOS transistor, so that the purpose of starting the differential NMOS transistor through the starting voltage can be achieved when the low power consumption kernel is converted from a low power consumption mode to a working mode, the differential NMOS transistor is also commonly applied to full-amplitude input regulation and control of the input stage of the level shifter, and the design that the signal output end D of the first charge pump outputs the starting voltage to the differential NMOS transistor can firstly meet the requirement of the full-amplitude input regulation and control of the level shifter, namely meet the requirement of the same IP module in a chip on voltage domains with different sizes and the regulation of power-on sequences of different components.
In the embodiment of the present invention, the embodiment corresponding to fig. 3 may be further designed, and the signal output end D' of the second charge pump may be connected to the ADC module, so as to satisfy the normal operation of the ADC module when the low power consumption mode is converted into the operating mode, thereby satisfying the requirements of different IP modules for voltage domains with different sizes.
Fig. 4 is a schematic structural diagram of a microprocessor chip according to an embodiment of the present invention, and as shown in fig. 4, the microprocessor chip includes a low power consumption control circuit, where the description of the low power consumption control circuit may refer to the description of the low power consumption control circuit in the embodiment shown in fig. 1 or fig. 3, and details are not repeated here.
In the embodiment of the present invention, the micro Processing chip includes, but is not limited to, a Micro Controller Unit (MCU), a DSP, a Microprocessor Unit (MPU), a Central Processing Unit (CPU), and other micro Central control chips and system-on-chip chips capable of Processing digital signals and analog signals, or performing functions such as signal control, instruction Processing, and operation.
In the micro-processing chip provided by the embodiment of the invention, the low-power consumption control circuit comprises a processor, a charge pump circuit and a level shifter, wherein the processor outputs a first voltage to the charge pump circuit, and the charge pump circuit boosts the first voltage to a second voltage and outputs the second voltage to the level shifter so as to enable the level shifter to work under the driving of the second voltage.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions in actual implementation, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) or a Processor (Processor) to execute some steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A low power consumption control circuit, comprising: the charge pump circuit comprises a processor, a charge pump circuit and a level shifter, wherein the processor is connected with the input end of the charge pump circuit, and the level shifter is connected with the output end of the charge pump circuit;
the processor is used for outputting a first voltage to the charge pump circuit;
the charge pump circuit is used for boosting the first voltage to a second voltage and outputting the second voltage to a level shifter;
the level shifter is used for working under the driving of the second voltage.
2. The low power consumption control circuit of claim 1, wherein the charge pump circuit comprises a clock generator and a plurality of charge pumps, the clock generator being connected to each of the charge pumps;
the clock generator is used for outputting a clock signal to each charge pump so as to control the plurality of charge pumps to boost the first voltage to the second voltage.
3. The low power consumption control circuit of claim 2, wherein the charge pump comprises a charge switch, a discharge switch, and a capacitor;
the clock generator is used for controlling the charging switch to be switched on or switched off and controlling the discharging switch to be switched on or switched off;
the capacitor is used for charging when the charging switch is turned on and the discharging switch is turned off;
the capacitor is used for discharging when the discharging switch is turned on and the charging switch is turned off.
4. The low power consumption control circuit according to claim 3, wherein the charge switch comprises a first NMOS transistor, a second NMOS transistor and a third PMOS transistor, and the discharge switch comprises a first PMOS transistor and a second PMOS transistor;
the grid electrode of the first NMOS tube is connected to the clock generator, the source electrode of the first NMOS tube is connected to the first end of the capacitor, and the drain electrode of the first NMOS tube is grounded;
the grid electrode of the second NMOS tube is connected to the clock generator, the source electrode of the second NMOS tube is connected to the signal output end, and the drain electrode of the second NMOS tube is grounded;
the grid electrode of the third PMOS tube is connected to the signal output end, the source electrode of the third PMOS tube is connected to the signal input end, and the drain electrode of the third PMOS tube is connected to the second end of the capacitor;
the grid electrode of the first PMOS tube is connected to the clock generator, the source electrode of the first PMOS tube is connected to the signal input end, and the drain electrode of the first PMOS tube is connected to the first end of the capacitor;
the grid electrode of the second PMOS tube is connected to the clock generator, the source electrode of the second PMOS tube is connected to the second end of the capacitor, and the drain electrode of the second PMOS tube is connected to the signal output end.
5. The low power consumption control circuit of claim 4, wherein when the clock signal output by the clock generator is a high level signal, the first NMOS transistor, the second NMOS transistor, and the third PMOS transistor are turned on, the first PMOS transistor and the second PMOS transistor are turned off, and the signal output terminal outputs a low level signal.
6. The low power consumption control circuit of claim 4, wherein when the clock signal output by the clock generator is a low level signal, the first NMOS transistor, the second NMOS transistor, and the third PMOS transistor are turned off, the first PMOS transistor and the second PMOS transistor are turned on, and the signal output terminal outputs a high level signal.
7. The low power consumption control circuit according to any one of claims 2 to 6, wherein the plurality of charge pumps comprises a first charge pump and a second charge pump, the processor is connected to the first charge pump and the second charge pump, an output terminal of the first charge pump is connected to the second charge pump, and an output terminal of the second charge pump is connected to the level shifter;
the processor is configured to output the first voltage to the first charge pump;
the first charge pump is used for outputting a third voltage to the second charge pump under the control of the clock signal and under the driving of the first voltage;
the second charge pump is used for outputting the second voltage to the level shifter under the control of the clock signal and under the driving of the third voltage.
8. The low power consumption control circuit of claim 7, wherein the first charge pump or the second charge pump comprises: the charge switch comprises a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube and a third PMOS tube, and the discharge switch comprises a first PMOS tube and a second PMOS tube;
the grid electrode of the first NMOS tube is connected to the clock generator, the source electrode of the first NMOS tube is connected to the first end of the capacitor, and the drain electrode of the first NMOS tube is grounded;
the grid electrode of the second NMOS tube is connected to the clock generator, the source electrode of the second NMOS tube is connected to the signal output end, and the drain electrode of the second NMOS tube is grounded;
the grid electrode of the third PMOS tube is connected to the signal output end, the source electrode of the third PMOS tube is connected to the signal input end, and the drain electrode of the third PMOS tube is connected to the second end of the capacitor;
the grid electrode of the first PMOS tube is connected to the clock generator, the source electrode of the first PMOS tube is connected to the signal input end, and the drain electrode of the first PMOS tube is connected to the first end of the capacitor;
the grid electrode of the second PMOS tube is connected to the clock generator, the source electrode of the second PMOS tube is connected to the second end of the capacitor, and the drain electrode of the second PMOS tube is connected to the signal output end;
the signal output end of the first charge pump is connected to the signal input end of the second charge pump.
9. The low power consumption control circuit according to any one of claims 1 to 6, wherein the level shifter comprises: a differential NMOS tube;
the differential NMOS tube is connected to the signal output end of the charge pump circuit.
10. A microprocessor chip comprising the low power consumption control circuit of any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211635679.2A CN115833576A (en) | 2022-12-19 | 2022-12-19 | Low-power consumption control circuit and micro-processing chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211635679.2A CN115833576A (en) | 2022-12-19 | 2022-12-19 | Low-power consumption control circuit and micro-processing chip |
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| CN115833576A true CN115833576A (en) | 2023-03-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202211635679.2A Pending CN115833576A (en) | 2022-12-19 | 2022-12-19 | Low-power consumption control circuit and micro-processing chip |
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| CN1792025A (en) * | 2003-05-20 | 2006-06-21 | 索尼株式会社 | Power supply voltage converting circuit, method for controlling the same, display device, and mobile terminal |
| KR20060122462A (en) * | 2005-05-27 | 2006-11-30 | 삼성전자주식회사 | Charge pump and low-power dc-dc converter using it |
| CN101212179A (en) * | 2006-12-25 | 2008-07-02 | 普诚科技股份有限公司 | Voltage boost circuit and voltage level shifter |
| CN113991999A (en) * | 2021-10-18 | 2022-01-28 | 上海华虹宏力半导体制造有限公司 | Charge pump boosting system |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1792025A (en) * | 2003-05-20 | 2006-06-21 | 索尼株式会社 | Power supply voltage converting circuit, method for controlling the same, display device, and mobile terminal |
| KR20060122462A (en) * | 2005-05-27 | 2006-11-30 | 삼성전자주식회사 | Charge pump and low-power dc-dc converter using it |
| CN101212179A (en) * | 2006-12-25 | 2008-07-02 | 普诚科技股份有限公司 | Voltage boost circuit and voltage level shifter |
| CN113991999A (en) * | 2021-10-18 | 2022-01-28 | 上海华虹宏力半导体制造有限公司 | Charge pump boosting system |
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