CN115832020A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Abstract

The application provides a manufacturing method of a semiconductor device, which comprises the following steps: firstly, providing a first substrate and a second substrate, wherein the second substrate comprises a second substrate layer, the first substrate comprises a first substrate layer, a first preparatory top layer silicon layer and a buried oxide layer which are sequentially stacked, the first substrate also comprises a groove, and the groove penetrates into the first preparatory top layer silicon layer from the buried oxide layer; then, bonding the first substrate and the second substrate by taking the oxygen buried layer and the second substrate layer as bonding interfaces, and removing the first substrate layer to obtain an initial semiconductor device; and finally, processing the initial semiconductor device by adopting a GAA technology to obtain a final semiconductor device. The groove penetrates into the first preparation top silicon layer from the buried oxide layer, and the position and the shape of the groove can be controlled before bonding, so that the first groove with regular appearance can be obtained before forming a GAA structure, and the reliability and the performance of a final semiconductor device obtained after processing by adopting a GAA technology are high.

Description

Method for manufacturing semiconductor device and semiconductor device

Technical Field

The present disclosure relates to the field of semiconductors, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.

Background

With the coming of 5nm nodes, higher requirements are put on the gating capacity, size and power consumption of transistors, which means that 3D FinFET (Fin Field Effect Transistor) will meet its limit because the distance between fins is too close, leakage current reappears, the fins are difficult to keep upright under the action of internal stress after reaching a certain height, and the limit of various physical materials allows the 3D FinFET to gradually exit from the historical stage.

The GAA (Gate All Around) nanotechnology compares in present 3D FinFET trigate structure, will redesign transistor bottom layer structure, overcomes the physics of current technology, performance limit, strengthens grid control, and the performance promotes greatly. The technology is characterized in that four sides of a channel are wrapped by a grid, a source electrode and a drain electrode are not contacted with a substrate any more, and the basic structure and the function of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) are realized by utilizing a plurality of linear (which can be understood as a stick shape) or flat plate-shaped or sheet-shaped source electrodes and drain electrodes which are transversely vertical to the grid. The design has solved various problems that bring after grid interval size reduces to a great extent, including capacitive effect etc. in addition the channel is wrapped up by grid four sides, therefore the channel current is also more smooth and easy than the trilateral parcel of FinFET. After the GAA technique is applied, it is estimated that semiconductor manufacturing problems of 5nm or less size can be substantially solved.

The existing GAA technology is basically integrated by continuously stacking SiGe or Si materials On planar Si, while little introduction is made to the integration technology On SOI (Silicon On Insulator) substrate, which undoubtedly presents a great challenge to the reliability and performance extension of SOI mosfets.

In the prior art, the pattern of the trench formed by etching the buried oxide layer below the top silicon cannot be well controlled because the anisotropy is poor although the selectivity is good during wet lateral etching, and the obtained etched cross section is in the shape of a circular arc, as shown in fig. 1. Inaccurate etch times and rates result in etching profiles that are smaller than the line width of the top silicon, as shown by the dashed lines, thus preventing GAA structures, and also provide significant benefits and throughput challenges if the etchant chemistry is changed more frequently to maintain the same initial etch rate.

Therefore, a method for integrating a GAA structure on an SOI substrate is needed to make up for the shortage of SOI MOSFETs in this field, and to solve the problem in the prior art that the reliability and performance of devices are poor due to the instability of the etching process.

Disclosure of Invention

The present application mainly aims to provide a method for manufacturing a semiconductor device and a semiconductor device, so as to solve the problem in the prior art that the reliability and performance of the device are poor due to the instability of an etching process.

In order to achieve the object, according to an aspect of the present application, there is provided a method of manufacturing a semiconductor device, the method including: providing a first substrate and a second substrate, wherein the second substrate comprises a second substrate layer, the first substrate comprises a first substrate layer, a first preparation top layer silicon layer and a buried oxide layer which are sequentially stacked, the first substrate further comprises a groove, and the groove penetrates into the first preparation top layer silicon layer from the buried oxide layer; bonding the first substrate and the second substrate by taking the buried oxide layer and the second substrate layer as bonding interfaces, and removing the first substrate layer to obtain an initial semiconductor device; and processing the initial semiconductor device by adopting a GAA technology to obtain a final semiconductor device.

Optionally, processing the initial semiconductor device using GAA techniques includes: removing part of the first prepared top silicon layer, wherein the rest first prepared top silicon layer forms a top silicon layer, the top silicon layer comprises a plurality of top silicon parts and at least one nanowire, each top silicon part is respectively positioned on the oxygen burying layers at two sides of the groove, two ends of the nanowire are respectively contacted with the two top silicon parts at two sides of the groove, and the nanowire is positioned at one side of the groove far away from the second substrate layer; and forming a gate structure in the groove, on part of the exposed surface of the buried oxide layer and part of the exposed surface of the nanowire, wherein the gate structure surrounds part of the side surface of the nanowire.

Optionally, after forming a gate structure in the trench, on a part of the exposed surface of the buried oxide layer and on a part of the exposed surface of the nanowire, the method further comprises: respectively oxidizing and implanting ions into the top silicon parts to obtain a drain electrode and a source electrode; and carrying out ion implantation on the exposed nanowire to form an LDD structure.

Optionally, removing a portion of the first preliminary top silicon layer, and the remaining first preliminary top silicon layer forming a top silicon layer, includes: and removing part of the first prepared top silicon layer by using electron beam lithography and reactive ion etching processes to obtain the top silicon layer.

Optionally, providing a first substrate comprising: providing a first preparation substrate, wherein the first preparation substrate comprises a first substrate layer, a second preparation top layer silicon layer and a preparation buried oxide layer, the first substrate layer and the second preparation top layer silicon layer are sequentially laminated, and the preparation buried oxide layer covers all exposed surfaces of the first substrate layer and the second preparation top layer silicon layer; and removing part of the second preparation top layer silicon layer and part of the preparation buried oxide layer, forming a plurality of trenches penetrating through part of the preparation buried oxide layer to the second preparation top layer silicon layer, enabling the rest of the preparation buried oxide layer to be only positioned on the surface, far away from the first substrate layer, of the second preparation top layer silicon layer, enabling the rest of the preparation buried oxide layer to form the buried oxide layer, and enabling the rest of the second preparation top layer silicon layer to form the first preparation top layer silicon layer to obtain the first substrate.

Optionally, providing a first preparation substrate comprising: providing a silicon wafer; oxidizing all exposed surfaces of the silicon wafer to form the prepared oxygen burying layer, wherein the rest silicon wafer forms a first prepared substrate layer; and forming the second preparation top layer silicon layer in the first preparation substrate layer by using an ion implantation process, and forming the first substrate layer by using the rest first preparation substrate layer to obtain the first preparation base.

Optionally, after bonding the first substrate and the second substrate, the method further comprises: removing the first substrate layer using a grinding and polishing process; and etching and removing part of the first preparation top silicon layer, so that the thickness of the remaining first preparation top silicon layer is in a preset range.

Optionally, the predetermined range is 12nm-15nm.

Optionally, the buried oxide layer has a thickness in a range of 140nm to 150nm.

According to another aspect of the present application, there is provided a semiconductor device fabricated by any one of the methods.

According to the technical scheme, in the manufacturing method of the semiconductor device, firstly, a first substrate and a second substrate are provided, the second substrate comprises a second substrate layer, the first substrate comprises a first substrate layer, a first preparation top layer silicon layer and an oxygen burying layer which are sequentially stacked, the first substrate further comprises a groove, and the groove penetrates into the first preparation top layer silicon layer from the oxygen burying layer; then, bonding the first substrate and the second substrate by taking the buried oxide layer and the second substrate layer as bonding interfaces, and removing the first substrate layer to obtain an initial semiconductor device; and finally, processing the initial semiconductor device by adopting a GAA technology to obtain a final semiconductor device. Compared with the problem that the reliability and performance of the device are poor due to instability of an etching process in the prior art, the manufacturing method of the semiconductor device comprises the steps of providing the first substrate layer, the first preparation top layer silicon layer, the buried oxide layer and the first substrate of the groove, providing the second substrate comprising the second substrate layer, and bonding the first substrate and the second substrate by using the buried oxide layer and the second substrate layer as bonding interfaces, wherein the groove penetrates into the first preparation top layer silicon layer from the buried oxide layer, and the position and the shape of the groove can be effectively controlled before bonding, so that the first groove with regular appearance can be obtained before forming the GAA structure, the problem that the groove between the first preparation top layer silicon layer and the substrate needs to be etched through the first preparation top layer silicon layer in the forming process of the GAA structure in the prior art is avoided, the problem that the appearance and the outline of the groove cannot meet the expected requirements due to instability of the etching process, the reliability and the performance of the device are poor due to instability of the etching process, and the problem that the semiconductor device is finally processed with poor reliability and the semiconductor device is obtained after the GAA process is adopted.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:

FIG. 1 is a schematic diagram of a structure obtained after a trench is formed by etching in the prior art;

fig. 2 shows a flow diagram of a method of fabricating a semiconductor device according to an embodiment of the present application;

fig. 3 to 9 respectively show schematic structural diagrams obtained after various process steps of a manufacturing method of a semiconductor device according to an embodiment of the present application;

fig. 10 shows a schematic structural diagram of a cross section of a semiconductor device according to an embodiment of the present application.

Wherein the figures include the following reference numerals:

10. a first substrate; 20. a second substrate; 30. a gate structure; 40. a drain electrode; 50. a source stage; 60. an LDD structure; 101. a first substrate layer; 102. a first preliminary top silicon layer; 103. an oxygen burying layer; 104. a trench; 105. a top silicon layer; 106. a top silicon portion; 107. a nanowire; 108. a first preliminary substrate; 109. a second preliminary top silicon layer; 110. preparing an oxygen burying layer; 111. a silicon wafer; 112. a first preliminary substrate layer; 201. a second substrate layer; 300. a gate oxide layer; 301. and a gate.

Detailed Description

It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.

As described in the background art, in order to solve the problem of poor reliability and performance of the device due to instability of the etching process in the prior art, the present application provides a method for manufacturing a semiconductor device and a semiconductor device.

According to an embodiment of the present application, a method of fabricating a semiconductor device is provided.

Fig. 2 is a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present application. As shown in fig. 2, the method comprises the steps of:

step S101, as shown in fig. 6, providing a first substrate 10 and a second substrate 20, where the second substrate 20 includes a second substrate layer 201, the first substrate 10 includes a first substrate layer 101, a first preliminary top silicon layer 102, and a buried oxide layer 103, which are sequentially stacked, the first substrate 10 further includes a trench 104, and the trench 104 penetrates from the buried oxide layer 103 into the first preliminary top silicon layer 102;

step S102, as shown in fig. 7, bonding the first substrate 10 and the second substrate 20 with the buried oxide layer 103 and the second substrate layer 201 as bonding interfaces, and removing the first substrate layer 101 to obtain an initial semiconductor device;

step S103, processing the initial semiconductor device by using GAA technology, as shown in fig. 9, to obtain a final semiconductor device.

In the manufacturing method of the semiconductor device, first, a first substrate and a second substrate are provided, the second substrate includes a second substrate layer, the first substrate includes a first substrate layer, a first preliminary top silicon layer and a buried oxide layer which are sequentially stacked, the first substrate further includes a trench, and the trench penetrates into the first preliminary top silicon layer from the buried oxide layer; then, bonding the first substrate and the second substrate by using the buried oxide layer and the second substrate layer as bonding interfaces, and removing the first substrate layer to obtain an initial semiconductor device; and finally, processing the initial semiconductor device by adopting a GAA technology to obtain a final semiconductor device. Compared with the problem that the reliability and performance of the device are poor due to instability of an etching process in the prior art, the method for manufacturing the semiconductor device comprises the steps of providing the first substrate including the first substrate layer, the first preparatory top layer silicon layer, the buried oxide layer and the trench, providing the second substrate including the second substrate layer, bonding the first substrate and the second substrate by using the buried oxide layer and the second substrate layer as bonding interfaces, wherein the trench penetrates through the first preparatory top layer silicon layer from the buried oxide layer, and the position and the shape of the trench can be effectively controlled before bonding, so that the first trench with regular shape can be obtained before forming the GAA structure, the problem that the trench between the first preparatory top layer silicon layer and the substrate needs to be etched through the first preparatory top layer silicon layer in the forming process of the GAA structure in the prior art is avoided, the problem that the shape and the profile of the trench cannot meet the expected requirements due to instability of the etching process, the reliability and performance of the device are poor due to instability of the etching process, and the problem that the semiconductor device is finally obtained after the poor reliability and performance of the GAA is obtained by adopting the GAA process.

In one embodiment, the first substrate and the second substrate are bonded at a high temperature.

Specifically, in the prior art, since the method for etching the buried oxide layer is relatively single, and is mainly focused on wet etching, and the etching is controlled by the etching rate and time, the pattern of the trench formed by etching the buried oxide layer under the top silicon by using BHF (Buffered hydrogen fluoride) cannot be well controlled, mainly because the selectivity is good but the anisotropy is poor during wet lateral etching, the obtained etching profile is in a circular arc shape, if the etching time and rate are not accurate, the etched profile is smaller than the line width of the top silicon, and thus the GAA structure cannot be obtained, and furthermore, if the etchant chemistry is changed more frequently to maintain the same initial etching rate, this undoubtedly brings great challenges to the yield and production capacity.

According to a specific embodiment of the present application, processing the initial semiconductor device using GAA techniques comprises: as shown in fig. 8, a portion of the first preliminary top silicon layer 102 is removed, the remaining first preliminary top silicon layer 102 forms a top silicon layer 105, the top silicon layer 105 includes a plurality of top silicon portions 106 and at least one nanowire 107, each of the top silicon portions 106 is located on the buried oxide layer 103 on both sides of the trench 104, both ends of the nanowire 107 are in contact with the two top silicon portions 106 on both sides of the trench 104, and the nanowire 107 is located on a side of the trench 104 away from the second substrate layer 201; as shown in fig. 9, a gate structure is formed in the trench 104, on a portion of the exposed surface of the buried oxide layer 103 and a portion of the exposed surface of the nanowire 107, and the gate structure surrounds a portion of the side surface of the nanowire 107. The plurality of top silicon parts and the at least one nanowire are obtained by removing part of the first prepared top silicon layer, the nanowire is ensured to be positioned on one side of the groove far away from the second substrate layer, and the grid structure is formed, so that the grid structure can wrap part of the nanowire along the preset direction, the control performance of the grid structure on the nanowire is ensured to be good, and the reliability and the performance of the final semiconductor device are further ensured to be high.

As shown in fig. 9, the gate structure including a gate oxide layer and a gate is formed in the trench 104, on a portion of the exposed surface of the buried oxide layer 103 and on a portion of the exposed surface of the nanowire 107, and includes: forming a gate oxide layer (not shown) in the trench 104, on a portion of the exposed surface of the buried oxide layer 103 and a portion of the side surface of the nanowire 107; forming the gate on the exposed surface of the gate oxide layer, wherein the gate fills up the remaining trench, and a first distance is greater than a second distance, the first distance is a distance between the surface of the gate away from the second substrate 20 and the second substrate 20, the second distance is a distance between the surface of the nanowire 107 away from the second substrate 20 and the second substrate 20, and the gate oxide layer constitute the gate structure 30.

Specifically, the nanowire may also be configured as a nanosheet, and since all four sides of the nanowire or the nanosheet are included by the gate structure, the control capability of the gate structure on the nanowire or the nanosheet is improved, and physical scaling and performance limitations in the prior art can be overcome.

In a specific embodiment, the gate structure is grown by thermal oxidation and LPCVD (Low Pressure Chemical Vapor Deposition), and the GAA structure is formed by photolithography and etching processes.

According to another specific embodiment of the present application, after forming a gate structure in the trench, on a portion of the exposed surface of the buried oxide layer and on a portion of the exposed surface of the nanowire, the method further includes: as shown in fig. 9, a plurality of the top silicon portions 106 are oxidized and ion-implanted to obtain the drain 40 and the source 50, respectively; the exposed nanowire 107 is ion implanted to form the LDD structure 60. The drain electrode and the source electrode are obtained by oxidizing and ion-implanting the top silicon part, and the LDD structure is obtained by ion-implanting the exposed nanowire, so that the reliability and the performance of the final semiconductor device are further ensured to be higher.

Specifically, the LDD structure is to provide a low doped drain region near the drain of the nanowire, and the low doped drain region can also bear a partial voltage, so as to prevent the hot electron degradation effect, and further ensure the reliability and performance of the final semiconductor device.

In a specific embodiment, as shown in fig. 10 along a cross-section AA' of fig. 9, the nanowire 107 is wrapped by four sides of the gate structure 30, specifically, the nanowire 107 is wrapped by four sides of the gate oxide layer 300 and the gate 301 in sequence, and the gate structure is in contact with the second substrate layer 201.

According to another specific embodiment of the present application, removing a portion of the first preliminary top silicon layer, the remaining first preliminary top silicon layer forming a top silicon layer, comprises: and removing part of the first preliminary top silicon layer by using electron beam lithography and reactive ion etching processes to obtain the top silicon layer. The top silicon layer is obtained by removing part of the first prepared top silicon layer through electron beam lithography and reactive ion etching processes, so that the nanowires and the top silicon part structure can be obtained, the subsequently formed gate structure can wrap part of the nanowires along the preset direction, the control performance of the gate structure on the nanowires is good, and the reliability and the performance of the final semiconductor device are further guaranteed to be high.

According to a specific embodiment of the present application, there is provided a first substrate comprising: as shown in fig. 5, providing a first preliminary base 108, wherein the first preliminary base 108 includes the first substrate layer 101, a second preliminary top silicon layer 109, and a preliminary buried oxide layer 110, the first substrate layer 101 and the second preliminary top silicon layer 109 are sequentially stacked, and the preliminary buried oxide layer 110 covers all exposed surfaces of the first substrate layer 101 and the second preliminary top silicon layer 109; as shown in fig. 6, a portion of the second preliminary top silicon layer 109 and a portion of the preliminary buried oxide layer 110 are removed, a plurality of trenches 104 penetrating a portion of the preliminary buried oxide layer 110 into the second preliminary top silicon layer 109 are formed, the remaining preliminary buried oxide layer 110 is only located on a surface of the second preliminary top silicon layer 109 away from the first substrate layer 101, the remaining preliminary buried oxide layer 110 forms the buried oxide layer 103, and the remaining second preliminary top silicon layer 109 forms the first preliminary top silicon layer 102, thereby obtaining the first substrate 10. The first preparation substrate comprising the first substrate layer, the second preparation top layer silicon layer and the preparation buried oxide layer is provided, and then a plurality of trenches penetrating through a part of the preparation buried oxide layer and the second preparation top layer silicon layer can be formed by removing a part of the second preparation top layer silicon layer and a part of the preparation buried oxide layer, wherein the trenches penetrate through the second preparation top layer silicon layer from the preparation buried oxide layer, and the positions and the shapes of the trenches can be effectively controlled before bonding, so that the first trenches with regular shapes can be obtained before the GAA structure is formed, the problem that in the prior art, the trenches between the first preparation top layer silicon layer and the substrate need to be etched through the first preparation top layer silicon layer in the forming process of the GAA structure, the appearance and the outline of the trenches cannot meet the expected requirements due to instability of an etching process, and the reliability and the performance of a device are poor is further solved, and the reliability and the performance of the semiconductor device obtained after the GAA technology is further guaranteed to be high.

Specifically, the trench is formed by photolithography and a one-step dry etching process, the thickness of the second preliminary top silicon layer is removed in a range of 30-50 angstroms, and then the photoresist & polymer on the surface is removed by a dry and wet photoresist removing process.

According to another specific embodiment of the present application, there is provided a first preparation substrate comprising: as shown in fig. 3, a silicon wafer 111 is provided; as shown in fig. 4, oxidizing all exposed surfaces of the silicon wafer 111 to form the preliminary buried oxide layer 110, and forming a first preliminary underlying layer 112 on the remaining silicon wafer 111; as shown in fig. 5, the second preliminary top silicon layer 109 is formed in the first preliminary base layer 112 by an ion implantation process, and the first base layer 101 is formed in the remaining first preliminary base layer 112, thereby obtaining the first preliminary base 108. The preparation buried oxide layer is obtained by oxidizing the silicon wafer, and the second preparation top silicon layer is formed in the first preparation substrate layer through an ion implantation process to obtain the first preparation substrate, so that the first preparation substrate can be obtained simply, and the cost of the semiconductor device is low.

Specifically, the temperature for oxidizing the silicon wafer is 900-950 ℃, the B element is implanted in the ion implantation process, wherein the ion implantation dosage is 10 ¹⁷ /cm ² Left and right.

According to another specific embodiment of the present application, after bonding the first substrate and the second substrate, the method further includes: removing the first substrate layer by using a grinding and polishing process; and etching and removing part of the first preliminary top silicon layer to ensure that the thickness of the residual first preliminary top silicon layer is within a preset range. And removing the first substrate layer by grinding and polishing processes, and etching and removing part of the first preparatory top silicon layer to ensure that the thickness of the residual first preparatory top silicon layer is within a preset range, so that the thickness of the subsequently obtained nanowire and the top silicon part is within the preset range, and the reliability and the performance of the final semiconductor device are further ensured to be higher.

According to a specific embodiment of the present application, the predetermined range is 12nm to 15nm.

According to another specific embodiment of the present application, the thickness of the buried oxide layer is in a range of 140nm to 150nm.

In one embodiment, after the source and the drain are formed, inter Level Dielectric (ILD) and hole layer fabrication and metal routing are performed to obtain the final semiconductor device.

According to an embodiment of the present application, there is also provided a semiconductor device manufactured by any one of the above methods.

Compared with the problem of poor reliability and performance of the device caused by instability of an etching process in the prior art, the semiconductor device provided by the application is manufactured by any one of the methods, the semiconductor device is manufactured by providing the first substrate comprising the first substrate layer, the first preliminary top silicon layer, the buried oxide layer and the trench, providing the second substrate comprising the second substrate layer, and bonding the first substrate and the second substrate by using the buried oxide layer and the second substrate layer as bonding interfaces, because the trench penetrates from the buried oxide layer to the first preliminary top silicon layer and the position and the shape of the trench can be effectively controlled before bonding, the first trench with regular morphology can be obtained before forming the GAA structure, the problem that the trench is required to be etched through the first preliminary top silicon layer during forming the GAA structure to form the trench between the first preliminary top silicon layer and the substrate, and the problem that the reliability and the performance of the device are poor due to instability of the etching process, and the problem that the reliability and the performance of the semiconductor device are finally high after the semiconductor device is processed by the poor technology is ensured.

In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:

1) In the method for manufacturing the semiconductor device, first, a first substrate and a second substrate are provided, the second substrate includes a second substrate layer, the first substrate includes a first substrate layer, a first preparatory top silicon layer and a buried oxide layer which are sequentially stacked, the first substrate further includes a trench, and the trench penetrates into the first preparatory top silicon layer from the buried oxide layer; then, bonding the first substrate and the second substrate by using the buried oxide layer and the second substrate layer as bonding interfaces, and removing the first substrate layer to obtain an initial semiconductor device; and finally, processing the initial semiconductor device by adopting a GAA technology to obtain a final semiconductor device. Compared with the problem that the reliability and performance of the device are poor due to instability of an etching process in the prior art, the method for manufacturing the semiconductor device comprises the steps of providing the first substrate including the first substrate layer, the first preparatory top layer silicon layer, the buried oxide layer and the trench, providing the second substrate including the second substrate layer, bonding the first substrate and the second substrate by using the buried oxide layer and the second substrate layer as bonding interfaces, wherein the trench penetrates through the first preparatory top layer silicon layer from the buried oxide layer, and the position and the shape of the trench can be effectively controlled before bonding, so that the first trench with regular shape can be obtained before forming the GAA structure, the problem that the trench between the first preparatory top layer silicon layer and the substrate needs to be etched through the first preparatory top layer silicon layer in the forming process of the GAA structure in the prior art is avoided, the problem that the shape and the profile of the trench cannot meet the expected requirements due to instability of the etching process, the reliability and performance of the device are poor due to instability of the etching process, and the problem that the semiconductor device is finally obtained after the poor reliability and performance of the GAA is obtained by adopting the GAA process.

2) The semiconductor device of the present application is manufactured by any one of the above methods, and compared with the problem of poor reliability and performance of the device caused by instability of an etching process in the prior art, the semiconductor device of the present application is manufactured by providing the first substrate including the first substrate layer, the first preliminary top layer silicon layer, the buried oxide layer, and the trench, providing the second substrate including the second substrate layer, and bonding the first substrate and the second substrate using the buried oxide layer and the second substrate layer as bonding interfaces, wherein the trench penetrates from the buried oxide layer to the first preliminary top layer silicon layer, and the position and the shape of the trench can be effectively controlled before bonding, so that the first trench having a regular shape can be obtained before forming the GAA structure, the problem of the prior art that the trench between the first preliminary top layer silicon layer and the substrate needs to be etched through the first preliminary top layer silicon layer during forming the GAA structure, the problem of poor reliability and performance of the semiconductor device caused by instability of the etching process, and the problem of poor reliability and performance of the semiconductor device obtained by adopting the prior art are avoided.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (10)

1. A method of fabricating a semiconductor device, the method comprising:

providing a first substrate and a second substrate, wherein the second substrate comprises a second substrate layer, the first substrate comprises a first substrate layer, a first preparation top layer silicon layer and a buried oxide layer which are sequentially stacked, the first substrate further comprises a groove, and the groove penetrates into the first preparation top layer silicon layer from the buried oxide layer;

bonding the first substrate and the second substrate by taking the buried oxide layer and the second substrate layer as bonding interfaces, and removing the first substrate layer to obtain an initial semiconductor device;

and processing the initial semiconductor device by adopting a GAA technology to obtain a final semiconductor device.

2. The method of claim 1, wherein processing the initial semiconductor device using GAA techniques comprises:

removing part of the first prepared top silicon layer, wherein the rest first prepared top silicon layer forms a top silicon layer, the top silicon layer comprises a plurality of top silicon parts and at least one nanowire, each top silicon part is respectively positioned on the oxygen burying layers at two sides of the groove, two ends of the nanowire are respectively contacted with the two top silicon parts at two sides of the groove, and the nanowire is positioned at one side of the groove far away from the second substrate layer;

and forming a gate structure in the groove, on part of the exposed surface of the buried oxide layer and part of the exposed surface of the nanowire, wherein the gate structure surrounds part of the side surface of the nanowire.

3. The method of claim 2, wherein after forming a gate structure within the trench, on a portion of an exposed surface of the buried oxide layer, and on a portion of an exposed surface of the nanowire, the method further comprises:

respectively oxidizing and implanting ions into the top silicon parts to obtain a drain electrode and a source electrode;

and carrying out ion implantation on the exposed nanowire to form an LDD structure.

4. The method of claim 2, wherein removing a portion of the first preliminary top silicon layer, the remaining first preliminary top silicon layer forming a top silicon layer, comprises:

and removing part of the first prepared top silicon layer by using electron beam lithography and reactive ion etching processes to obtain the top silicon layer.

5. The method of claim 1, wherein providing a first substrate comprises:

providing a first preparation substrate, wherein the first preparation substrate comprises a first substrate layer, a second preparation top layer silicon layer and a preparation buried oxide layer, the first substrate layer and the second preparation top layer silicon layer are sequentially laminated, and the preparation buried oxide layer covers all exposed surfaces of the first substrate layer and the second preparation top layer silicon layer;

and removing part of the second preparation top layer silicon layer and part of the preparation buried oxide layer, forming a plurality of trenches penetrating through part of the preparation buried oxide layer to the second preparation top layer silicon layer, enabling the rest of the preparation buried oxide layer to be only positioned on the surface, far away from the first substrate layer, of the second preparation top layer silicon layer, enabling the rest of the preparation buried oxide layer to form the buried oxide layer, and enabling the rest of the second preparation top layer silicon layer to form the first preparation top layer silicon layer to obtain the first substrate.

6. The method of claim 5, wherein providing a first preliminary substrate comprises:

providing a silicon wafer;

oxidizing all exposed surfaces of the silicon wafer to form the prepared oxygen burying layer, wherein the rest silicon wafer forms a first prepared substrate layer;

and forming the second preparation top layer silicon layer in the first preparation substrate layer by using an ion implantation process, and forming the first substrate layer by using the rest first preparation substrate layer to obtain the first preparation base.

7. The method of claim 1, wherein after bonding the first and second substrates, the method further comprises:

removing the first substrate layer using a grinding and polishing process;

and etching and removing part of the first preparation top silicon layer, so that the thickness of the remaining first preparation top silicon layer is in a preset range.

8. The method of claim 7, wherein the predetermined range is 12nm to 15nm.

9. The method according to any of claims 1 to 8, wherein the buried oxide layer has a thickness in the range of 140nm-150nm.

10. A semiconductor device manufactured by the method according to any one of claims 1 to 9.

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