CN108010968B - Fin type field effect transistor and manufacturing method thereof - Google Patents
Fin type field effect transistor and manufacturing method thereof Download PDFInfo
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- CN108010968B CN108010968B CN201711347871.0A CN201711347871A CN108010968B CN 108010968 B CN108010968 B CN 108010968B CN 201711347871 A CN201711347871 A CN 201711347871A CN 108010968 B CN108010968 B CN 108010968B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 238000002353 field-effect transistor method Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 46
- 230000005669 field effect Effects 0.000 claims abstract description 41
- 238000005530 etching Methods 0.000 claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims description 15
- 239000007772 electrode material Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000206 photolithography Methods 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims 1
- 150000002500 ions Chemical class 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
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- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a method for manufacturing a fin field effect transistor, which comprises the following steps: forming a source region and a drain region on the surface of the silicon substrate; forming an oxide layer on the surface of the silicon substrate, and carrying out planarization treatment on the oxide layer to expose the source region and the drain region; removing the oxide layer in the channel region between the source region and the drain region by etching the oxide layer in the channel region; forming an epitaxial layer on the surface of the oxide layer, and carrying out back etching treatment on the epitaxial layer, wherein the epitaxial layer is filled in the channel region; etching the oxide layers on two sides of the epitaxial layer of the channel region; forming a gate dielectric layer on the surface of the epitaxial layer of the channel region, wherein the gate dielectric layer covers the channel region of the source region and the drain region; and forming a grid on the surface of the grid dielectric layer. The invention also provides a fin type field effect transistor manufactured by the method.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of semiconductor chip manufacturing, in particular to a fin type field effect transistor and a manufacturing method thereof.
[ background of the invention ]
A fin field effect transistor (FinFET) is a field effect transistor having a fin channel structure. In a finfet, a Fin (Fin) is formed vertically on a silicon substrate surface and acts as a channel, with a gate overlying the Fin surface to control the channel.
In the manufacturing process flow of the fin field effect transistor, when a fin part is formed, the surface of a device becomes uneven; if the height of the fin portion is higher, the influence on subsequent manufacturing processes is larger, such as a photolithography process, the glue spreading effect and the exposure effect are deteriorated. However, for fin devices, the higher the fin, the greater the current carrying capacity of the finfet device itself. In view of the uneven problem existing in the fin field effect transistor process, the fin part cannot be too high; therefore, the manufacturing process of the fin height of the fin field effect transistor and the device performance are in contradiction.
Accordingly, there is a need for a fin field effect transistor and a method for fabricating the same to solve the above-mentioned problems of the prior art.
[ summary of the invention ]
One objective of the present invention is to provide a fin field effect transistor and a method for fabricating the same.
The invention provides a method for manufacturing a fin field effect transistor, which comprises the following steps: forming a source region and a drain region on the surface of the silicon substrate; forming an oxide layer on the surface of the silicon substrate, and carrying out planarization treatment on the oxide layer to expose the source region and the drain region; removing the oxide layer in the channel region between the source region and the drain region by etching the oxide layer in the channel region; forming an epitaxial layer on the surface of the oxide layer, and carrying out back etching treatment on the epitaxial layer, wherein the epitaxial layer is filled in the channel region; etching the oxide layers on two sides of the epitaxial layer of the channel region; forming a gate dielectric layer on the surface of the epitaxial layer of the channel region, wherein the gate dielectric layer covers the channel region of the source region and the drain region; and forming a grid on the surface of the grid dielectric layer.
As an improvement of the method for manufacturing the fin field effect transistor provided in the present invention, in a preferred embodiment, the forming a source region and a drain region on the surface of the silicon substrate includes: providing a silicon substrate, and carrying out doping treatment on a source region position and a drain region position of the silicon substrate to form a source region and a drain region; after doping is complete, the source and drain regions are etched out by a photolithography or etching process.
As an improvement of the method for manufacturing the fin field effect transistor provided in the present invention, in a preferred embodiment, the source region and the drain region are doped by ion implantation, and the ion doping amount is 1.015～9.016Per cm2The injection energy is 1 to 400 KEV.
As an improvement of the method for manufacturing the fin field effect transistor provided in the present invention, in a preferred embodiment, the oxide layer is a silicon dioxide layer, and the oxide layer is planarized by etching or chemical mechanical polishing.
As an improvement of the method for manufacturing the fin field effect transistor provided in the present invention, in a preferred embodiment, after the epitaxial layer is subjected to the etching back process, the epitaxial layer inside the channel region remains and is planarized with the surfaces of the source region and the drain region.
As an improvement of the method for manufacturing the fin field effect transistor provided by the present invention, in a preferred embodiment, after etching the oxide layers on both sides of the epitaxial layer of the channel region, gaps are respectively formed between both sides of the epitaxial layer of the channel region and the oxide layers, and the gaps expose the side surfaces of the epitaxial layer of the channel region.
As an improvement of the method for manufacturing the fin field effect transistor provided in the present invention, in a preferred embodiment, the gate dielectric layer is formed to cover the source region and the drain region, and cover the surface and the side surface of the epitaxial layer of the channel region, wherein the portion covering the side surface of the epitaxial layer is located in the gap between the epitaxial layer and the oxide layer.
As an improvement of the method for manufacturing the fin field effect transistor provided in the present invention, in a preferred embodiment, the step of forming the gate on the surface of the gate dielectric layer includes: growing a grid electrode material layer on the surface of the grid electrode dielectric layer, wherein the grid electrode material layer entirely covers the surface of the grid electrode material layer; after the gate material layer is formed, etching the gate material layer on the surface of the gate dielectric layer through a photolithography process, so that the gate material layer only covers the channel region and does not cover the body portions of the source region and the drain region.
As an improvement of the method for manufacturing the fin field effect transistor provided in the present invention, in a preferred embodiment, the gate material layer is a polysilicon layer or a metal material layer.
The fin field effect transistor is manufactured by the method for manufacturing the fin field effect transistor.
According to the fin type field effect transistor and the manufacturing method thereof, the fin part is etched firstly, then the surface of the fin part is covered with the oxide layer, and the channel region, the gate dielectric layer and the grid electrode material layer are formed in an embedding mode, so that the surface of the device always has good flatness in the whole process of implementing the whole process, photoetching and etching processes are facilitated, the fin part of the fin type field effect transistor can have higher height, the current circulation capacity of the fin type field effect transistor is improved, and the performance of the fin type field effect transistor is ensured.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
fig. 1 is a schematic flow chart illustrating a method of fabricating a finfet in accordance with an embodiment of the present invention;
fig. 2 to 11 are schematic diagrams illustrating process steps of the method for fabricating the finfet shown in fig. 1.
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to solve the contradiction between the fin height manufacturing process and the device performance of the fin field effect transistor in the prior art, the invention solves the influence of the fin height on the device surface planarization by optimizing the structure and the manufacturing process flow of the fin field effect transistor.
Specifically, according to the manufacturing method of the fin field effect transistor, the fin part is etched, the surface of the fin part is covered with the oxide layer, and the channel region, the gate dielectric layer and the gate material layer are formed in an embedded mode, so that the surface of the device always has good flatness in the whole process of implementing the whole process, photoetching and etching processes are facilitated, the fin part of the fin field effect transistor can have high height, the current circulation capacity of the fin field effect transistor is improved, and the performance of the fin field effect transistor is guaranteed.
Fig. 1 is a flow chart illustrating a method for fabricating a fin field effect transistor according to an embodiment of the present invention. The manufacturing method of the fin field effect transistor comprises the following steps:
step S1, forming a source region and a drain region on the surface of the silicon substrate;
specifically, referring to fig. 2, a silicon substrate is provided, and a source region position (S) and a drain region position (D) are defined on the surface of the silicon substrate; and then, doping the source region and the drain region by doping treatment, such as ion implantation, on the source region position and the drain region position. When the ion implantation treatment is adopted, the ions can adopt N-type impurities or P-type impurities, and the ion doping amount can be 1.015～9.016Per cm2The injection energy can be 1-400 KEV. Referring further to fig. 3(a) and 3(b), after doping is completed, the source and drain regions are etched out by photolithography or etching process, thereby forming a step-shaped source and drain region on the surface of the silicon substrate. The source region and the drain region may be doped regions of the silicon substrate, and each of the source region and the drain region includes a body portion and an extension portion facing each other; the width of the extension part is smaller than that of the main body parts of the source region and the drain region, and an opening is formed between the extension parts of the source region and the drain region and can be used as a channel region of the fin field effect transistor.
Step S2, forming an oxide layer on the surface of the silicon substrate, and carrying out planarization treatment on the oxide layer to expose the source region and the drain region;
specifically, referring to fig. 4(a) and 4(b), first, an oxide layer, such as silicon dioxide, may be grown on the surface of the silicon substrate by chemical vapor deposition, and the thickness of the oxide layer is required to be about the step height of the source region and the drain region, i.e., the oxide layer can completely cover the source region and the drain region. Next, referring to fig. 5(a) and 5(b), after the oxide layer is formed, the oxide layer is planarized by etching or Chemical Mechanical Polishing (CMP) to remove a portion of the oxide layer and expose the source and drain regions.
Step S3, removing the oxide layer in the channel region between the source region and the drain region by etching the oxide layer in the channel region; as shown in fig. 6(a) and 6(b), after the oxide layer of the channel region is removed, the channel region between the source region and the drain region is exposed.
Step S4, forming an epitaxial layer on the surface of the oxide layer, wherein the epitaxial layer is filled in the channel region;
specifically, in step S4, as shown in fig. 7(a) and 7(b), an epitaxial layer may be grown on the surface of the oxide layer by an epitaxial growth process, and the epitaxial layer covers the oxide layer and the source and drain regions; meanwhile, since the oxide layer of the channel region is removed in step S3, the channel region is also filled with the epitaxial layer during the epitaxial layer formation.
Step S5, carrying out back etching treatment on the epitaxial layer to enable the surfaces of the epitaxial layer of the channel region and the source region and the drain region to be smooth;
specifically, as shown in fig. 8(a) and 8(b), after the epitaxial layer is formed, in step S5, the epitaxial layer is further etched back by an etching back process to make the surface of the epitaxial layer of the channel region and the surface of the source and drain regions flat, that is, the epitaxial layer of the channel region is remained, and the epitaxial layer is etched back elsewhere.
Step S6, etching the oxide layers on two sides of the epitaxial layer of the channel region to form a gap between the epitaxial layer of the channel region and the oxide layers;
specifically, referring to fig. 9(a) and 9(c), in step S6, the oxide layers on both sides of the epitaxial layer of the channel region may be partially removed by a photolithography process to form gaps between both sides of the epitaxial layer of the channel region and the oxide layers, respectively, and the length of the gaps may be slightly greater than the length of the channel; after the gap is formed, the side surface of the epitaxial layer of the channel region is exposed so as to be covered by a gate dielectric layer which is manufactured subsequently.
Step S7, forming a gate dielectric layer on the surface of the epitaxial layer of the channel region, wherein the gate dielectric layer covers the surface and the side faces of the channel region of the source region and the drain region;
specifically, referring to fig. 10(a) and 10(c), in step S7, after the oxide layers on both sides of the epitaxial layer of the channel region are etched, a gate dielectric layer may be formed on the surface of the epitaxial layer, and the gate dielectric layer may specifically be silicon dioxide or another dielectric material. And after the gate dielectric layer is formed, the gate dielectric layer covers the source region and the drain region, and simultaneously covers the surface and the side surface of the epitaxial layer of the channel region, wherein the part covering the side surface of the epitaxial layer is positioned in a gap between the epitaxial layer and the oxide layer.
Step S8, forming a grid electrode on the surface of the grid dielectric layer;
specifically, referring to fig. 11(a) and 11(c), in step S8, a gate material layer is first grown on the surface of the gate dielectric layer, where the gate material layer may be a polysilicon layer or a metal material layer; the gate material layer covers the surface of the gate dielectric layer as a whole, namely covers the front surface of the gate dielectric layer and also fills a gap between the oxide layer and the side surface of the epitaxial layer covered with the gate dielectric layer. After the gate material layer is formed, etching the gate material layer on the surface of the gate dielectric layer through a photolithography process, so that the gate material layer only covers the channel region and does not cover the body portions of the source region and the drain region. And forming a grid electrode of the fin field effect transistor after the grid electrode material layer is etched.
Therefore, according to the manufacturing method of the fin field effect transistor, the fin part is etched firstly, then the surface of the fin part is covered with the oxide layer, and the channel region, the gate dielectric layer and the grid electrode material layer are formed in an embedded mode, so that the surface of the device always has good flatness in the whole process of implementing the whole process, the photoetching and etching processes are facilitated, the fin part of the fin field effect transistor can have higher height, the current circulation capacity of the fin field effect transistor device is improved, and the performance of the fin field effect transistor is ensured.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (8)
1. A method for manufacturing a fin field effect transistor is characterized by comprising the following steps:
forming a source region and a drain region on the surface of the silicon substrate;
forming an oxide layer on the surface of the silicon substrate, and carrying out planarization treatment on the oxide layer to expose the source region and the drain region;
removing the oxide layer in the channel region between the source region and the drain region by etching the oxide layer in the channel region;
forming an epitaxial layer on the surface of the oxide layer, and carrying out back etching treatment on the epitaxial layer, wherein the epitaxial layer is filled in the channel region;
etching the oxide layers on two sides of the epitaxial layer of the channel region;
forming a gate dielectric layer on the surface of the epitaxial layer of the channel region, wherein the gate dielectric layer covers the channel region of the source region and the drain region;
forming a grid electrode on the surface of the grid dielectric layer;
after the oxide layers on the two sides of the epitaxial layer of the channel region are etched, gaps are formed between the two sides of the epitaxial layer of the channel region and the oxide layers respectively, and the side faces of the epitaxial layer of the channel region are exposed due to the gaps; and after the gate dielectric layer is formed, covering the source region and the drain region, and simultaneously covering the surface and the side surface of the epitaxial layer of the channel region, wherein the part covering the side surface of the epitaxial layer is positioned in a gap between the epitaxial layer and the oxide layer.
2. The method of claim 1, wherein forming source and drain regions on the surface of the silicon substrate comprises:
providing a silicon substrate, and carrying out doping treatment on a source region position and a drain region position of the silicon substrate to form a source region and a drain region;
after doping is complete, the source and drain regions are etched out by a photolithography or etching process.
3. The method of claim 2, wherein the source and drain regions are doped by ion implantation with an ion dopant amount of 1.015～9.016Per cm2The injection energy is 1 to 400 KEV.
4. The method of claim 1, wherein the oxide layer is a silicon dioxide layer and the oxide layer is planarized by etching or chemical mechanical polishing.
5. The method of claim 1, wherein the epitaxial layer remains within the channel region after the epitaxial layer has been etched back and is planar to the surface of the source and drain regions.
6. The method of claim 1, wherein the step of forming the gate on the surface of the gate dielectric layer comprises:
growing a grid electrode material layer on the surface of the grid electrode dielectric layer, wherein the grid electrode material layer entirely covers the surface of the grid electrode material layer;
after the gate material layer is formed, etching the gate material layer on the surface of the gate dielectric layer through a photolithography process, so that the gate material layer only covers the channel region and does not cover the body portions of the source region and the drain region.
7. The method of claim 6, wherein the gate material layer is a polysilicon layer or a metal material layer.
8. A fin field effect transistor manufactured by the method of any one of claims 1 to 7.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104009086A (en) * | 2013-02-27 | 2014-08-27 | 瑞萨电子株式会社 | Semiconductor device having compressively strained channel region and method of making same |
| US9735257B2 (en) * | 2014-04-09 | 2017-08-15 | International Business Machines Corporation | finFET having highly doped source and drain regions |
| CN107068756A (en) * | 2015-11-30 | 2017-08-18 | 格罗方德半导体公司 | The replacement body FINFET of knot distribution is improved by grid autoregistration knot |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104009086A (en) * | 2013-02-27 | 2014-08-27 | 瑞萨电子株式会社 | Semiconductor device having compressively strained channel region and method of making same |
| US9735257B2 (en) * | 2014-04-09 | 2017-08-15 | International Business Machines Corporation | finFET having highly doped source and drain regions |
| CN107068756A (en) * | 2015-11-30 | 2017-08-18 | 格罗方德半导体公司 | The replacement body FINFET of knot distribution is improved by grid autoregistration knot |
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