CN108010968B - Fin type field effect transistor and manufacturing method thereof - Google Patents

Abstract

The present invention provides a method for manufacturing a fin field effect transistor, comprising: forming a source region and a drain region on the surface of a silicon substrate; forming an oxide layer on the surface of the silicon substrate, and performing a planarization treatment on the oxide layer , so that the source region and the drain region are exposed; by etching the oxide layer in the channel region between the source region and the drain region, the oxide layer in the channel region is removed; An epitaxial layer is formed on the surface of the oxide layer, and the epitaxial layer is etched back, wherein the epitaxial layer is filled into the channel region; and the oxide layers on both sides of the epitaxial layer in the channel region are etched forming a gate dielectric layer on the surface of the epitaxial layer of the channel region, the gate dielectric layer covering the source region and the drain region and the channel region; forming a gate on the surface of the gate dielectric layer. The present invention also provides a fin field effect transistor fabricated by the above method.

Description

Fin field effect transistor and method of making the same

【Technical field】

The present invention relates to the technical field of semiconductor chip manufacturing, and in particular, to a fin field effect transistor and a manufacturing method thereof.

【Background technique】

A fin field effect transistor (FinFET) is a field effect transistor with a fin channel structure. In a fin field effect transistor, a fin (Fin) is formed vertically on the surface of a silicon substrate, and the fin serves as a channel, and the gate controls the channel by covering the surface of the fin.

In the manufacturing process of fin field effect transistors, after the fins are formed, the surface of the device will become uneven; if the height of the fins is higher, it will have a greater impact on subsequent manufacturing processes, such as photolithography, glue coating The effect and exposure effect will be worse. But for a fin device, the higher the fin, the greater the current flow capability of the fin field effect transistor device itself. In view of the unevenness problem in the process of the fin field effect transistor, the fin cannot be made too high; therefore, there is a contradiction between the fabrication process of the fin height of the fin field effect transistor and the device performance.

In view of this, it is necessary to provide a fin field effect transistor and a fabrication method thereof to solve the above problems existing in the prior art.

[Content of the invention]

One of the objectives of the present invention is to provide a fin field effect transistor and a manufacturing method thereof to solve the above problems.

The manufacturing method of the fin field effect transistor provided by the present invention includes: forming a source region and a drain region on the surface of a silicon substrate; forming an oxide layer on the surface of the silicon substrate, and performing a planarization treatment on the oxide layer, so that The source region and the drain region are exposed; the oxide layer in the channel region is removed by etching the oxide layer in the channel region between the source region and the drain region; forming an epitaxial layer on the surface of the layer, and performing an etch back treatment on the epitaxial layer, wherein the epitaxial layer is filled into the channel region; performing etching treatment on the oxide layers on both sides of the epitaxial layer in the channel region; A gate dielectric layer is formed on the surface of the epitaxial layer of the channel region, the gate dielectric layer covers the source region and the drain region and the channel region; a gate is formed on the surface of the gate dielectric layer.

As an improvement of the method for fabricating the fin field effect transistor provided by the present invention, in a preferred embodiment, the forming the source region and the drain region on the surface of the silicon substrate includes: providing a silicon substrate, and The source and drain regions of the silicon substrate are doped to form the source and drain regions; after the doping is completed, the source and drain regions are etched out by photolithography or etching.

As an improvement of the manufacturing method of the fin field effect transistor provided by the present invention, in a preferred embodiment, the source region and the drain region are doped by ion implantation, and the ion doping dose is 1.0 ¹⁵ ~ 9.0 ¹⁶ /cm ² , and the injection energy is 1 to 400 KEV.

As an improvement of the manufacturing method of the fin field effect transistor provided by the present invention, in a preferred embodiment, the oxide layer is a silicon dioxide layer, and the oxide layer is performed by etching or chemical mechanical polishing Flattening.

As an improvement to the method for fabricating the fin field effect transistor provided by the present invention, in a preferred embodiment, after the epitaxial layer is etched back, the epitaxial layer inside the channel region remains and is connected with the epitaxial layer. Surfaces of the source and drain regions are flat.

As an improvement of the manufacturing method of the fin field effect transistor provided by the present invention, in a preferred embodiment, after etching the oxide layers on both sides of the epitaxial layer of the channel region, the A gap is respectively formed between two sides of the epitaxial layer of the channel region and the oxide layer, and the gap makes the side surfaces of the epitaxial layer of the channel region also exposed.

As an improvement to the method for fabricating a fin field effect transistor provided by the present invention, in a preferred embodiment, the gate dielectric layer covers the source region and the drain region and simultaneously covers the channel region after the formation of the gate dielectric layer. The surface and side of the epitaxial layer, wherein the part covering the side of the epitaxial layer is located in the gap between the epitaxial layer and the oxide layer.

As an improvement of the method for manufacturing a fin field effect transistor provided by the present invention, in a preferred embodiment, the step of forming a gate on the surface of the gate dielectric layer includes: growing on the surface of the gate dielectric layer a gate material layer, the gate material layer entirely covers the surface of the gate material layer; after the gate material layer is formed, the gate material layer on the surface of the gate dielectric layer is etched by a photolithography process etching process, so that the gate material layer only covers the channel region and does not cover the main body portions of the source and drain regions.

As an improvement of the manufacturing method of the fin field effect transistor provided by the present invention, in a preferred embodiment, the gate material layer is a polysilicon layer or a metal material layer.

The fin field effect transistor provided by the present invention is fabricated by using the above-mentioned fabrication method of the fin field effect transistor.

In the fin field effect transistor and the manufacturing method thereof provided by the present invention, the fins are first etched, and then an oxide layer is covered on the surface thereof, and then a channel region, a gate dielectric layer and a gate material layer are formed in a damascene manner, During the whole process, the surface of the device always has a good flatness, which is beneficial to the photolithography and etching process, so that the fin of the fin field effect transistor can have a higher height and improve the fin field effect. The current flow capacity of the transistor device ensures the performance of the fin field effect transistor.

【Description of drawings】

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, under the premise of no creative work, other drawings can also be obtained from these drawings, wherein:

FIG. 1 is a schematic flowchart of an embodiment of a method for fabricating a fin field effect transistor provided by the present invention;

2 to 11 are schematic diagrams of various process steps of the manufacturing method of the fin field effect transistor shown in FIG. 1 .

【Detailed ways】

The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In order to solve the contradiction between the fin height manufacturing process and device performance of the prior art fin field effect transistor, the present invention solves the problem of the flatness of the device surface due to the fin height by optimizing the structure and manufacturing process of the fin field effect transistor. Impact.

Specifically, in the method for manufacturing a fin field effect transistor provided by the present invention, the fins are first etched, and then an oxide layer is covered on the surface thereof, and then a channel region, a gate dielectric layer, and a gate material layer are formed in a damascene manner. During the whole process, the surface of the device always has a good flatness, which is beneficial to the photolithography and etching process, so that the fin of the fin field effect transistor can have a higher height and improve the fin field effect. The current flow capacity of the transistor device ensures the performance of the fin field effect transistor.

Please refer to FIG. 1 , which is a schematic flowchart of an embodiment of a method for fabricating a fin field effect transistor provided by the present invention. The manufacturing method of the fin field effect transistor includes the following steps:

Step S1, forming a source region and a drain region on the surface of the silicon substrate;

Specifically, referring to FIG. 2, a silicon substrate is provided first, and a source region position (S) and a drain region position (D) are defined on the surface of the silicon substrate; then, by comparing the source region position and the drain region position Doping treatment, such as ion implantation, is performed at the position of the region, so as to realize the doping of the source and drain regions. Wherein, when using ion implantation, the ions can be N-type impurities or P-type impurities, the ion doping dose can be 1.0 ¹⁵ ～9.0 ¹⁶ pieces/cm ² , and the implantation energy can be 1～400KEV. Please refer to FIGS. 3( a ) and 3 ( b ) further, after the doping is completed, the source region and the drain region are etched out by photolithography or etching process, thereby forming a step-shaped source region on the surface of the silicon substrate area and drain area. Wherein, the source region and the drain region may specifically be doped regions of the silicon substrate, and in addition to the main body portion, the source region and the drain region respectively have an extension portion facing each other; the width of the extension portion is smaller than the width of the extension portion. The main body parts of the source region and the drain region have an opening between the extension parts of the source region and the drain region, and the opening can be used as a channel region of the fin field effect transistor.

Step S2, forming an oxide layer on the surface of the silicon substrate, and performing a planarization process on the oxide layer, so that the source region and the drain region are exposed;

Specifically, please refer to FIGS. 4(a) and 4(b). First, an oxide layer, such as silicon dioxide, can be grown on the surface of the silicon substrate by chemical vapor deposition. The thickness of the oxide layer requires about The step heights of the source and drain regions, that is, the oxide layer can completely cover the source and drain regions. Next, referring to FIGS. 5(a) and 5(b), after the oxide layer is formed, the oxide layer is planarized by etching or chemical mechanical polishing (Chemical Mechanical Polishing, CMP), Thereby, part of the oxide layer is removed and the source and drain regions are exposed.

Step S3, removing the oxide layer in the channel region by etching the oxide layer in the channel region between the source region and the drain region; as shown in Figure 6(a) and Figure 6(b) ), after the oxide layer of the channel region is removed, the channel region between the source region and the drain region is exposed.

Step S4, an epitaxial layer is formed on the surface of the oxide layer, and the epitaxial layer is filled into the channel region;

Specifically, in step S4, as shown in FIG. 7(a) and FIG. 7(b), an epitaxial layer may be grown on the surface of the oxide layer by an epitaxial growth process, and the epitaxial layer covers the oxide layer and the source region and the drain region; at the same time, since the oxide layer of the channel region is removed in step S3, in the process of forming the epitaxial layer, the channel region is also covered by the epitaxial layer filling.

Step S5, performing an etchback process on the epitaxial layer, so that the epitaxial layer of the channel region and the surfaces of the source region and the drain region are flat;

Specifically, as shown in FIG. 8( a ) and FIG. 8( b ), after the epitaxial layer is formed, in step S5 , the epitaxial layer needs to be etched back through an etchback process, so that all the The surface of the epitaxial layer of the channel region and the source region and the drain region are flat, that is, the epitaxial layer of the channel region is retained, and the epitaxial layers in other places are etched back.

Step S6, etching the oxide layers on both sides of the epitaxial layer of the channel region, so that a gap is formed between the epitaxial layer of the channel region and the oxide layer;

Specifically, please refer to FIG. 9( a ) and FIG. 9( c ), in step S6 , the oxide layers on both sides of the epitaxial layer of the channel region may be partially removed by a photolithography process, so as to remove the oxide layers on both sides of the epitaxial layer in the channel region. A gap is formed between the two sides of the epitaxial layer of the channel region and the oxide layer, and the length of the gap may be slightly larger than the length of the channel; after the gap is formed, the side surfaces of the epitaxial layer of the channel region are formed. It is also exposed to be covered by the gate dielectric layer produced later.

Step S7, forming a gate dielectric layer on the surface of the epitaxial layer of the channel region, the gate dielectric layer covering the surface and side surfaces of the channel region of the source region and the drain region;

Specifically, please refer to FIG. 10(a) and FIG. 10(c), in step S7, after the oxide layers on both sides of the epitaxial layer of the channel region are etched, a surface of the epitaxial layer can be fabricated on the surface of the epitaxial layer. The gate dielectric layer, the gate dielectric layer may specifically use silicon dioxide or other dielectric materials. And, after the gate dielectric layer is formed, it covers the source region and the drain region, and simultaneously covers the surface and side surface of the epitaxial layer of the channel region, wherein the part covering the side surface of the epitaxial layer is located in the epitaxial layer and the oxide layer. gap between layers.

Step S8, forming a gate on the surface of the gate dielectric layer;

Specifically, please refer to FIG. 11(a) and FIG. 11(c), in step S8, a gate material layer is first grown on the surface of the gate dielectric layer, and the gate material layer may be a polysilicon layer or a metal material The gate material layer entirely covers the surface of the gate dielectric layer, that is, it not only covers the front surface of the gate dielectric layer, but also fills the oxide layer and the epitaxial layer covered with the gate dielectric layer at the same time. The gap between the sides of the layer. After the gate material layer is formed, the gate material layer on the surface of the gate dielectric layer is etched through a photolithography process, so that the gate material layer only covers the channel region but not the channel region body portions of the source and drain regions. After the gate material layer is etched, the gate of the fin field effect transistor can be formed.

It can be seen that the method for manufacturing the fin field effect transistor of the present invention is to first etch the fin, then cover the surface with an oxide layer, and then use a damascene method to form a channel region, a gate dielectric layer, and a gate material layer. , so that the surface of the device always has a good flatness during the whole process, which is conducive to the lithography and etching process, so that the fin of the fin field effect transistor can have a higher height and improve the fin field. The current flow capability of the effect transistor device ensures the performance of the fin field effect transistor.

The above are only the embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, improvements can be made without departing from the inventive concept of the present invention, but these belong to the present invention. scope of protection.

Claims (8)

1. A method for manufacturing a fin field effect transistor is characterized by comprising the following steps:

forming a source region and a drain region on the surface of the silicon substrate;

forming an oxide layer on the surface of the silicon substrate, and carrying out planarization treatment on the oxide layer to expose the source region and the drain region;

removing the oxide layer in the channel region between the source region and the drain region by etching the oxide layer in the channel region;

forming an epitaxial layer on the surface of the oxide layer, and carrying out back etching treatment on the epitaxial layer, wherein the epitaxial layer is filled in the channel region;

etching the oxide layers on two sides of the epitaxial layer of the channel region;

forming a gate dielectric layer on the surface of the epitaxial layer of the channel region, wherein the gate dielectric layer covers the channel region of the source region and the drain region;

forming a grid electrode on the surface of the grid dielectric layer;

after the oxide layers on the two sides of the epitaxial layer of the channel region are etched, gaps are formed between the two sides of the epitaxial layer of the channel region and the oxide layers respectively, and the side faces of the epitaxial layer of the channel region are exposed due to the gaps; and after the gate dielectric layer is formed, covering the source region and the drain region, and simultaneously covering the surface and the side surface of the epitaxial layer of the channel region, wherein the part covering the side surface of the epitaxial layer is positioned in a gap between the epitaxial layer and the oxide layer.

2. The method of claim 1, wherein forming source and drain regions on the surface of the silicon substrate comprises:

providing a silicon substrate, and carrying out doping treatment on a source region position and a drain region position of the silicon substrate to form a source region and a drain region;

after doping is complete, the source and drain regions are etched out by a photolithography or etching process.

3. The method of claim 2, wherein the source and drain regions are doped by ion implantation with an ion dopant amount of 1.0¹⁵～9.0¹⁶Per cm²The injection energy is 1 to 400 KEV.

4. The method of claim 1, wherein the oxide layer is a silicon dioxide layer and the oxide layer is planarized by etching or chemical mechanical polishing.

5. The method of claim 1, wherein the epitaxial layer remains within the channel region after the epitaxial layer has been etched back and is planar to the surface of the source and drain regions.

6. The method of claim 1, wherein the step of forming the gate on the surface of the gate dielectric layer comprises:

growing a grid electrode material layer on the surface of the grid electrode dielectric layer, wherein the grid electrode material layer entirely covers the surface of the grid electrode material layer;

after the gate material layer is formed, etching the gate material layer on the surface of the gate dielectric layer through a photolithography process, so that the gate material layer only covers the channel region and does not cover the body portions of the source region and the drain region.

7. The method of claim 6, wherein the gate material layer is a polysilicon layer or a metal material layer.

8. A fin field effect transistor manufactured by the method of any one of claims 1 to 7.

Images