CN108511344B - Vertical nanowire transistor and manufacturing method thereof - Google Patents
Vertical nanowire transistor and manufacturing method thereof Download PDFInfo
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Abstract
The application provides a vertical nanowire transistor and a manufacturing method thereof. The manufacturing method comprises the following steps: step S1, providing a substrate comprising a substrate and a plurality of spaced nanowires located on the substrate, each nanowire comprising sub-nanowires, each sub-nanowire comprising a first end portion, a middle portion, and a second end portion; step S2, forming a gate dielectric layer and a gate; step S3, forming an interlayer dielectric layer on the surface of the substrate; step S4, forming a first contact hole and a second contact hole which are isolated from each other in the interlayer dielectric layer, wherein the first contact hole is connected with the side surface of the first end part, and the second contact hole is connected with the side surface of the second end part; and step S5, filling heavily doped materials in the first contact hole and/or the second contact hole, carrying out high-temperature annealing diffusion, and carrying out transverse doping to form a drain region and/or a source region. In the manufacturing method, a transverse diffusion method is adopted to form a uniformly doped source region and/or drain region, so that the doping process of the source region and the drain region of the vertical nanowire transistor is simple and easy to control.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a vertical nanowire transistor and a method for fabricating the same.
Background
The scaling of CMOS integrated circuits continues to progress, and the device structure is from a two-dimensional planar structure (2D planar) to a three-dimensional Fin Field Effect transistor (3D Field Effect transistor, 3D Field FET for short) to a three-dimensional horizontal structure ring-Gate Nanowire Field Effect transistor (3D Gate-All-Around Nanowire Field Effect transistor (3D Gate NW FET for short), and in the future, to a three-dimensional Vertical structure ring-Gate Nanowire Field Effect transistor (3D Vertical Gate-All-Around Nanowire Field Effect transistor, 3D Vertical NW or Vertical Nanowire transistor for short) for higher integration. The vertical nanowire transistor can better inhibit short-channel effect, the cylindrical ring-gate structure has the best gate control capability, the corner effect is inhibited, and the gate electrode can better form electrostatic control on a channel region from multiple directions.
Methods of fabricating 3D Vertical NW FETs include two main categories: the CMOS process is compatible with the traditional CMOS process from top to bottom. The former is that process control problems are difficult to integrate on a large scale due to process defects. The compatible traditional CMOS technology mainly comprises the following steps: vertical etching, selective etching, epitaxial growth, polysilicon deposition and the like.
The 3D Vertical NW FET can also adopt a mode of growing a multilayer SiGe/Si lamination and etching to form a Vertical nanowire, and then selectively etching SiGe or Si to manufacture a gate electrode. The method needs a complex multi-layer epitaxial process, and the channel quality and the interface quality are difficult to guarantee.
In the above method for manufacturing the 3D Vertical NW FET, many challenges are faced by the source and drain region doping and metal contact technology, mainly including two problems of complicated process and excessively large contact area.
Disclosure of Invention
The present disclosure is directed to a vertical nanowire transistor and a method for fabricating the same, so as to solve the problem of complex doping process of a source/drain region in the prior art.
In order to achieve the above object, according to one aspect of the present application, there is provided a method of fabricating a vertical nanowire transistor, the method comprising: step S1, providing a substrate, where the substrate includes a substrate and a plurality of spaced nanowires located on the substrate, each of the nanowires includes at least one sub-nanowire sequentially connected from bottom to top, each of the sub-nanowires includes a first end portion, a middle portion, and a second end portion, and the sub-nanowires connected to the substrate are connected to the substrate through the first end portions; step S2, forming a gate dielectric layer on the outer surface of the nanowire, and forming a gate on the outer surface of the gate dielectric layer corresponding to the middle portion; step S3, forming an interlayer dielectric layer on the exposed surface of the substrate; step S4, etching and removing a portion of the interlayer dielectric layer and a portion of the gate dielectric layer, forming a first contact hole and a second contact hole in the interlayer dielectric layer, the first contact hole being connected to a side surface of the first end portion, the second contact hole being connected to a side surface of the second end portion; step S5, filling a heavily doped material in the first contact hole and/or the second contact hole, and annealing, wherein the heavily doped material is laterally diffused to selectively form a drain region and/or a source region at the first end portion and/or the second end portion.
Furthermore, the doping concentration of the heavily doped material is more than 1.0 multiplied by 1019/cm3。
Further, the step S2 includes: forming the gate dielectric layer on the exposed surface of the substrate and the exposed surface of the nanowire; depositing a gate material on the exposed surface of the gate dielectric layer; and removing part of the gate material, and forming the gate by the rest gate material.
Further, the outer surface of the sidewall of the gate electrode, the outer surface of the sidewall of the gate dielectric layer on the first end portion, and the outer surface of the sidewall of the gate dielectric layer on the second end portion are on the same plane.
Further, the step S3 includes: depositing an interlayer dielectric material on the exposed surfaces of the gate dielectric layer and the gate electrode; and flattening the interlayer dielectric material to form the interlayer dielectric layer, wherein the surface of the interlayer dielectric layer, which is far away from the substrate, covers the gate dielectric layer on the surface of the second end part.
Further, the width of the first contact hole and/or the second contact hole is larger at an end close to the substrate than at an end far from the substrate.
Further, the first contact hole includes a first base portion and a first connection portion connected to the first base portion, the first connection portion being connected to the first end portion, and a width of the first connection portion being greater than a width of the first base portion; the second contact hole includes a second base portion and a second connection portion connected to the second base portion, the second connection portion is connected to the second end portion, and a width of the second connection portion is larger than a width of the second base portion; preferably, both ends of the first connecting portion are connected to the adjacent two first end portions, respectively; further preferably, the first connecting portion has a height smaller than a height of the first end portion, and the second connecting portion has a height smaller than a height of the second end portion.
Further, after the step S5, the manufacturing method further includes: step S6, etching to remove the heavily doped material in the first contact hole and/or the second contact hole; step S7, filling metal in the first contact hole and/or the second contact hole to form a source contact and a drain contact, etching to remove a portion of the interlayer dielectric layer between adjacent nanowires to form a third contact hole, wherein the third contact hole is connected to the gate, and filling metal in the third contact hole to form a gate contact; preferably, the width of the third contact hole is larger at an end close to the substrate than at an end far from the substrate; more preferably, the third contact hole includes a third base portion and a third connecting portion connected to the third base portion, the third connecting portion is connected to the intermediate portion, a width of the third connecting portion is larger than a width of the third base portion, and a height of the third connecting portion is smaller than a height of the intermediate portion.
Further, the third contact hole is located between two adjacent nanowires, and two ends of the third connection portion are respectively connected to two adjacent gates.
Further, the heavily doped material includes a base material and a dopant impurity, the dopant impurity includes at least one of B, P and As, and the base material includes at least one of polysilicon, amorphous silicon, oxide, nitride, amorphous carbon, and organic matter.
According to another aspect of the present application, there is provided a vertical nanowire transistor including: a substrate; a plurality of spaced nanowires located on the surface of the substrate, each nanowire including at least one sub-nanowire connected in sequence from bottom to top, each sub-nanowire including a drain region, an intermediate portion and a source region connected in sequence, the intermediate portion being a conductive channel; the gate dielectric layer is positioned on the outer surface of the nanowire; the grid electrode is positioned on the outer surface of the grid dielectric layer corresponding to the middle part; an interlayer dielectric layer on a surface of the substrate, the interlayer dielectric layer having a first contact hole, a second contact hole and a third contact hole isolated from each other, the first contact hole being connected to one of the source region and the drain region, the second contact hole being connected to the other of the source region and the drain region, the third contact hole being connected to the gate electrode; and a metal contact including a source contact, a drain contact, and a gate contact, one of the drain contact and the source contact being located in the first contact hole, the other being located in the second contact hole, and the gate contact being located in the third contact hole.
Further, the width of the source region and the width of the drain region are both larger than the width of the intermediate portion, and the width of the source region and the width of the drain region are preferably the same.
According to the technical scheme, in the manufacturing method, a first contact hole and a second contact hole are formed firstly, then heavily doped materials are filled, high-temperature annealing is carried out, after the high-temperature annealing, doped impurities in the heavily doped materials in the first contact hole are diffused into the first end portion from the side face of the first end portion, and/or doped impurities in the heavily doped materials in the second contact hole are diffused into the second end portion from the side face of the second end portion, so that one of the first end portion and the second end portion forms a source region, and/or the other one forms a drain region, and the middle portion is used as a conducting channel. In the manufacturing method, a transverse diffusion method is adopted to form a uniformly doped source region and/or drain region, so that the doping process of the source region and the drain region of the vertical nanowire transistor is simpler and easy to control, and the injection damage can be well avoided.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
fig. 1 through 15 show structural schematic diagrams of a fabrication process of an embodiment of a vertical nanowire transistor according to the present application.
Wherein the figures include the following reference numerals:
10. a substrate; 11. pre-substrate; 12. pre-nanowire; 110. a substrate; 120. a nanowire; 012. a sub-nanowire; 121. a first end portion; 122. an intermediate portion; 123. a second end portion; 13. a drain region; 14. a source region; 20. a gate dielectric layer; 30. a gate electrode; 300. a gate material; 40. an interlayer dielectric layer; 41. a first contact hole; 411. a first base part; 412. a first connection portion; 42. a second contact hole; 421. a second base part; 422. a second connecting portion; 43. a third contact hole; 431. a third base part; 432. a third connecting portion; 50. a source contact; 60. a drain contact; 70. a gate contact; 80. the material is heavily doped.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the description and claims that follow, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "electrically connected" to the other element through a third element.
As described in the background art, the doping process of the source and drain regions of the vertical nanowire transistor in the prior art is complex, and in order to solve the above technical problems, the present application provides a vertical nanowire transistor and a method for manufacturing the same.
In an exemplary embodiment of the present application, there is provided a method for fabricating a vertical nanowire transistor, the method comprising:
step S1, providing a substrate 10, where the substrate 10 includes a substrate 110 and a plurality of spaced nanowires 120 located on the substrate 110, each nanowire 120 includes at least one sub-nanowire 012 connected in sequence from bottom to top, each sub-nanowire 012 includes a first end portion 121, a middle portion 122, and a second end portion 123 connected in sequence, where the sub-nanowire 012 connected to the substrate 110 is connected to the substrate 110 through the first end portion 121, as shown in fig. 3, in which the nanowire includes only one sub-nanowire;
step S2, forming a gate dielectric layer 20 on the outer surface of the nanowire 120 to form the structure shown in fig. 4, and forming the gate 30 on the surface of the gate dielectric layer 20 corresponding to the middle portion 122 to form the structure shown in fig. 6;
step S3, forming an interlayer dielectric layer 40 on the exposed surface of the substrate 110 to form the structure shown in fig. 7;
step S4, etching and removing a portion of the interlayer dielectric layer 40 and a portion of the gate dielectric layer 20, and forming a first contact hole 41 and a second contact hole 42 isolated from each other in the interlayer dielectric layer 40, as shown in fig. 8 and 9, since the first contact hole 41 and the second contact hole 42 are isolated from each other, in a cross-sectional view, the first contact hole 41 and the second contact hole 42 cannot be simultaneously shown, so that only the first contact hole 41 is shown in fig. 8, only the second contact hole 42 is shown in a cross-sectional view 9, the first contact hole 41 is connected to a side surface of the first end portion 121, and the second contact hole 42 is connected to a side surface of the second end portion 123;
step S5, filling a heavily doped material 80 in the first contact hole 41 and/or the second contact hole 42, and annealing to laterally and selectively diffuse the doped ions therein into the source region and/or the drain region, so that one of the first end portion 121 and/or the second end portion 123 forms the drain region 13 and/or the source region 14, as shown in fig. 10.
In step S5 of the method, one of the first contact hole 41 and the second contact hole 42 may be filled with a heavily doped material 80 and annealed to form one of a source region and a drain region, or both of the first contact hole 41 and the second contact hole 42 may be filled with a heavily doped material 80 and annealed to form a source region and a drain region. Those skilled in the art can fill the heavily doped material into both contact holes or only one contact hole according to actual conditions. When one of the source region and the drain region is formed by filling a metal into one of the contact holes and annealing, the other of the source region and the drain region may be formed by other methods in the prior art, and the specific forming step may be performed before step S5 or after step S5.
In the present application, the first end portion 121 and the second end portion 123 in the "first contact hole 41 is connected to the side surface of the first end portion 121, and the second contact hole 42 is connected to the side surface of the second end portion 123" may be the same first end portion 121 and the second end portion 123 of the sub-nanowire, or may be the first end portion 121 and the second end portion 123 of different sub-nanowires. Specifically, when only one sub-nanowire is included in the nanowire of the device, the first end portion 121 and the second end portion 123 refer to the first end portion 121 and the second end portion 123 of the same sub-nanowire; when the nanowire includes a plurality of sub-nanowires, the first end portion 121 and the second end portion 123 are the first end portion 121 and the second end portion 123 of different sub-nanowires, and two sub-nanowires are taken as an example, and the two sub-nanowires sequentially include a first sub-nanowire and a second sub-nanowire along a direction away from the substrate, wherein the first contact hole contacts one of the drain region of the first sub-nanowire and the source region of the second sub-nanowire, and the second contact hole contacts the other of the drain region of the first sub-nanowire and the source region of the second sub-nanowire.
The etching in step S4 and the subsequent step S6 may be any feasible etching method in the prior art, and may be dry etching, wet etching, specifically RIE etching, ICP etching, or the like, or may be a combination of multiple etching methods to complete one etching step. Those skilled in the art can select an appropriate etching method to complete step S4 and the subsequent step S6 according to practical situations.
In the method for manufacturing the vertical nanowire, the first contact hole and the second contact hole are formed firstly, then the heavily doped material is filled, then high-temperature annealing is carried out, and after the high-temperature annealing, the doping impurities in the heavily doped material in the first contact hole are transversely diffused into the first end part from the side surface of the first end part, and/or the doping impurities in the heavily doped material in the second contact hole are transversely diffused into the second end part from the side surface of the second end part, so that one of the first end part and the second end part forms a source region, and/or the other one forms a drain region, and the middle part is used as a conducting channel. In the manufacturing method, a transverse diffusion method is adopted to form a source region and/or a drain region in the vertical nanowires of different layers or regions, so that the doping process of the source region and the drain region of the vertical nanowire transistor is simpler and easier to control.
In order to further ensure that a source region and/or a drain region with better performance is formed, in an embodiment of the present application, the doping concentration of the heavily doped material 80 is greater than 1.0 × 1019/cm3。
The sub-nanowires in the present application may be concave-convex sub-nanowires, that is, the width of the sub-nanowires is not uniform, and as shown in fig. 3, the width of the first end portion 121 and the width of the second end portion 123 are both larger than the width of the middle portion 122; the sub-nanowires may also have uniform width, i.e., the first end portion, the second end portion, and the middle portion have the same width.
It should be noted that the term "width" as used herein refers to the width in the lateral direction parallel to the plane of the paper or the computer screen.
In an embodiment of the present application, as shown in fig. 3, when the sub-nanowire is a concave-convex sub-nanowire, the width of the first end portion 121 is the same as the width of the second end portion 123, which is more convenient for manufacturing the device.
As shown in fig. 3, the intermediate portion has a smaller width, so that the two side walls have a groove, which may be C-shaped, D-shaped, half-i-shaped, trapezoidal, triangular or sigma-shaped. Those skilled in the art can select the groove with a suitable shape according to actual conditions.
In a specific embodiment of the present application, the step S1 includes: step S11, providing the substrate 10, as shown in fig. 1; step S12, etching and removing a portion of the base 10 to obtain a substrate 110 and a plurality of spaced nanowires 120 on the surface of the substrate 110, as shown in fig. 3.
It should be noted that, before the etching in step S12, a planar pattern of the subsequent nanowire vertical structure needs to be defined by photolithography or a method of transferring a hard mask pattern, where the planar pattern may be a circle, a square, a rectangle, an ellipse, etc. and has a size between 1 nm and 100 nm, and the specific method is not limited to the above method.
More specifically, the step S12 may further include: step S121, etching and removing a part of the base 10 to form a pre-substrate 11 and a plurality of spaced pre-nanowires 12 on the surface of the pre-substrate 11, as shown in fig. 2; step S122, etching to remove a part of the pre-substrate 11, forming the nanowire 120 from the pre-nanowire and a part of the pre-substrate connected to the pre-nanowire, as shown in fig. 3, forming the substrate 110 from the remaining pre-substrate.
In order to avoid damage to the pre-nanowire during the etching of the pre-substrate, in an embodiment of the present application, which is not shown in the drawing, between the step S121 and the step S122, the step S2 further includes: a protective layer is formed on the exposed surface of the pre-nanowire 12, and the material of the protective layer includes at least one of chloride, carbide, oxide and nitride.
In order to obtain an ultra-thin protective layer, in one embodiment of the present application, after the protective layer is formed, the protective layer is further subjected to a plasma surface treatment. Specifically, the surface may be treated with O ions or N plasma to form an ultra-thin oxide layer or nitride layer as a protective layer.
For a device comprising a plurality of sub-nanowires, step S1 further comprises: after the first nanowire is formed, the nanowire is protected, the substrate is etched to form a second sub-nanowire, and the sub-nanowire formed in the previous step is protected before the subsequent sub-nanowire is etched and formed. Specifically, a protective layer may be formed on the surface of the sub-nanowire, and specific materials of the protective layer and the like may be referred to as the above protective layer, which is not described herein again.
Specifically, the method for forming a plurality of sub-nanowires by etching includes a BOSCH method. The principle of the BOSCH process is to circulate a passivating gas such as C in the reaction chamber4F8With an etching gas SF6Reacting with the sample, wherein the whole process is repeated and alternated with the steps of depositing the passivation layer and etching. Wherein, a protective gas C4F8Decomposing the carbon fluorine polymer under the action of high-density plasma to form a protective layer, and depositing the protective layer on the surface of the sample with the pattern.
In an embodiment of the application, the step S121 sequentially includes: the pre-substrate 11 is etched by anisotropic etching, isotropic etching and anisotropic etching to form the structure shown in fig. 3.
Of course, the forming process of the nanowire and the substrate in the present application is not limited to the above method, and those skilled in the art can select an appropriate forming method to form the nanowire and the substrate according to actual situations.
In a specific embodiment, in two adjacent sub-nanowires 012 of one nanowire, a second end 123 of the sub-nanowire 012 close to the substrate 110 is a first end 121 of the sub-nanowire 012 far away from the substrate 110. This can simplify the fabrication process of the device and reduce the fabrication cost of the device.
For the nanowire including a plurality of sub-nanowires, the forming process of the source region and the drain region of the nanowire is similar to that of the nanowire including only one sub-nanowire, the shape of the contact hole can be specifically adjusted, the source region and the drain region of the plurality of sub-nanowires are simultaneously formed by diffusion of the heavily doped material, the source region and the drain region of the plurality of sub-nanowires can also be formed by diffusion step by step, and a person skilled in the art can select a suitable method according to the actual situation, which is not described herein again. In another embodiment of the present application, the step S2 includes: forming the gate dielectric layer 20 on the exposed surface of the substrate 110 and the exposed surface of the nanowire 120, as shown in fig. 4; depositing a gate material 300 on the exposed surface of the gate dielectric layer 20 to form the structure shown in fig. 5; a portion of the gate material 300 is removed and the gate material 300 remains to form the gate electrode 30 shown in fig. 5.
The gate dielectric layer of the present application may be formed by using conventional materials in the prior art, such as silicon dioxide, silicon oxynitride and/or high-k material, and those skilled in the art can select a suitable material according to the actual situation.
In order to make the gate dielectric layer have a higher dielectric constant, and further better isolate the gate from the conductive channel and reduce the amount of leakage, in an embodiment of the present application, the material of the gate dielectric layer includes a high-K material, and the high-K material is selected from HfO2、HfSiO、HfSiON、HfTiO、HfZrO、Al2O3、La2O3、ZrO2And LaAlO.
The gate 30 of the present application is a metal gate or a polysilicon gate, and those skilled in the art can select an appropriate material to form the gate 30 of the present application according to actual situations.
When the gate dielectric layer is a High-K dielectric layer and the gate electrode is a metal gate electrode, in step S2, a HKMG (High K insulating layer + metal gate electrode) process may be used to form the gate dielectric layer and the gate material on the substrate.
The process of removing the gate material 300 may adopt an etching method, and specifically, may be an isotropic etching.
As shown in fig. 6, in order to simplify the etching process, thereby simplifying the manufacturing process and improving the manufacturing efficiency, the outer surface of the sidewall of the gate electrode 30, the outer surface of the sidewall of the gate dielectric layer 20 on the first end portion 121, and the outer surface of the sidewall of the gate dielectric layer 20 on the second end portion 123 are on the same plane.
In order to further ensure that the manufactured device has good flatness and thus good performance, in an embodiment of the present application, the step S3 includes: depositing an interlayer dielectric material on the exposed surfaces of the gate dielectric layer 20 and the gate electrode 30; and planarizing the interlayer dielectric material to form an interlayer dielectric layer 40, as shown in fig. 7, wherein the surface of the interlayer dielectric layer 40 away from the substrate 110 covers the gate dielectric layer 20 on the surface of the second end 123.
In order to further ensure that the doping ions in the heavily doped material can be diffused to the first end portion and the second end portion, to form the source region and the drain region with predetermined doping concentrations, and at the same time, to ensure that the finally formed metal contact can form a good ohmic contact with the corresponding structure, in an embodiment of the present application, as shown in fig. 8 and 9, the width of the first contact hole 41 and/or the second contact hole 42 is larger at the end close to the substrate 110 than at the end far from the substrate 110.
In a specific embodiment, as shown in fig. 8, the first contact hole 41 includes a first base portion 411 and a first connecting portion 412 connected to the first base portion 411, the first connecting portion 412 is connected to the first end portion 121, and a width of the first connecting portion 412 is greater than a width of the first base portion 411; as shown in fig. 9, the second contact hole 42 includes a second base portion 421 and a second connection portion 422 connected to the second base portion 421, the second connection portion 422 is connected to the second end portion 123, and a width of the second connection portion 422 is greater than a width of the second base portion 421.
In order to further improve the integration of the vertical nanowires, simplify the process and improve the manufacturing efficiency, in an embodiment of the present invention, as shown in fig. 8, two ends of the first connection portion 412 are respectively connected to two adjacent first end portions 121, so that, as shown in fig. 12, the contact metal filled in the first contact hole forms a corresponding ohmic contact with both adjacent nanowires.
In another embodiment of the present invention, as shown in fig. 8, the height of the first connecting portion 412 is smaller than the height of the first end portion 121, and as shown in fig. 9, the height of the second connecting portion 422 is smaller than the height of the second end portion 123. Therefore, doped ions can be better prevented from diffusing into other regions, ohmic contact between contact metal arranged subsequently and other regions can be further avoided, and the vertical nanowire transistor is guaranteed to have better performance.
In a specific embodiment of the present application, the manufacturing method further includes:
step S6, etching to remove the heavily doped material 80 in the first contact hole 41 and/or the second contact hole 42, as shown in fig. 11;
step S7, filling metal in the first contact hole 41 and/or the second contact hole 42 to form a source contact 50 and a drain contact 60, as shown in fig. 13 and 12, respectively, etching away a portion of the interlayer dielectric layer 40 between adjacent nanowires 120 to form a third contact hole 43, as shown in fig. 14, where the third contact hole 43 is located on a third side of the nanowire 120, the first side is opposite to the third side and adjacent to the second side, the third contact hole 43 is connected to the gate 30, and filling metal in the third contact hole 43 to form a gate contact 70, as shown in fig. 15.
It should be noted that, in the step S7, the sequence of the process of "forming source contact and drain contact by filling metal in the first contact hole 41 and the second contact hole 42" and the process of "forming the third contact hole" is not fixed, and the third contact hole may be formed first, and then the first contact hole 41, the second contact hole 42, and the third contact hole 43 are filled with metal at the same time to form corresponding metal contacts; alternatively, the first contact hole 41 and the second contact hole 42 may be filled with metal to form a source contact and a drain contact, then the third contact hole is formed, and finally the third contact hole 43 is filled with metal to form a gate contact.
It should be noted that, when the heavily doped material itself is a metal, the heavily doped material may not be removed in the manufacturing method of the present application, and may be directly used as a contact metal.
In order to ensure that the finally formed metal contact can form a good ohmic contact with the gate, in an embodiment of the present application, the width of the third contact hole 43 is larger at an end close to the substrate 110 than at an end far from the substrate 110.
In another embodiment of the present invention, as shown in fig. 14, the third contact hole 43 includes a third base portion 431 and a third connecting portion 432 connected to the third base portion 431, the third connecting portion 432 is connected to the intermediate portion 122, and a width of the third connecting portion 432 is greater than a width of the third base portion 431. This can better ensure that the gate forms a good ohmic contact with the metal.
In order to further improve the integration of the vertical nanowires, simplify the process and improve the manufacturing efficiency, in an embodiment of the present invention, as shown in fig. 14, the third contact hole 43 is located between two adjacent nanowires 120, and two ends of the third connection portion 432 are respectively connected to two adjacent gates 30, so that, as shown in fig. 15, the contact metal filled in the third contact hole forms a corresponding ohmic contact with both adjacent nanowires.
The heavily doped material in the present application comprises a base material and a doping impurity, the doping impurity comprises at least one of B, P and As, and the base material comprises at least one of polysilicon, amorphous silicon, oxide, nitride, amorphous carbon and organic matter. The skilled person can select suitable doping impurities and matrix materials according to the actual situation. For example, some low-k materials and some metal oxides are selected.
In order to remove the heavily doped material layer in a simpler manner while avoiding removing more interlayer dielectric layers, in an embodiment of the present application, the etching selectivity ratio of the material of the heavily doped material 80 to the material of the interlayer dielectric layer 40 is greater than 8.
In order to further ensure the isolation effect of the interlayer dielectric layer, in an embodiment of the present application, the material of the interlayer dielectric layer is selected from SiO2And/or Si3N4。
The substrate 10 may be any substrate made of any material available in the art, and may be a Si substrate, a Ge substrate, a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, a zinc oxide substrate, diamond, an aluminum nitride substrate, a metal or metalloid substrate, etc., and those skilled in the art may select a substrate of a suitable material according to actual circumstances.
In order to simplify the process and improve the performance of the device, in an embodiment of the present application, the substrate 10 is a silicon substrate.
In an embodiment of the present application, after the source contact, the drain contact, and the gate contact are formed, the manufacturing method further includes a step of forming a multi-layer interconnection, and the step may adopt a conventional process, which is not described herein again.
In another exemplary embodiment of the present application, a vertical nanowire transistor is provided, and the vertical nanowire transistor is manufactured by using any one of the above manufacturing methods. As shown in fig. 15, the vertical nanowire transistor comprises a substrate 110, a plurality of spaced nanowires having a source region 14, a drain region 13, and a middle portion 122, a gate dielectric layer 20, a gate electrode 30, an interlayer dielectric layer 40, a source contact 50, a drain contact 60, and a gate contact 70.
In a specific embodiment, the vertical nanowire transistor is manufactured by any one of the above manufacturing methods.
Specifically, the nanowires 120 are located on the surface of the substrate 110, each of the nanowires 120 includes at least one sub-nanowire 012 connected in sequence from bottom to top, each of the sub-nanowires 012 includes a drain region 13, an intermediate portion 122 and a source region 14 connected in sequence, and the intermediate portion 122 is a conductive channel; a gate dielectric layer 20 on the exposed surface of the nanowire 120, a gate electrode 30 on the surface of the gate dielectric layer 20 corresponding to the middle portion 122, an interlayer dielectric layer 40 on the surface of the substrate 110, the interlayer dielectric layer 40 having a first contact hole 41, a second contact hole 42 and a third contact hole 43 isolated from each other, the first contact hole 41 being connected to one of the source region 14 and the drain region 13, the second contact hole 42 being connected to the other of the source region 14 and the drain region 13, the third contact hole 43 being connected to the gate electrode 30; one of the drain contact 60 and the source contact 50 is located in the first contact hole 41, the other is located in the second contact hole 42, and the gate contact 70 is located in the third contact hole 43. In fig. 13 and 15, the drain contact 60 is located in the first contact hole 41, and the source contact 50 is located in the second contact hole 42.
In the present application, the source region and the drain region in the "connection of the first contact hole 41 to one of the source region 14 and the drain region 13, and the connection of the second contact hole 42 to the other of the source region 14 and the drain region 13" may be the source region and the drain region of the same sub-nanowire, or may be the source region and the drain region of different sub-nanowires. Specifically, when only one sub-nanowire is included in the nanowire of the device, the source region and the drain region refer to the source region and the drain region of the same sub-nanowire; when the nanowire comprises a plurality of sub-nanowires, the source region and the drain region are the source region and the drain region of different sub-nanowires, and two sub-nanowires are taken as an example, and the two sub-nanowires sequentially comprise a first sub-nanowire and a second sub-nanowire along a direction away from the substrate, wherein the first contact hole is in contact with one of the drain region of the first sub-nanowire and the source region of the second sub-nanowire, and the second contact hole is in contact with the other of the drain region of the first sub-nanowire and the source region of the second sub-nanowire.
The vertical nanowire transistor is manufactured by the method, the manufacturing process is simple, and the doping of the source region and/or the drain region is uniform, so that the performance of the device is good.
In order to simplify the manufacturing process and simultaneously form a conductive channel with better performance, i.e. the middle portion, as shown in fig. 15, in an embodiment of the present application, the width of the drain region 13 and the width of the source region 14 are both greater than the width of the middle portion 122.
In one embodiment of the present application, as shown in fig. 15, the width of the drain region 13 is the same as the width of the source region 14, which facilitates the fabrication of the device.
It should be noted that the term "width" as used herein refers to the width in the lateral direction parallel to the plane of the paper or the computer screen.
The width of the drain region 13 is the same as the width of the source region 14, and the contact surface of the drain region 13 with the intermediate portion 122 is a slope, and/or the contact surface of the source region 14 with the intermediate portion 122 is a slope. This allows a better formation of the conduction channel, thus ensuring a good performance of the device.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) according to the manufacturing method of the vertical nanowire transistor, the first contact hole and the second contact hole are formed firstly, then the heavily doped materials are filled, high-temperature annealing is carried out, after the high-temperature annealing, the doped impurities in the heavily doped materials in the first contact hole are diffused into the first end portion from the side face of the first end portion, and/or the doped impurities in the heavily doped materials in the second contact hole are diffused into the second end portion from the side face of the second end portion, so that one of the first end portion and the second end portion forms a source region, and/or the other one forms a drain region, and the middle portion is used as a conducting channel. In the manufacturing method, a transverse diffusion method is adopted to form a source region and/or a drain region, so that the doping process of the source region and the drain region of the vertical nanowire transistor is simple and easy to control, and injection damage can be well avoided.
2) The vertical nanowire transistor is manufactured by the method, the manufacturing process is simple, and the doping of the source region and/or the drain region is uniform, so that the performance of the device is good.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (18)
1. A method of fabricating a vertical nanowire transistor, the method comprising:
step S1, providing a substrate (10), wherein the substrate (10) includes a substrate (110) and a plurality of spaced nanowires (120) located on the substrate (110), each nanowire (120) includes at least one sub-nanowire (012) connected in sequence from bottom to top, each sub-nanowire (012) includes a first end portion (121), a middle portion (122) and a second end portion (123) connected in sequence, and the sub-nanowires (012) connected to the substrate (110) are connected to the substrate (110) through the first end portion (121);
step S2, forming a gate dielectric layer (20) on the outer surface of the nanowire (120), and forming a gate (30) on the outer surface of the gate dielectric layer (20) corresponding to the middle part (122);
step S3, forming an interlayer dielectric layer (40) on the exposed surface of the substrate (110);
step S4, etching to remove a part of the interlayer dielectric layer (40) and a part of the gate dielectric layer (20), forming a first contact hole (41) and a second contact hole (42) which are isolated from each other in the interlayer dielectric layer (40), wherein the first contact hole (41) is connected with the side surface of the first end part (121), and the second contact hole (42) is connected with the side surface of the second end part (123); and
step S5, filling heavily doped material (80) in the first contact hole (41) and/or the second contact hole (42), annealing, and laterally diffusing doped impurities in the heavily doped material, so that the first end portion (121) and/or the second end portion (123) form a drain region (13) and/or a source region (14).
2. Method of manufacturing according to claim 1, wherein the heavily doped material (80) has a doping concentration greater than 1.0 x 1019/cm3。
3. The method of manufacturing according to claim 1, wherein the step S2 includes:
forming the gate dielectric layer (20) on the exposed surface of the substrate (110) and on the exposed surface of the nanowire (120);
depositing a gate material (300) on the exposed surface of the gate dielectric layer (20); and
removing a portion of the gate material (300), the remaining gate material (300) forming the gate electrode (30).
4. The method of claim 1, wherein the outer surface of the sidewall of the gate electrode (30), the outer surface of the sidewall of the gate dielectric layer (20) on the first end portion (121), and the outer surface of the sidewall of the gate dielectric layer (20) on the second end portion (123) are on the same plane.
5. The method of manufacturing according to claim 1, wherein the step S3 includes:
depositing an interlayer dielectric material on exposed surfaces of the gate dielectric layer (20) and the gate electrode (30); and
and flattening the interlayer dielectric material to form the interlayer dielectric layer (40), wherein the surface of the interlayer dielectric layer (40) far away from the substrate (110) covers the gate dielectric layer (20) on the surface of the second end part (123).
6. Method according to claim 1, characterized in that the width of the first contact hole (41) and/or the second contact hole (42) is larger near one end of the substrate (110) than at the end remote from the substrate (110).
7. The method according to claim 1, wherein the first contact hole (41) comprises a first base portion (411) and a first connecting portion (412) connected to the first base portion (411), the first connecting portion (412) is connected to the first end portion (121), and a width of the first connecting portion (412) is greater than a width of the first base portion (411); the second contact hole (42) includes a second base portion (421) and a second connection portion (422) connected to the second base portion (421), the second connection portion (422) is connected to the second end portion (123), and a width of the second connection portion (422) is greater than a width of the second base portion (421).
8. The method according to claim 7, wherein both ends of the first connecting portion (412) are connected to two adjacent first end portions (121), respectively.
9. The method of claim 8, wherein the first connecting portion (412) has a height less than a height of the first end portion (121), and the second connecting portion (422) has a height less than a height of the second end portion (123).
10. The method of manufacturing of claim 1, wherein after the step S5, the method of manufacturing further comprises:
step S6, etching to remove the heavily doped material (80) in the first contact hole (41) and/or the second contact hole (42); and
step S7, filling metal in the first contact hole (41) and/or the second contact hole (42) to form a source contact (50) and a drain contact (60), etching to remove a part of the interlayer dielectric layer (40) between adjacent nanowires (120) to form a third contact hole (43), connecting the third contact hole (43) with the grid (30), filling metal in the third contact hole (43), and forming a grid contact (70).
11. The method of manufacturing of claim 10, wherein after the step S5, the method of manufacturing further comprises:
the third contact hole (43) has a width at an end closer to the substrate (110) larger than a width at an end farther from the substrate (110).
12. The method of manufacturing of claim 11, wherein after the step S5, the method of manufacturing further comprises:
the third contact hole (43) includes a third base portion (431) and a third connection portion (432) connected to the third base portion (431), the third connection portion (432) is connected to the intermediate portion (122), and a width of the third connection portion (432) is greater than a width of the third base portion (431).
13. The method of manufacturing of claim 12, wherein after the step S5, the method of manufacturing further comprises:
the height of the third connecting portion (432) is smaller than the height of the intermediate portion (122).
14. The method of claim 13, wherein the third contact hole (43) is located between two adjacent nanowires (120) and two ends of the third connecting portion (432) are respectively connected to two adjacent gates (30).
15. The method of claim 1, wherein the heavily doped material (80) comprises a base material and dopant impurities, the dopant impurities comprise at least one of B, P and As, and the base material comprises at least one of polysilicon, amorphous silicon, an oxide, a nitride, amorphous carbon, and an organic.
16. A vertical nanowire transistor, comprising:
a substrate (110);
the nanowire array comprises a plurality of spaced nanowires (120) positioned on the surface of a substrate (110), each nanowire (120) comprises at least one sub-nanowire (012) which are sequentially connected from bottom to top, each sub-nanowire (012) comprises a drain region (13), an intermediate portion (122) and a source region (14) which are sequentially connected, and the intermediate portion (122) is a conductive channel;
a gate dielectric layer (20) on an outer surface of the nanowire (120);
the grid electrode (30) is positioned on the outer surface of the grid dielectric layer (20) corresponding to the middle part (122);
an interlayer dielectric layer (40) located on the surface of the substrate (110), wherein the interlayer dielectric layer (40) is provided with a first contact hole (41), a second contact hole (42) and a third contact hole (43) which are isolated from each other, the first contact hole (41) is connected with one of the source region (14) and the drain region (13), the second contact hole (42) is connected with the other of the source region (14) and the drain region (13), and the third contact hole (43) is connected with the grid electrode (30);
metal contacts including source contacts (50), drain contacts (60), and gate contacts (70), one of the drain contacts (60) and the source contacts (50) being located in the first contact holes (41) and the other being located in the second contact holes (42), the gate contacts (70) being located in the third contact holes (43).
17. The vertical nanowire transistor of claim 16, wherein a width of the source region (14) and a width of the drain region (13) are both greater than a width of the intermediate portion (122).
18. The vertical nanowire transistor of claim 16, characterized in that the width of the source region (14) is the same as the width of the drain region (13).
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101399207A (en) * | 2007-09-24 | 2009-04-01 | 国际商业机器公司 | Manufacturing method for vertical nano-wire fet device and fet device manufactured thereby |
| CN102412301A (en) * | 2011-10-13 | 2012-04-11 | 复旦大学 | Nano-wire tunneling field-effect transistor with vertical structure and preparation method thereof |
| CN103151391A (en) * | 2013-03-18 | 2013-06-12 | 北京大学 | Short gate tunneling field effect transistor of vertical non-uniform doping channel and preparation method thereof |
| CN104823282A (en) * | 2012-12-18 | 2015-08-05 | 英特尔公司 | Vertical nanowire transistor with axially engineered semiconductor and gate metallization |
| CN106206706A (en) * | 2014-09-03 | 2016-12-07 | 台湾积体电路制造股份有限公司 | The method forming transistor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101399207A (en) * | 2007-09-24 | 2009-04-01 | 国际商业机器公司 | Manufacturing method for vertical nano-wire fet device and fet device manufactured thereby |
| CN102412301A (en) * | 2011-10-13 | 2012-04-11 | 复旦大学 | Nano-wire tunneling field-effect transistor with vertical structure and preparation method thereof |
| CN104823282A (en) * | 2012-12-18 | 2015-08-05 | 英特尔公司 | Vertical nanowire transistor with axially engineered semiconductor and gate metallization |
| CN103151391A (en) * | 2013-03-18 | 2013-06-12 | 北京大学 | Short gate tunneling field effect transistor of vertical non-uniform doping channel and preparation method thereof |
| CN106206706A (en) * | 2014-09-03 | 2016-12-07 | 台湾积体电路制造股份有限公司 | The method forming transistor |
Non-Patent Citations (1)
| Title |
|---|
| 垂直纳米线晶体管的制备技术;侯朝昭，姚佳欣，殷华湘;《半导体制造技术》;20170430;第42卷(第4期);283-292 * |
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