CN108511344A - Vertical nanowire transistor and manufacturing method thereof - Google Patents
Vertical nanowire transistor and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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Abstract
The application provides a vertical nanowire transistor and a manufacturing method thereof. The manufacturing method comprises the following steps: step S1, providing a substrate comprising a substrate and a plurality of spaced nanowires located on the substrate, each nanowire comprising sub-nanowires, each sub-nanowire comprising a first end portion, a middle portion, and a second end portion; step S2, forming a gate dielectric layer and a gate; step S3, forming an interlayer dielectric layer on the surface of the substrate; step S4, forming a first contact hole and a second contact hole which are isolated from each other in the interlayer dielectric layer, wherein the first contact hole is connected with the side surface of the first end part, and the second contact hole is connected with the side surface of the second end part; and step S5, filling heavily doped materials in the first contact hole and/or the second contact hole, carrying out high-temperature annealing diffusion, and carrying out transverse doping to form a drain region and/or a source region. In the manufacturing method, a transverse diffusion method is adopted to form a uniformly doped source region and/or drain region, so that the doping process of the source region and the drain region of the vertical nanowire transistor is simple and easy to control.
Description
Technical field
This application involves semiconductor applications, in particular to a kind of vertical nanowire transistor and its production method.
Background technology
CMOS integrated circuit micro sustainable developments, device architecture is from two-dimension plane structure (2D planar) to three-dimensional fin
Formula field-effect transistor (3D Fin Field Effect Transisitor, abbreviation 3D Fin FET), then arrive three-dimensional horizontal junction
Ring gate nano line field-effect transistor (the 3D Lateral Gate-All-Around Nanowire Field Effect of structure
Transisitor abbreviation 3D Lateral NW FET), future for more high integration, will develop to the ring of three-dimensional vertical structure
Gate nano line field-effect transistor (3D Vertical Gate-All-Around Nanowire Field Effect
Transisitor, abbreviation 3D Vertical NW FET or vertical nanowire transistor).Vertical nanowire transistor can be more
Inhibit short-channel effect well, because its cylindrical ring grid structure has best grid-control ability, it is suppressed that corner-turning effect, gate electrode
Can Electrostatic Control preferably be formed to channel region from multiple directions.
The manufacturing method of 3D Vertical NW FET includes two major classes：When from bottom to top using nanotechnology, one
Be compatible traditional cmos process from top to bottom.For former due to defective workmanship, process control issues are difficult by large-scale integrated.
Being compatible with traditional cmos process includes mainly：Vertical etch, selective etching modes such as epitaxial growth and polysilicon deposition again.
3D Vertical NW FET can also etch to form vertical nano-wire again using multilayer SiGe/Si layer-by-layer growths,
The mode of gate electrode is made followed by selective etching SiGe or Si.This method needs complicated multilayer epitaxial technique, raceway groove matter
Amount is difficult to ensure with interface quality.
In the production method of above-mentioned 3D Vertical NW FET, the doping of source-drain area and metal contact technique face
Many challenges mainly include complex process and the excessive both of these problems of contact area.
Invention content
The main purpose of the application is to provide a kind of vertical nanowire transistor and its production method, to solve existing skill
The more complex problem of the doping process of source-drain area in art.
To achieve the goals above, according to the one side of the application, the making side of vertical nanowire transistor is provided
Method, the production method include：Step S1, provides substrate, and above-mentioned substrate includes substrate and multiple intervals on above-mentioned substrate
Nano wire, each above-mentioned nano wire include at least one sub- nano wire sequentially connected from bottom to up, each above-mentioned sub- nano wire packet
Include sequentially connected first end, middle part and the second end, wherein the above-mentioned sub- nano wire being connect with above-mentioned substrate passes through
Above-mentioned first end is connect with above-mentioned substrate；Step S2 forms gate dielectric layer, among the above on the outer surface of above-mentioned nano wire
Between the corresponding above-mentioned gate dielectric layer in portion outer surface on form grid；Step S3, the forming layer on exposed above-mentioned substrate surface
Between dielectric layer；Step S4, the above-mentioned interlayer dielectric layer in etching removal part and the above-mentioned gate dielectric layer in part, in above-mentioned inter-level dielectric
Mutually isolated the first contact hole and the second contact hole are formed in layer, the side of above-mentioned first contact hole and above-mentioned first end connects
It connects, above-mentioned second contact hole is connect with the side of above-mentioned the second end；Step S5, in above-mentioned first contact hole and/or above-mentioned
Heavily doped material is filled in two contact holes, and is annealed, the impurity horizontal proliferation in above-mentioned heavily doped material so that on
It states first end and/or above-mentioned the second end selects to form drain region and/or source region.
Further, the doping concentration of above-mentioned heavily doped material is more than 1.0 × 1019/cm3。
Further, above-mentioned steps S2 includes：On the exposed surface of above-mentioned substrate and the exposed table of above-mentioned nano wire
Above-mentioned gate dielectric layer is formed on face；Grid material is deposited on the exposed surface of above-mentioned gate dielectric layer；Remove the above-mentioned grid material of part
Material, remaining above-mentioned grid material form above-mentioned grid.
Further, the outer surface of the side wall of above-mentioned grid, above-mentioned gate dielectric layer on above-mentioned first end side wall
The outer surface of the side wall of above-mentioned gate dielectric layer on outer surface and above-mentioned the second end is in the same plane.
Further, above-mentioned steps S3 includes：The sedimentary on the exposed surface of above-mentioned gate dielectric layer and above-mentioned grid
Between dielectric material；Above-mentioned interlevel dielectric material is planarized, forms above-mentioned interlayer dielectric layer, above-mentioned interlayer dielectric layer it is remote
Surface from above-mentioned substrate covers the above-mentioned gate dielectric layer on above-mentioned the second end surface.
Further, above-mentioned first contact hole and/or above-mentioned second contact hole are in the width close to above-mentioned substrate at one end
Relatively larger than in the width far from above-mentioned substrate at one end.
Further, above-mentioned first contact hole includes first our department and the first connecting portion that is connect with above-mentioned first our department,
Above-mentioned first connecting portion is connect with above-mentioned first end, and the width of above-mentioned first connecting portion is more than the width of above-mentioned first our department；
Above-mentioned second contact hole includes second our department and the second connecting portion that is connect with above-mentioned second our department, above-mentioned second connecting portion with it is upper
The second end connection is stated, the width of above-mentioned second connecting portion is more than the width of above-mentioned second our department；It is preferred that above-mentioned first connecting portion
Both ends connect respectively with two adjacent above-mentioned first ends；The height of further preferred above-mentioned first connecting portion is less than above-mentioned
The height of first end, the height of above-mentioned second connecting portion are less than the height of above-mentioned the second end.
Further, after above-mentioned steps S5, above-mentioned production method further includes：Step S6, etching removal above-mentioned first
Above-mentioned heavily doped material in contact hole and/or above-mentioned second contact hole；Step S7, in above-mentioned first contact hole and/or above-mentioned
Metal is filled in second contact hole, forms source contact and drain contact, and the part that etching removes between adjacent above-mentioned nano wire is above-mentioned
Interlayer dielectric layer forms third contact hole, and above-mentioned third contact hole connect with above-mentioned grid, filled in above-mentioned third contact hole
Metal forms grid contact；It is preferred that above-mentioned third contact hole is relatively larger than in the width close to above-mentioned substrate at one end far from above-mentioned
The width of substrate at one end；Further preferred above-mentioned third contact hole include third our department and connect with above-mentioned third our department the
Three interconnecting pieces, above-mentioned third interconnecting piece are connect with above-mentioned middle part, and the width of above-mentioned third interconnecting piece is more than above-mentioned third our department
Width, the height of still more preferably above-mentioned third interconnecting piece is less than the height of above-mentioned middle part.
Further, above-mentioned third contact hole is between two adjacent above-mentioned nano wires and above-mentioned third interconnecting piece
Both ends are connect with two adjacent above-mentioned grids respectively.
Further, above-mentioned heavily doped material includes basis material and impurity, and above-mentioned impurity includes B, P and As
At least one of, above-mentioned basis material include in polysilicon, non-crystalline silicon, oxide, nitride, amorphous carbon and organic matter extremely
Few one kind.
According to the another aspect of the application, a kind of vertical nanowire transistor is provided, the vertical nanowire transistor packet
It includes：Substrate；The nano wire at multiple intervals is located on the surface of above-mentioned substrate, and each above-mentioned nano wire includes connecting successively from bottom to up
At least one sub- nano wire connect, each above-mentioned sub- nano wire include sequentially connected drain region, middle part and source region, above-mentioned centre
Portion is conducting channel；Gate dielectric layer is located on the outer surface of above-mentioned nano wire；It is corresponding above-mentioned to be located at above-mentioned middle part for grid
On the outer surface of gate dielectric layer；Interlayer dielectric layer is located on the surface of above-mentioned substrate, and has in above-mentioned interlayer dielectric layer mutual
In the first contact hole, the second contact hole and the third contact hole of isolation, above-mentioned first contact hole and above-mentioned source region and above-mentioned drain region
A connection, above-mentioned second contact hole connect with another in above-mentioned source region and above-mentioned drain region, above-mentioned third contact hole and
Above-mentioned grid connection；Metal contacts, including source contact, drain contact and grid contact, and one in above-mentioned drain contact and the contact of above-mentioned source
A to be located in above-mentioned first contact hole, another is located in above-mentioned second contact hole, and above-mentioned grid contact is located at above-mentioned third and contacts
Kong Zhong.
Further, the width in the width of above-mentioned source region and above-mentioned drain region is all higher than the width of above-mentioned middle part, preferably on
State the of same size of the width of source region and above-mentioned drain region.
Using the technical solution of the application, in the production method, it is initially formed the first contact hole and the second contact hole, is then existed
Heavily doped material is filled, then carries out high annealing, after high annealing, the doping in heavily doped material in the first contact hole
Impurity is miscellaneous from the doping in the heavily doped material in the side diffusion to first end of first end and/or in the second contact hole
Matter is from the side diffusion of the second end to the second end, so that first end and a formation source region in the second end,
And/or another forms drain region, middle part is as conducting channel.In the production method, using the method for horizontal proliferation, formed equal
The source region of even doping and/or drain region so that the doping process of the source-drain area of vertical nanowire transistor is relatively simple and is easy to control,
And implant damage can be avoided well.
Description of the drawings
The accompanying drawings which form a part of this application are used for providing further understanding of the present application, and the application's shows
Meaning property embodiment and its explanation do not constitute the improper restriction to the application for explaining the application.In the accompanying drawings：
Fig. 1 to Figure 15 shows that the structure of the manufacturing process of the embodiment of the vertical nanowire transistor according to the application is shown
It is intended to.
Wherein, above-mentioned attached drawing includes the following drawings label：
10, substrate；11, pre- substrate；12, pre- nano wire；110, substrate；120, nano wire；012, sub- nano wire；121,
One end；122, middle part；123, the second end；13, drain region；14, source region；20, gate dielectric layer；30, grid；300, grid material
Material；40, interlayer dielectric layer；41, the first contact hole；411, first our department；412, first connecting portion；42, the second contact hole；421、
Second our department；422, second connecting portion；43, third contact hole；431, third our department；432, third interconnecting piece；50, source contacts；
60, drain contact；70, grid contact；80, heavily doped material.
Specific implementation mode
It is noted that following detailed description is all illustrative, it is intended to provide further instruction to the application.Unless another
It indicates, all technical and scientific terms used herein has usual with the application person of an ordinary skill in the technical field
The identical meanings of understanding.
It should be noted that term used herein above is merely to describe specific implementation mode, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative
It is also intended to include plural form, additionally, it should be understood that, when in the present specification using term "comprising" and/or " packet
Include " when, indicate existing characteristics, step, operation, device, component and/or combination thereof.
It should be understood that when element (such as layer, film, region or substrate) is described as in another element "upper", this yuan
Part can be directly on another element, or intermediary element also may be present.Moreover, in specification and following claims
In, when description has element " connected " to another element, which " can be directly connected to " to another element, or pass through third
Element " electrical connection " is to another element.
As background technology is introduced, the doping process of the source-drain area of vertical nanowire transistor in the prior art compared with
Complexity, in order to solve technical problem as above, present applicant proposes a kind of vertical nanowire transistors and its production method.
In a kind of typical embodiment of the application, a kind of production method of vertical nanowire transistor is provided, on
Stating production method includes：
Step S1, provides substrate 10, and above-mentioned substrate 10 includes substrate 110 and multiple intervals for being located on substrate 110 are received
Rice noodles 120, each above-mentioned nano wire 120 include at least one sub- nano wire 012 sequentially connected from bottom to up, each above-mentioned sub- nanometer
Line 012 includes sequentially connected first end 121, middle part 122 and the second end 123, wherein is connected with above-mentioned substrate 110
The above-mentioned sub- nano wire 012 connect is connect by above-mentioned first end 121 with above-mentioned substrate 110, as shown in figure 3, in the figure, nanometer
Line only includes a sub- nano wire；
Step S2 forms gate dielectric layer 20 on the outer surface of above-mentioned nano wire 120, structure shown in Fig. 4 is formed, upper
It states and forms above-mentioned grid 30 on the surface of the corresponding above-mentioned gate dielectric layer of middle part 122 20, form structure shown in fig. 6；
Step S3 forms interlayer dielectric layer 40 on the exposed surface of above-mentioned substrate 110, forms structure shown in Fig. 7；
Step S4, the above-mentioned interlayer dielectric layer 40 in etching removal part and the above-mentioned gate dielectric layer 20 in part, in above-mentioned interlayer
Mutually isolated the first contact hole 41 and the second contact hole 42 are formed in dielectric layer 40, as shown in Fig. 8 and Fig. 9, are connect due to first
Contact hole 41 and the second contact hole 42 are mutually isolated, so, in sectional view, it cannot show that the first contact hole 41 connects with second simultaneously
Contact hole 42, therefore the first contact hole 41 is merely illustrated in Fig. 8, it is the second contact hole 42 in sectional view Fig. 9, above-mentioned first
Contact hole 41 is connect with the side of above-mentioned first end 121, and above-mentioned second contact hole 42 and the side of above-mentioned the second end 123 connect
It connects；
Step S5 fills heavily doped material 80 in above-mentioned first contact hole 41 and/or above-mentioned second contact hole 42, goes forward side by side
Row annealing so that Doped ions therein are lateral and selectively diffuse in source region and/or drain region, so that above-mentioned first
One in end 121 and/or above-mentioned the second end 123 forms drain region 13 and/or source region 14, as shown in Figure 10.
It should be noted that in step S5 in the above method, can be connect in above-mentioned first contact hole 41 and above-mentioned second
Heavily doped material 80 is filled in one in contact hole 42 and carries out annealing forms source region and one in drain region, it can also be above-mentioned
Heavily doped material 80 is filled in first contact hole 41 and above-mentioned second contact hole 42 and carries out annealing forms source region and drain region.This
Field technology personnel can fill heavily doped material according to actual conditions into two kinds of contact holes, can also only be filled out in one kind
Fill heavily doped material.When filling metal into a kind of contact hole and annealing forms one in source region and drain region, source region and leakage
Another in area may be used other methods in the prior art and be formed, and specific forming step can step S5 it
Before, it can also be after step s 5.
It should be noted that in the application " above-mentioned first contact hole 41 is connect with the side of above-mentioned first end 121,
Above-mentioned second contact hole 42 is connect with the side of above-mentioned the second end 123 " in first end 121 and the second end 123 can be with
It is the first end 121 and the second end 123 of same sub- nano wire, can also be the first end 121 of different sub- nano wires
With the second end 123.Specifically, when only including a sub- nano wire in the nano wire of the device, first end 121 here
Refer to just the first end 121 and the second end 123 of the same sub- nano wire with the second end 123；When the nano wire includes
When multiple sub- nano wires, first end 121 here and the second end 123 be exactly different sub- nano wires first end 121 with
The second end 123 illustrates that the two sub- nano wires are followed successively by the first son along the direction far from substrate by taking two sub- nano wires as an example
Nano wire and the second sub- nano wire, wherein the source region in the drain region and the second sub- nano wire of the first contact hole and the first sub- nano wire
In a contact, the second contact hole connects with another in the drain region of the first sub- nano wire and the source region of the second sub- nano wire
It touches.
Etching in above-mentioned steps S4 and follow-up step S6 can be any feasible lithographic method in the prior art,
It can be dry etching, can be wet etching, be specifically as follows RIE etchings or ICP etchings etc., can also be a variety of quarters
Etching method, which is used in combination, completes some etch step.Those skilled in the art can select suitable etching according to actual conditions
Method completes step S4 and follow-up step S6.
In the production method of above-mentioned vertical nano-wire, it is initially formed the first contact hole and the second contact hole, is then being filled
Heavily doped material, then high annealing is carried out, after high annealing, the impurity in heavily doped material in the first contact hole
From the side horizontal proliferation to first end of first end, and/or, the doping in heavily doped material in the second contact hole is miscellaneous
Matter is from the side horizontal proliferation of the second end to the second end, so that first end and a formation source in the second end
Area and/or another formation drain region, middle part is as conducting channel.In the production method, using the method for horizontal proliferation,
Source region and/or drain region are formed in the vertical nano-wire in different levels or region so that the source-drain area of vertical nanowire transistor
Doping process it is relatively simple and be easy to control.
It is above-mentioned heavy in a kind of embodiment of the application in order to further ensure the preferable source region of forming properties and/or drain region
The doping concentration of dopant material 80 is more than 1.0 × 1019/cm3。
Sub- nano wire in the application can be concave-convex sub- nano wire, i.e., the width of sub- nano wire is uneven, such as Fig. 3 institutes
Show, the width of the width of above-mentioned first end 121 and above-mentioned the second end 123 is all higher than above-mentioned middle part 122；It can also be width
The uniform sub- nano wire of degree, the i.e. width of first end, the second end and middle part are equal.
It should be noted that " width " here refer to be parallel to it is laterally wide in the plane of paper or computer screen
Degree.
In a kind of embodiment of the application, as shown in figure 3, when group nano wire is concave-convex sub- nano wire, above-mentioned first end
The width in portion 121 is of same size with above-mentioned the second end 123, the making of device more convenient in this way.
As shown in figure 3, the width of middle part is smaller, it therefore, on two side is respectively provided with a groove, which can be
C-shaped, D-shaped, half I-shaped, trapezoidal, triangle or Sigma's shape.Those skilled in the art can select to close according to actual conditions
The groove of conformal shape.
In a kind of specific embodiment of the application, above-mentioned steps S1 includes：Step S11 provides substrate 10, such as Fig. 1 institutes
Show；Step S12, etching removal part above-mentioned substrate 10, obtain substrate 110 be located at 110 surface of above-mentioned substrate on it is multiple
The nano wire 120 at interval, as shown in Figure 3.
It should be noted that before the etching of step S12, the side for first passing through photoetching or the hard mask of pattern transfer is needed
Method defines the planar graph of subsequent nano wire vertical structure, which can be round, rectangular, rectangle, ellipse etc., size
Between 1 nanometer to 100 nanometers, specific method is not limited to the above method.
More specifically, above-mentioned steps S12 can also include：Step S121, the above-mentioned substrate 10 of etching removal part, forms
The pre- nano wire 12 of pre- substrate 11 and multiple intervals on above-mentioned 11 surface of pre- substrate, as shown in Figure 2；Step S122 is carved
Etching off removes the above-mentioned pre- substrate 11 in part, and the pre- substrate of pre- nano wire and part connected to it forms above-mentioned nano wire 120, such as Fig. 3
Shown, remaining pre- substrate forms substrate 110, and this method is simple, and is further ensured that the shape and ruler of the nano wire to be formed
It is very little identical as the dimension and shape of scheduled nano wire.
In order to avoid being damaged to pre- nano wire during etching above-mentioned pre- substrate, in a kind of figure of the application not
In the embodiment shown, between above-mentioned steps S121 and above-mentioned steps S122, above-mentioned steps S2 further includes：In above-mentioned pre- nanometer
Protective layer is formed on the exposed surface of line 12, the material of above-mentioned protective layer includes in chloride, carbide, oxide and nitride
It is at least one.
In order to obtain ultra-thin protective layer, in a kind of embodiment of the application, after forming protective layer, also to above-mentioned protection
Layer carries out Surface Treatment with Plasma.Specifically, O ions or N gas ions processing surface may be used, form super thin oxide layer or nitrogen
Change layer as protective layer.
For the device including multiple sub- nano wires, step S1 further includes：It, will after forming first nano wire
The nano wire protects, then is performed etching to substrate and to form second sub- nano wire, and the etching of subsequent sub- nano wire is formed
Before, the sub- nano wire that will be formed to preceding step is protected.Specifically, guarantor can be formed on the surface of sub- nano wire
Sheath, specific material of the protective layer etc. may refer to protective layer above, and details are not described herein again.
Specifically, the method that etching forms multiple sub- nano wires includes BOSCH methods.The principle of BOSCH methods is to react
Passivation gas such as C is passed through in chamber in turn4F8With etching gas SF6It is reacted with sample, the whole process of technique is deposit
Passivation layer step and etch step are alternately and repeatedly.Wherein, protective gas C4F8Life is decomposed under the action of high-density plasma
Protective layer is formed at fluorocarbon polymer, is deposited on the sample surfaces for being ready for figure.
In a kind of embodiment of the application, above-mentioned steps S121 includes successively：Anisotropic etching method, isotropic etching
Method and anisotropic etching method etch above-mentioned pre- substrate 11, form structure shown in Fig. 3.
Certainly, the nano wire of the application and the forming process of substrate are not limited to above-mentioned method, those skilled in the art
Suitable forming method can be selected to form above-mentioned nano wire and substrate according to actual conditions.
In a kind of specific embodiment, in the above-mentioned sub- nano wire of adjacent two in a nano wire 012, close to above-mentioned
The second end 123 of the above-mentioned sub- nano wire 012 of substrate 110 is first of the above-mentioned sub- nano wire 012 far from above-mentioned substrate 110
End 121.The manufacture craft of the device can be simplified in this way and reduce the cost of manufacture of the device.
For the nano wire including multiple sub- nano wires, the forming process in source region and drain region and a son is only included
The nano wire of nano wire it is similar, can specifically adjust the shape of contact hole, be formed simultaneously using the diffusion of heavily doped material more
The source region of a sub- nano wire and drain region, can also gradepervasion form source region and the drain region of multiple sub- nano wires, art technology
Personnel can select suitable method according to actual conditions, just not repeat herein.In another embodiment of the application, on
Stating step S2 includes：Above-mentioned grid are formed on the exposed surface of above-mentioned substrate 110 and on the exposed surface of above-mentioned nano wire 120
Dielectric layer 20, as shown in Figure 4；Grid material 300 is deposited on the exposed surface of above-mentioned gate dielectric layer 20, forms knot shown in fig. 5
Structure；The above-mentioned grid material 300 of part is removed, remaining above-mentioned grid material 300 forms above-mentioned grid 30 shown in fig. 5.
The gate dielectric layer of the application may be used conventional material in the prior art and be formed, for example may include titanium dioxide
Silicon, silicon oxynitride and/or high-g value, those skilled in the art can select suitable material according to actual conditions.
In order to enable gate dielectric layer has higher dielectric constant, and then preferably isolated gate and conducting channel, reduce leakage
Electricity, in a kind of embodiment of the application, the material of above-mentioned gate dielectric layer includes hafnium, and above-mentioned hafnium is selected from HfO2、
HfSiO、HfSiON、HfTiO、HfZrO、Al2O3、La2O3、ZrO2With it is one or more in LaAlO.
The grid 30 of the application is metal gates or polysilicon gate, and those skilled in the art can be according to actual conditions
Selection suitable material forms the grid 30 of the application.
When above-mentioned gate dielectric layer is high-K dielectric layer, and when grid is metal gates, in the step S2 of the application can be with
Gate dielectric layer and grid material are formed using HKMG (High K insulating layers+metal gates) process substrate.
Etching method may be used in the process of above-mentioned removal grid material 300, is specifically as follows isotropic etching.
As shown in fig. 6, in order to simplify etching process, to simplify manufacture craft, producing efficiency is improved, above-mentioned grid 30
The outer surface of the side wall of above-mentioned gate dielectric layer 20 on the outer surface of side wall, above-mentioned first end 121 and above-mentioned the second end
The outer surface of the side wall of above-mentioned gate dielectric layer 20 on 123 is in the same plane.
There is good flatness in order to further ensure making the device formed, to good performance, this Shen
In a kind of embodiment please, above-mentioned steps S3 includes：It sinks on the exposed surface of above-mentioned gate dielectric layer 20 and above-mentioned grid 30
Interlevel dielectric material；Above-mentioned interlevel dielectric material is planarized, interlayer dielectric layer 40 is formed, as shown in fig. 7, above-mentioned layer
Between the surface far from above-mentioned substrate 110 of dielectric layer 40 cover the above-mentioned gate dielectric layer 20 on 123 surface of above-mentioned the second end.
The Doped ions in heavily doped material can be diffused to first end and the second end, shape to further ensure that
Source region at predetermined dopant concentration and drain region, and it is good to ensure that the metal eventually formed contact can be formed with corresponding structure simultaneously
Good Ohmic contact, in a kind of embodiment of the application, as shown in Fig. 8 and Fig. 9, above-mentioned first contact hole 41 and/or above-mentioned the
Two contact holes 42 are relatively larger than in the width close to 110 at one end of above-mentioned substrate in the width far from 110 at one end of above-mentioned substrate.
In a kind of specific embodiment, as shown in figure 8, above-mentioned first contact hole 41 include first our department 411 and with it is above-mentioned
The first connecting portion 412 of first our department 411 connection, above-mentioned first connecting portion 412 connect with above-mentioned first end 121, and above-mentioned the
The width of one interconnecting piece 412 is more than the width of above-mentioned first our department 411；As shown in figure 9, above-mentioned second contact hole 42 includes second
Our department 421 and the second connecting portion 422 being connect with above-mentioned second our department 421, above-mentioned second connecting portion 422 and above-mentioned the second end
123 connections, the width of above-mentioned second connecting portion 422 are more than the width of above-mentioned second our department 421.
In order to further increase the integrated level of vertical nano-wire, and simplify technique, promotes producing efficiency, one kind of the application
In embodiment, as shown in figure 8, the both ends of above-mentioned first connecting portion 412 connect with two adjacent above-mentioned first ends 121 respectively
It connects, as shown in figure 12 in this way, the contacting metal filled in the first contact hole is just respectively formed with two adjacent nano wires corresponding
Ohmic contact.
In another embodiment of the application, as shown in figure 8, the height of above-mentioned first connecting portion 412 is less than above-mentioned first
The height of end 121, as shown in figure 9, the height of above-mentioned second connecting portion 422 is less than the height of above-mentioned the second end 123.In this way
It can preferably avoid Doped ions from diffusing in other regions, the contacting metal being subsequently arranged and its can also be further avoided
He forms Ohmic contact in region, and then ensure that vertical nanowire transistor has preferable performance.
In a kind of specific embodiment of the application, above-mentioned production method further includes：
Step S6, etching remove the above-mentioned heavy doping material in above-mentioned first contact hole 41 and/or above-mentioned second contact hole 42
Material 80, as shown in figure 11；
Step S7 fills metal in above-mentioned first contact hole 41 and/or above-mentioned second contact hole 42, forms source contact 50
With drain contact 60, respectively as shown in Figure 13 and Figure 12, etching removes the above-mentioned interlayer in part between adjacent above-mentioned nano wire 120 and is situated between
Matter layer 40 forms third contact hole 43, and as shown in figure 14, above-mentioned third contact hole 43 is located at the third side of above-mentioned nano wire 120,
Above-mentioned first side is opposite and adjacent with above-mentioned the second side with above-mentioned third side, and above-mentioned third contact hole 43 connects with above-mentioned grid 30
It connects, metal is filled in above-mentioned third contact hole 43, form grid contact 70, as shown in figure 15.
It should be noted that in above-mentioned steps S7, " metal is filled in the first contact hole 41 and the second contact hole 42 and forms source
The sequencing of the process of contact and drain contact " and the process of " formation third contact hole " is simultaneously not fixed, and can be initially formed the
Then three contact holes, while being filled metal into the first contact hole 41, the second contact hole 42 and third contact hole 43 and being formed pair
The metal contact answered；Can also be first carry out the first contact hole 41 in the second contact hole 42 fill metal formed source contact and
Then drain contact re-forms third contact hole, metal is finally filled into third contact hole 43, forms grid contact.
It should also be noted that, when heavily doped material itself is metal, in the production method of the application, can not also go
Except heavily doped material, directly as contacting metal.
In order to ensure that the metal eventually formed contact can form good Ohmic contact, a kind of reality of the application with grid
It applies in example, above-mentioned third contact hole 43 is in the width close to 110 at one end of above-mentioned substrate relatively larger than far from above-mentioned substrate 110 1
Width at end.
In another embodiment of the application, as shown in figure 14, above-mentioned third contact hole 43 include third our department 431 and with
The third interconnecting piece 432 that above-mentioned third our department 431 connects, above-mentioned third interconnecting piece 432 is connect with above-mentioned middle part 122, above-mentioned
The width of third interconnecting piece 432 is more than the width of above-mentioned third our department 431.It can better ensure that grid is formed with metal in this way
Good Ohmic contact.
In order to further increase the integrated level of vertical nano-wire, and simplify technique, promotes producing efficiency, one kind of the application
In embodiment, as shown in figure 14, above-mentioned third contact hole 43 is between two adjacent above-mentioned nano wires 120 and above-mentioned third
The both ends of interconnecting piece 432 are connect with two adjacent above-mentioned grids 30 respectively, as shown in figure 15 in this way, are filled out in third contact hole
The contacting metal filled is just respectively formed corresponding Ohmic contact with two adjacent nano wires.
Heavily doped material in the application includes basis material and impurity, and above-mentioned impurity includes in B, P and As
At least one, above-mentioned basis material include in polysilicon, non-crystalline silicon, oxide, nitride, amorphous carbon and organic matter at least
It is a kind of.Those skilled in the art can select suitable impurity and basis material according to actual conditions.For example it selects
Low-k materials select some metal oxides.
It avoids removing more interlayer dielectric layer while heavily doped material layer to remove in a simpler way, this Shen
In a kind of embodiment please, above-mentioned heavily doped material 80 and the etching selection ratio of the material of above-mentioned interlayer dielectric layer 40 are more than 8.
In order to further ensure that the isolation effect of interlayer dielectric layer, in a kind of embodiment of the application, above-mentioned inter-level dielectric
The material of layer is selected from SiO2And/or Si3N4。
Above-mentioned substrate 10 in the application can be the substrate that available any material in the prior art is formed, Ke Yiwei
Si substrates, Ge substrates, sapphire substrates, silicon carbide substrate, gallium nitride substrates, GaAs substrate, Zinc oxide-base bottom, diamond,
Aluminum-nitride-based bottom, metal or metalloid substrate etc., those skilled in the art can be according to the suitable materials that actual conditions select
Substrate.
In order to simplify technique, and the performance of device is improved simultaneously, in a kind of embodiment of the application, above-mentioned substrate 10 is silicon
Substrate.
In a kind of embodiment of the application, after forming above-mentioned source contact, drain contact and grid contact, above-mentioned production method
Further include the steps that forming multilayer interconnection, this step can be used conventional technique, just repeat no more herein.
In the typical embodiment of another kind of the application, a kind of vertical nanowire transistor is provided, the straight nano wire
Transistor is made using above-mentioned any production method.As shown in figure 15, which includes lining
Nano wire, gate dielectric layer 20, grid 30, the interlayer at bottom 110, multiple intervals with source region 14, drain region 13 and middle part 122
Dielectric layer 40, source contact 50, drain contact 60 and grid contact 70.
In a kind of specific embodiment, above-mentioned vertical nanowire transistor is made of any one above-mentioned production method
It forms.
Specifically, nano wire 120 is located on the surface of substrate 110, and each above-mentioned nano wire 120 includes connecting successively from bottom to up
At least one sub- nano wire 012 connect, each above-mentioned sub- nano wire 012 include sequentially connected drain region 13, middle part 122 and source
Area 14, above-mentioned middle part 122 are conducting channel；Gate dielectric layer 20 is located on the exposed surface of above-mentioned nano wire 120, grid 30
In on the surface of the corresponding above-mentioned gate dielectric layer of above-mentioned middle part 122 20, interlayer dielectric layer 40 is located at the surface of above-mentioned substrate 110
On, and there is the first mutually isolated contact hole 41, the second contact hole 42 and third contact hole 43 in above-mentioned interlayer dielectric layer 40,
Above-mentioned first contact hole 41 is connect with one in above-mentioned source region 14 and above-mentioned drain region 13, above-mentioned second contact hole 42 and above-mentioned source
Another connection in area 14 and above-mentioned drain region 13, above-mentioned third contact hole 43 are connect with above-mentioned grid 30；Drain contact 60 and source
One in contact 50 is located in above-mentioned first contact hole 41, another is located in above-mentioned second contact hole 42, and grid contact 70
In above-mentioned third contact hole 43.In Figure 13 and Figure 15, drain contact 60 is located in above-mentioned first contact hole 41, and source contact 50 is located at
In above-mentioned second contact hole 42.
It should be noted that in the application " in above-mentioned first contact hole 41 and above-mentioned source region 14 and above-mentioned drain region 13
One connection, above-mentioned second contact hole 42 connect with another in above-mentioned source region 14 and above-mentioned drain region 13 " in source region and leakage
Area can be source region and the drain region of same a sub- nano wire, can also be source region and the drain region of different sub- nano wires.Specifically, when
As soon as only include a sub- nano wire in the nano wire of the device, source region here and the source that drain region refers to the same sub- nano wire
Area and drain region；When the nano wire includes multiple sub- nano wires, source region here and the source that drain region is exactly different sub- nano wires
Area and drain region illustrate that the two sub- nano wires are followed successively by the first son along the direction far from substrate and receive by taking two sub- nano wires as an example
Rice noodles and the second sub- nano wire, wherein in the source region in the drain region and the second sub- nano wire of the first contact hole and the first sub- nano wire
A contact, the second contact hole contacts with another in the source region of the drain region of the first sub- nano wire and the second sub- nano wire.
Above-mentioned vertical nanowire transistor is adopted to be made with the aforedescribed process, and manufacture craft is fairly simple, also,
The doping in source region and/or drain region is more uniform so that the better performances of device.
In order to simplify manufacture craft, and it is formed simultaneously the conducting channel of better performances, i.e. middle part, as shown in figure 15, this
In a kind of embodiment of application, the width of the width in above-mentioned drain region 13 and above-mentioned source region 14 is all higher than the width of above-mentioned middle part 122
Degree.
In a kind of embodiment of the application, as shown in figure 15, the width in drain region 13 and above-mentioned source region 14 it is of same size, this
Sample is more convenient the making of device.
It should be noted that " width " here refer to be parallel to it is laterally wide in the plane of paper or computer screen
Degree.
The rank with above-mentioned middle part 122 of the width in above-mentioned drain region 13 and the above-mentioned drain region 13 of same size of above-mentioned source region 14
It with the interface of above-mentioned middle part 122 is inclined-plane that junction, which is inclined-plane and/or above-mentioned source region 14,.It can preferably be formed in this way
Conducting channel, to ensure the superperformance of device.
It can be seen from the above description that the application the above embodiments realize following technique effect：
1), in the production method of the vertical nanowire transistor of the application, it is initially formed the first contact hole and the second contact hole,
Then in filling heavily doped material, then high annealing is carried out, after high annealing, in the heavily doped material in the first contact hole
Impurity from the heavily doped material in the side diffusion to first end of first end and/or in the second contact hole
Impurity is from the side diffusion of the second end to the second end, so that first end and a formation in the second end
Source region and/or another formation drain region, middle part is as conducting channel.In the production method, using the method for horizontal proliferation,
Forming source region and/or drain region so that the doping process of the source-drain area of vertical nanowire transistor is relatively simple and is easy to control, and
Implant damage can be avoided well.
2), the vertical nanowire transistor of the application, adopts and is made with the aforedescribed process, and manufacture craft is simpler
It is single, also, the doping in source region and/or drain region is more uniform so that the better performances of device.
The foregoing is merely the preferred embodiments of the application, are not intended to limit this application, for the skill of this field
For art personnel, the application can have various modifications and variations.Within the spirit and principles of this application, any made by repair
Change, equivalent replacement, improvement etc., should be included within the protection domain of the application.
Claims (12)
1. a kind of production method of vertical nanowire transistor, which is characterized in that the production method includes：
Step S1, provides substrate (10), the substrate (10) include substrate (110) with it is multiple on the substrate (110)
The nano wire (120) at interval, each nano wire (120) include at least one sub- nano wire sequentially connected from bottom to up
(012), each sub- nano wire (012) includes sequentially connected first end (121), middle part (122) and the second end
(123), wherein the sub- nano wire (012) being connect with the substrate (110) by the first end (121) with it is described
Substrate (110) connects；
Step S2 forms gate dielectric layer (20) on the outer surface of the nano wire (120), corresponding in the middle part (122)
The gate dielectric layer (20) outer surface on formed grid (30)；
Step S3 forms interlayer dielectric layer (40) on the exposed substrate (110) surface；
Step S4, the etching removal part interlayer dielectric layer (40) and the part gate dielectric layer (20), in the interlayer
Form mutually isolated the first contact hole (41) and the second contact hole (42) in dielectric layer (40), first contact hole (41) with
The side of the first end (121) connects, and second contact hole (42) connect with the side of the second end (123)；
And
Step S5, the filling heavily doped material (80) in first contact hole (41) and/or second contact hole (42), and
It anneals, the impurity horizontal proliferation in the heavily doped material so that the first end (121) and/or described
Two ends (123) form drain region (13) and/or source region (14).
2. manufacturing method according to claim 1, which is characterized in that the doping concentration of the heavily doped material (80) is more than
1.0×1019/cm3。
3. manufacturing method according to claim 1, which is characterized in that the step S2 includes：
The gate medium is formed on the exposed surface of the substrate (110) and on the exposed surface of the nano wire (120)
Layer (20)；
Grid material (300) is deposited on the exposed surface of the gate dielectric layer (20)；And
The grid material (300) of part is removed, the remaining grid material (300) forms the grid (30).
4. manufacturing method according to claim 1, which is characterized in that the outer surface of the side wall of the grid (30), described
The outer surface of the side wall of the gate dielectric layer (20) on first end (121) and described on the second end (123)
The outer surface of the side wall of gate dielectric layer (20) is in the same plane.
5. manufacturing method according to claim 1, which is characterized in that the step S3 includes：
The interlayer dielectric material on the exposed surface of the gate dielectric layer (20) and the grid (30)；And
The interlevel dielectric material is planarized, the interlayer dielectric layer (40) is formed, the interlayer dielectric layer (40)
Surface far from the substrate (110) covers the gate dielectric layer (20) on the second end (123) surface.
6. manufacturing method according to claim 1, which is characterized in that first contact hole (41) and/or described second
Contact hole (42) is relatively larger than in the width close to the substrate (110) at one end in the width far from the substrate (110) at one end
Degree.
7. manufacturing method according to claim 1, which is characterized in that first contact hole (41) includes first our department
(411) and with first our department (411) first connecting portion (412) connecting, the first connecting portion (412) and described first
End (121) connects, and the width of the first connecting portion (412) is more than the width of first our department (411)；Described second connects
Contact hole (42) includes second our department (421) and the second connecting portion (422) that is connect with second our department (421), and described second
Interconnecting piece (422) is connect with the second end (123), and the width of the second connecting portion (422) is more than described second our department
(421) width；It is preferred that the both ends of the first connecting portion (412) connect with two adjacent first ends (121) respectively
It connects；The height of the further preferred first connecting portion (412) is less than the height of the first end (121), and described second connects
The height of socket part (422) is less than the height of the second end (123).
8. manufacturing method according to claim 1, which is characterized in that after the step S5, the production method is also
Including：
Step S6, etching remove the heavy doping material in first contact hole (41) and/or second contact hole (42)
Expect (80)；And
Step S7 fills metal in first contact hole (41) and/or second contact hole (42), forms source contact
(50) with drain contact (60), the part interlayer dielectric layer (40) formation between removing the adjacent nano wire (120) is etched
Third contact hole (43), the third contact hole (43) connect with the grid (30), are filled out in the third contact hole (43)
Metal is filled, grid contact (70) is formed；It is preferred that the third contact hole (43) close to the substrate (110) at one end width compared with
More than in the width far from the substrate (110) at one end；The further preferred third contact hole (43) includes third our department
(431) and with the third our department (431) the third interconnecting piece (432) connecting, the third interconnecting piece (432) and the centre
Portion (122) connects, and the width of the third interconnecting piece (432) is more than the width of the third our department (431), still more preferably
The height of the third interconnecting piece (432) is less than the height of the middle part (122).
9. production method according to claim 8, which is characterized in that the third contact hole (43) is located at adjacent two
Between the nano wire (120) and the both ends of the third interconnecting piece (432) connect with two adjacent grids (30) respectively
It connects.
10. manufacturing method according to claim 1, which is characterized in that the heavily doped material (80) includes basis material
With impurity, the impurity includes at least one of B, P and As, described matrix material include polysilicon, non-crystalline silicon,
At least one of oxide, nitride, amorphous carbon and organic matter.
11. a kind of vertical nanowire transistor, which is characterized in that the vertical nanowire transistor includes：
Substrate (110)；
The nano wire (120) at multiple intervals is located on the surface of the substrate (110), and each nano wire (120) includes under
Supreme sequentially connected at least one sub- nano wire (012), each sub- nano wire (012) includes sequentially connected drain region
(13), middle part (122) and source region (14), the middle part (122) are conducting channel；
Gate dielectric layer (20) is located on the outer surface of the nano wire (120)；
Grid (30) is located on the outer surface of the corresponding gate dielectric layer (20) of the middle part (122)；
Interlayer dielectric layer (40), be located at the substrate (110) surface on, and in the interlayer dielectric layer (40) have mutually every
From the first contact hole (41), the second contact hole (42) and third contact hole (43), first contact hole (41) and the source
A connection in area (14) and the drain region (13), second contact hole (42) and the source region (14) and the drain region
(13) another connection in, the third contact hole (43) connect with the grid (30)；
Metal contacts, including source contact (50), drain contact (60) and grid contact (70), the drain contact (60) and source contact
(50) one in is located in first contact hole (41), another is located in second contact hole (42), and the grid connect
(70) are touched to be located in the third contact hole (43).
12. vertical nanowire transistor according to claim 11, which is characterized in that the width of the source region (14) and institute
The width for stating drain region (13) is all higher than the width of the middle part (122), width and the drain region of the preferably described source region (14)
(13) of same size.
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