CN112466747B - Manufacturing method of trench gate and trench gate power device - Google Patents

Manufacturing method of trench gate and trench gate power device Download PDF

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CN112466747B
CN112466747B CN201910842552.XA CN201910842552A CN112466747B CN 112466747 B CN112466747 B CN 112466747B CN 201910842552 A CN201910842552 A CN 201910842552A CN 112466747 B CN112466747 B CN 112466747B
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layer
trench
dielectric layer
gate
gate dielectric
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CN112466747A (en
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平延磊
黄文康
曾伟雄
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SiEn Qingdao Integrated Circuits Co Ltd
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SiEn Qingdao Integrated Circuits Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors

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Abstract

The invention provides a manufacturing method of a trench gate and a trench gate power device, which comprises the following steps: 1) Providing a substrate, and forming a groove in the substrate; 2) Forming a non-conformal liner layer in the trench covering an upper portion of the trench; 3) Forming a first gate dielectric layer at the lower part and the bottom of the exposed groove; 4) Removing the non-conformal liner layer to expose the upper part of the trench; 5) Forming a second gate dielectric layer on the upper part of the exposed groove, wherein the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer; 6) And filling the grid layer in the groove. According to the invention, the gate dielectric layers in the groove are respectively prepared through the non-conformal liner, the thickness of the first gate dielectric layer at the lower part of the groove is firstly controlled through oxidation or atomic layer deposition, and the thickness of the first gate dielectric layer can be simultaneously increased when the second gate dielectric layer at the upper part of the groove is deposited, so that the capacitance between the grid and the drain can be effectively reduced, the QG parameter is obviously reduced, and the quality factor of the power device is greatly optimized.

Description

Manufacturing method of trench gate and trench gate power device
Technical Field
The invention belongs to the field of semiconductor design and manufacture, and particularly relates to a trench gate and a manufacturing method of a trench gate power device.
Background
A power device is an amplifying device for the purpose of outputting a large power. Therefore, it is required that it can output a large voltage and current at the same time. Quality factors are commonly used to evaluate the quality of power MOSFET products, and are denoted as FOM = RDSON × QG, where RDSON denotes the on-resistance of the power MOSFET and QG denotes the gate charge.
The power loss of a power MOSFET is generally the sum of the conduction loss and the switching loss, and the higher the on-resistance RDSON of the power MOSFET, the higher the conduction loss. The higher the gate charge QG parameter, which has a large relationship with the capacitance between the gate and the drain, the higher the switching time of the power MOSFET, and finally the higher the switching loss of the power MOSFET.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a trench gate and a method for manufacturing a trench gate power device, which are used to solve the problem of poor quality factor caused by large capacitance between the gate and the drain of the power MOSFET in the prior art.
In order to achieve the above and other related objects, the present invention provides a method for manufacturing a trench gate, the method comprising: 1) Providing a substrate, and forming a groove in the substrate; 2) Forming a non-conformal liner layer in the trench covering the upper portion of the trench, exposing the lower portion and the bottom of the trench; 3) Forming a first gate dielectric layer at the lower part and the bottom of the exposed groove; 4) Removing the non-conformal liner layer to expose the upper part of the groove; 5) Forming a second gate dielectric layer on the upper part of the exposed groove, wherein the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer; 6) And filling the gate layer in the groove.
Optionally, step 2) forms a non-conformal liner layer in the trench covering an upper portion of the trench by using an atomic layer deposition method.
Optionally, the non-conformal liner layer has a thickness in a range from 5 angstroms to 200 angstroms.
Optionally, the material of the non-conformal liner layer comprises TaN, tiN, al 2 O 3 、ZrO 2 、Y 2 O 3 And HfO 2 One kind of (1).
Optionally, step 4) employs H 3 PO 4 The solution removes the non-conformal liner layer.
Optionally, in the step 5), in the process of forming the second gate dielectric layer on the exposed upper portion of the trench, the thickness of the first gate dielectric layer is increased at the same time.
Optionally, the thickness of the first gate dielectric layer is not less than 2 times the thickness of the second gate dielectric layer.
Optionally, the material of the first gate dielectric layer and the second gate dielectric layer includes silicon dioxide.
Optionally, the preparation process of the first gate dielectric layer and the second gate dielectric layer includes one of a dry oxygen oxidation process, a wet oxygen oxidation process, an in-situ water vapor oxidation process, and atomic layer deposition.
Optionally, the dry oxygen oxidation process, wet oxygenThe oxidizing atmosphere of the chemical process and the in-situ water gas oxidation process comprises H 2 、N 2 And NO.
Optionally, the material of the first gate dielectric layer and the second gate dielectric layer includes a high-k dielectric layer, and the preparation process of the high-k dielectric layer includes one of a chemical vapor deposition process and an atomic layer deposition process.
Optionally, the material of the high-k dielectric layer comprises HFO 2 、Al 2 O 3 And AlN.
Optionally, the material of the gate layer includes polysilicon, and the step 6) of filling the gate layer in the trench includes one of a furnace process and a single wafer process.
Optionally, after forming the trench in the substrate in step 1), the method further includes: and carrying out thermal oxidation on the groove to form a thermal oxidation layer, and removing the thermal oxidation layer by a wet method so as to enable the top angle and the bottom angle of the groove to realize the round angle.
The invention also provides a manufacturing method of the trench gate power device, which comprises the following steps: 1) Providing an N + type substrate, wherein an N-type epitaxial layer is formed on the N + type substrate; 2) Forming a P-well region and a P + well region in the N-type epitaxial layer, wherein the P + well region is positioned in the P-well region; 3) Manufacturing a trench gate in the N-type epitaxial layer and the P-type well region by adopting the manufacturing method of the trench gate; 4) Forming N + type source regions on two sides of the trench gate, wherein the N + type source regions cross over the P + well region and are positioned in the P-well region; 5) And manufacturing a source electrode on the N + type source region, and manufacturing a drain electrode on the back of the N + type substrate.
Optionally, a bottom end of the first gate layer is lower than a bottom end of the P-type well region.
As described above, the trench gate and the method for manufacturing the trench gate power device of the present invention have the following advantages:
the invention provides a manufacturing method of a trench gate power device, which is characterized in that gate dielectric layers in a trench are respectively prepared through a non-conformal liner, the thickness of a first gate dielectric layer at the lower part of the trench is firstly controlled through oxidation or atomic layer deposition, and the thickness of the first gate dielectric layer can be simultaneously increased when a second gate dielectric layer at the upper part of the trench is deposited, so that the capacitance between a gate and a drain can be effectively reduced, the QG parameter of gate charges is obviously reduced, and the quality factor of the power device is greatly optimized. Meanwhile, the second gate dielectric on the upper part of the groove is controlled to be smaller in thickness, so that the threshold voltage of the power device can be effectively reduced, and the control capability of the gate electrode is improved.
Drawings
Fig. 1 to 8 are schematic structural diagrams showing steps of a method for manufacturing a trench gate according to the present invention.
Fig. 9 is a schematic structural diagram finally presented in the manufacturing method of the trench gate power device of the present invention.
Description of the element reference
101 N + type substrate
102 N-type epitaxial layer
103. Groove
104. Non-conformal liner layer
105. First gate dielectric layer
106. Second gate dielectric layer
107. Gate layer
108 P-well region
109 P + well region
110 N + type source region
111. Source electrode
112. Drain electrode
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example 1
As shown in fig. 1 to fig. 8, the present embodiment provides a method for manufacturing a trench gate, where the method includes:
as shown in fig. 1-2, step 1) is performed first, a substrate is provided, and a trench 103 is formed in the substrate.
The base may be a semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, or the like, and in this embodiment, the base is a silicon substrate, which may include an N + type substrate 101 and an N-type epitaxial layer 102.
For example, a photolithography process and an etching process may be used to form a trench 103 in the substrate, and the depth of the trench 103 is not greater than the thickness of the N-type epitaxial layer 102, so that the bottom of the trench 103 has a distance from the N + -type substrate 101. In this embodiment, the N + type substrate 101 may serve as a drain region of a device.
Then, the method can further comprise the following steps: the trench 103 is thermally oxidized to form a thermal oxide layer, and the thermal oxide layer is removed by a wet method, so that the top angle and the bottom angle of the trench 103 are rounded, the steps can effectively avoid the effects of point discharge and the like of the device, simultaneously improve the defects of the surface of the trench 103 caused by etching, and improve the breakdown voltage of the device.
As shown in fig. 3, step 2) is then performed to form a non-conformal liner layer 104 in the trench 103 covering an upper portion of the trench 103, exposing a lower portion and a bottom portion of the trench 103.
For example, a non-conformal liner layer 104 is preferably formed in the trench 103 by atomic layer deposition, covering an upper portion of the trench 103, wherein the non-conformal liner layer 104 is used for blocking the growth of a gate dielectric layer in a subsequent covering region. The non-conformal liner layer 104 has a thickness in a range from 5 angstroms to 200 angstroms. The non-conformal liner layer 104 comprises TaN, tiN, al 2 O 3 、ZrO 2 、Y 2 O 3 And HfO 2 To (3) is provided. In this embodiment, the material of the non-conformal liner layer 104 is selected to be Al 2 O 3 To facilitate subsequent removal.
As an example, the height of the non-conformal liner layer 104 at the sidewalls of the trench 103 may be between one quarter and three quarters of the height of the trench 103.
As shown in fig. 4, step 3) is performed to form a first gate dielectric layer 105 on the exposed lower portion and bottom of the trench 103.
In one embodiment, the material of the first gate dielectric layer 105 may be silicon dioxide. The first isThe preparation process of the gate dielectric layer 105 includes one of a dry oxygen oxidation process, a wet oxygen oxidation process, an in-situ water vapor oxidation process and atomic layer deposition. Wherein the oxidizing atmosphere of the dry oxygen oxidation process, the wet oxygen oxidation process and the in-situ water-gas oxidation process comprises H 2 、N 2 And NO. The non-conformal liner layer 104 may prevent the sidewalls of the trench 103 in the region covered by the non-conformal liner layer from contacting oxygen, thereby inhibiting the growth of silicon dioxide in the region. The growth thickness of the silicon dioxide at the lower part and the bottom of the exposed trench 103 can be controlled by parameters such as oxidation time, oxidation atmosphere, and oxidation temperature.
In order to further optimize the capacitance value of the gate dielectric layer, the material of the first gate dielectric layer 105 may also be a high-k dielectric layer, and the preparation process of the high-k dielectric layer includes one of a chemical vapor deposition process and an atomic layer deposition process. In this embodiment, the material of the high-k dielectric layer includes HFO 2 、Al 2 O 3 And AlN. Wherein the non-conformal liner layer 104 may prevent deposition of a high-k dielectric layer on the sidewalls of the trench 103 in the area covered by the non-conformal liner layer. The thickness of the exposed high-k dielectric layer at the lower part and the bottom of the trench 103 can be controlled by controlling the process conditions of the chemical vapor deposition process and the atomic layer deposition process.
As shown in fig. 5, step 4) is then performed to remove the non-conformal liner layer 104 and expose an upper portion of the trench 103.
As an example, in removing the non-conformal liner layer 104, the etching liquid used has a high selectivity ratio of the non-conformal liner layer 104 to the first gate dielectric layer 105, such as no less than 10, preferably no less than 50, for example, in this embodiment, H 3 PO 4 The solution removes the non-conformal liner layer 104.
As shown in fig. 6, step 5) is performed to form a second gate dielectric layer 106 on the exposed upper portion of the trench 103, wherein the thickness of the second gate dielectric layer 106 is smaller than that of the first gate dielectric layer 105,
in one embodiment, the material of the second gate dielectric layer 106 may beAs silicon dioxide. The preparation process of the second gate dielectric layer 106 includes one of a dry oxidation process, a wet oxidation process, an in-situ water-gas oxidation process and atomic layer deposition. Wherein the oxidizing atmosphere of the dry oxygen oxidation process, the wet oxygen oxidation process and the in-situ water-gas oxidation process comprises H 2 、N 2 And NO. The growth thickness of the silicon dioxide on the upper portion of the exposed trench 103 can be controlled by parameters such as oxidation time, oxidation atmosphere, and oxidation temperature.
In order to further optimize the capacitance value of the gate dielectric layer, the material of the second gate dielectric layer 106 may also be a high-k dielectric layer, and the preparation process of the high-k dielectric layer includes one of a chemical vapor deposition process and an atomic layer deposition process. In this embodiment, the material of the high-k dielectric layer includes HFO 2 、Al 2 O 3 And AlN. The thickness of the high-k dielectric layer deposited on the exposed upper portion of the trench 103 can be controlled by controlling the process conditions of the chemical vapor deposition process and the atomic layer deposition process.
In the present embodiment, during the process of forming the second gate dielectric layer 106 on the exposed upper portion of the trench 103, the thickness of the first gate dielectric layer 105 is increased, for example, the exposed lower portion and bottom portion of the trench 103 are continuously oxidized to form silicon dioxide or a high-k dielectric layer is continuously deposited on the exposed lower portion and bottom portion of the trench 103. Preferably, the thickness of the first gate dielectric layer 105 is not less than 2 times of the thickness of the second gate dielectric layer 106, so that the capacitance between the gate and the drain is effectively reduced, the gate charge QG parameter is obviously reduced, and the quality factor of the power device is greatly optimized. Meanwhile, the second gate dielectric on the upper part of the trench 103 is controlled to be smaller in thickness, so that the threshold voltage of the power device can be effectively reduced, and the control capability of the gate can be improved.
As shown in fig. 7 to 8, step 6) is finally performed to fill the trench 103 with the gate layer 107, and the gate layer 107 with excessive surface is removed by a grinding process, such as a chemical mechanical polishing process CMP, to obtain a planar surface.
For example, the material of the gate layer 107 includes polysilicon, and the process of filling the gate layer 107 in the trench 103 in step 6) includes one of a furnace process and a single wafer process.
Example 2
As shown in fig. 1 to fig. 9, the present embodiment provides a method for manufacturing a trench gate power device, including the steps of:
step 1), providing an N + type substrate 101, wherein an N-type epitaxial layer 102 is formed on the N + type substrate 101.
And step 2), forming a P-well region 108 and a P + well region 109 in the N-type epitaxial layer 102, wherein the P + well region 109 is located in the P-well region 108.
And step 3), with the N + type substrate 101 and the N-type epitaxial layer 102 as substrates, manufacturing trench gates in the N-type epitaxial layer 102 and the P-type well region by using the method for manufacturing trench gates according to embodiment 1. Wherein the bottom end of the first gate layer 107 is lower than the bottom end of the P-type well region.
And 4), forming N + type source regions 110 on two sides of the trench gate, wherein the N + type source regions 110 cross over the P + well region 109 and are positioned in the P-well region 108.
And 5), manufacturing a source electrode 111 on the N + type source region 110, and manufacturing a drain electrode 112 on the back surface of the N + type substrate 101.
According to the embodiment, the gate dielectric layers in the grooves are respectively prepared through the non-conformal liner, the thickness of the first gate dielectric layer at the lower part of the groove is firstly controlled through oxidation or atomic layer deposition, and the thickness of the first gate dielectric layer can be increased simultaneously when the second gate dielectric layer at the upper part of the groove is deposited, so that the capacitance between the grid and the drain can be effectively reduced, the QG parameter of the grid charge is obviously reduced, and the quality factor of the power device is greatly optimized. Meanwhile, the second gate dielectric on the upper part of the groove is controlled to be smaller in thickness, so that the threshold voltage of the power device can be effectively reduced, and the control capability of the gate electrode is improved.
As described above, the trench gate and the method for manufacturing the trench gate power device of the present invention have the following advantages:
the invention provides a manufacturing method of a trench gate power device, which is characterized in that gate dielectric layers in trenches are respectively prepared through a non-conformal liner, the thickness of a first gate dielectric layer 105 at the lower part of the trench is firstly controlled through oxidation or atomic layer deposition, and the thickness of the first gate dielectric layer 105 can be simultaneously increased when a second gate dielectric layer 106 at the upper part of the trench is deposited, so that the capacitance between a gate and a drain can be effectively reduced, the QG parameter of gate charge is obviously reduced, and the quality factor of the power device is greatly optimized. Meanwhile, the second gate dielectric on the upper part of the groove is controlled to be smaller in thickness, so that the threshold voltage of the power device can be effectively reduced, and the control capability of the gate electrode is improved.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims (10)

1. A manufacturing method of a trench gate is characterized by comprising the following steps:
1) Providing a substrate, and forming a groove in the substrate;
2) Forming a non-conformal liner layer in the trench covering the upper portion of the trench, exposing the lower portion and the bottom of the trench;
3) Forming a first gate dielectric layer at the lower part and the bottom of the exposed groove;
4) Removing the non-conformal liner layer to expose the upper part of the groove;
5) Forming a second gate dielectric layer on the upper part of the exposed groove, wherein the thickness of the second gate dielectric layer is smaller than that of the first gate dielectric layer, the materials of the first gate dielectric layer and the second gate dielectric layer comprise high-k dielectric layers, the preparation process of the high-k dielectric layers comprises one of a chemical vapor deposition process and an atomic layer deposition process, the thickness of the first gate dielectric layer is increased simultaneously in the process of forming the second gate dielectric layer on the upper part of the exposed groove, and the thickness of the first gate dielectric layer is not smaller than 2 times of that of the second gate dielectric layer;
6) And filling the gate layer in the groove.
2. The method for manufacturing a trench gate according to claim 1, wherein: and 2) forming a non-conformal liner layer covering the upper part of the groove in the groove by adopting an atomic layer deposition method.
3. The method of claim 1, wherein: the thickness of the non-conformal liner layer ranges from 5 angstroms to 200 angstroms.
4. The method for manufacturing a trench gate according to claim 1, wherein: the non-conformal liner layer is made of TaN, tiN or Al 2 O 3 、ZrO 2 、Y 2 O 3 And HfO 2 One kind of (1).
5. The method for manufacturing the trench gate according to claim 4, wherein: step 4) with H 3 PO 4 The solution removes the non-conformal liner layer.
6. The method for manufacturing a trench gate according to claim 1, wherein: the material of the high-k dielectric layer comprises HFO 2 、Al 2 O 3 And AlN.
7. The method of claim 1, wherein: the material of the gate layer comprises polycrystalline silicon, and the process of filling the gate layer in the groove in the step 6) comprises one of a furnace tube process and a single wafer process.
8. The method for manufacturing a trench gate according to claim 1, wherein: step 1) after forming a trench in the substrate, further comprising the steps of: and carrying out thermal oxidation on the groove to form a thermal oxidation layer, and removing the thermal oxidation layer by a wet method so as to enable the top angle and the bottom angle of the groove to realize the round angle.
9. A manufacturing method of a trench gate power device is characterized by comprising the following steps:
1) Providing an N + type substrate, wherein an N-type epitaxial layer is formed on the N + type substrate;
2) Forming a P-type well region and a P + type well region in the N-type epitaxial layer, wherein the P + type well region is positioned in the P-type well region;
3) Manufacturing a trench gate in the N-type epitaxial layer and the P-type well region by adopting the manufacturing method of the trench gate according to any one of claims 1 to 8;
4) Forming N + type source regions on two sides of the trench gate, wherein the N + type source regions cross over the P + type well region and are positioned in the P-type well region;
5) And manufacturing a source electrode on the N + type source region, and manufacturing a drain electrode on the back of the N + type substrate.
10. The method of claim 9, wherein: the bottom end of the grid layer is lower than the bottom end of the P-type well region.
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