CN115831844A - Wafer alignment method and alignment device - Google Patents
Wafer alignment method and alignment device Download PDFInfo
- Publication number
- CN115831844A CN115831844A CN202211485561.6A CN202211485561A CN115831844A CN 115831844 A CN115831844 A CN 115831844A CN 202211485561 A CN202211485561 A CN 202211485561A CN 115831844 A CN115831844 A CN 115831844A
- Authority
- CN
- China
- Prior art keywords
- wafer
- alignment
- mark
- objective lens
- coaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention belongs to the technical field of chip manufacturing, and particularly relates to a wafer alignment method and an alignment device. The wafer alignment method of the invention comprises the following steps: step 1: respectively arranging alignment marks on the back of the upper wafer and the back of the lower wafer; step 2: enabling the back surface of the upper wafer to face upwards and the back surface of the lower wafer to face downwards, and then moving the upper wafer and the lower wafer to an alignment station until the alignment mark of the upper wafer and the alignment mark of the lower wafer are both in the field range of the visual identification system; and step 3: identifying the alignment mark of the upper wafer through an upper objective lens of a visual identification system, and identifying the alignment mark of the lower wafer through a lower objective lens of the visual identification system to obtain the position deviation between the alignment mark of the upper wafer and the alignment mark of the lower wafer; and 4, step 4: a fine alignment operation between the upper wafer and the lower wafer is performed based on the positional deviation. The invention can eliminate the alignment error caused by the link of moving the lower wafer out and then moving the lower wafer in, and improve the alignment precision.
Description
Technical Field
The invention belongs to the technical field of chip manufacturing, and particularly relates to a wafer alignment method and an alignment device.
Background
The three-dimensional integrated wafer stacking technology is developed aiming at the current technology of backside-illuminated CIS chips and 3D memory chips, and is an optimal scheme for solving the bottleneck problem of interconnection leads. Alignment is one of the most important process steps in the three-dimensional integrated wafer stacking process, and directly determines the degree of wafer bonding accuracy.
The basic principle of alignment is: after the surfaces of the two wafers are respectively treated, the Mark marks at the appointed positions on the two wafers are identified and positioned through a precise optical system, and then the two wafers are aligned in space through various adjusting mechanisms. The aligned wafer pair can be subjected to a subsequent bonding process, thereby completing the three-dimensional integrated wafer stacking process.
In the prior art, the alignment marks of the upper wafer and the lower wafer are processed on the front surface of the wafer, and the alignment process of the upper wafer and the lower wafer includes the following 5 steps:
(1) And at the alignment station, the front surface of the upper wafer faces downwards, the front surface of the lower wafer faces upwards, the alignment Mark of the upper wafer and the alignment Mark of the lower wafer are arranged oppositely up and down, and the upper wafer and the lower wafer are staggered in the vertical direction, so that a visual recognition system can recognize single wafer alignment marks independently.
(2) And moving the vision recognition system until the upper objective lens of the vision recognition system recognizes the central coordinates of the two alignment marks on the front surface of the lower wafer, fixing the vision recognition system at the position, and taking the position of the lower wafer as the initial recognition position of the lower wafer at the moment.
(3) And moving the lower wafer out of the field range of the vision recognition system, and then moving the upper wafer into the field range of the vision recognition system, so that the lower objective of the vision recognition system recognizes the central coordinates of the two alignment marks on the front surface of the upper wafer.
(4) And returning the lower wafer to the initial identification position, so that the alignment mark of the upper wafer and the alignment mark of the lower wafer are overlapped in the vertical direction.
(5) And (5) recording the position deviation generated in the steps (1) to (4) by the displacement control system, calculating a position compensation value, and controlling the precision displacement system to drive the lower wafer to finish the precision alignment with the upper wafer according to the current central coordinate deviation of the upper wafer and the lower wafer.
The prior art mainly has the following defects:
in the alignment process of the prior art, the center coordinates of the alignment marks of the lower wafer are identified in the steps (3) to (4), then the center coordinates are moved out and moved into the field range of the vision identification system again, so that intermediate errors are introduced, and the displacement control system cannot accurately measure and compensate all the intermediate errors. Therefore, the alignment mark of the lower wafer cannot return to the original position accurately, which has adverse effect on the alignment precision;
the prior art wafer alignment is an indirect "blind" alignment. After the upper wafer and the lower wafer are aligned and overlapped, the alignment marks of the upper wafer and the lower wafer cannot be captured in real time by the vision recognition system, and the alignment effect completely depends on historical experience data and position compensation values of central coordinates of the alignment marks which are recognized by the vision system independently, so that the central coordinate error of the alignment marks between the upper wafer and the lower wafer after the alignment process is completed cannot be mastered in real time, and the alignment process cannot be intervened and adjusted in time. Therefore, the alignment precision before the bonding process cannot be directly detected and verified, the detection can only be carried out after the bonding process is completed, the alignment error at the moment is the superposition error of the alignment process and the bonding process, the alignment precision is poor, and the qualified rate of bonded wafers is influenced. Meanwhile, the alignment process is executed again after the wafers which are not qualified after verification need to be debonded, so that the wafer processing efficiency is reduced, and in addition, the risk of wafer fragmentation is caused due to poor debonding process.
Disclosure of Invention
The invention provides a wafer alignment method and an alignment device, which are used for eliminating alignment errors caused by the fact that a lower wafer moves out and then moves a visual identification system, so that the technical problem of poor alignment precision of the existing alignment method is solved, the position deviation between alignment marks of an upper wafer and a lower wafer can be analyzed and adjusted in an intervening mode in real time, accurate assessment of the alignment precision before a bonding process is realized, and the wafer bonding processing efficiency is effectively improved.
The wafer alignment method of the invention comprises the following steps:
step 1: respectively arranging alignment marks on the back surface of the upper wafer and the back surface of the lower wafer;
step 2: enabling the back surface of the upper wafer to face upwards and the back surface of the lower wafer to face downwards, and then moving the upper wafer and the lower wafer to an alignment station until the alignment mark of the upper wafer and the alignment mark of the lower wafer are both in the field range of a visual identification system;
and step 3: identifying the alignment mark of the upper wafer through an upper objective lens of the visual identification system, and identifying the alignment mark of the lower wafer through a lower objective lens of the visual identification system to obtain the position deviation between the alignment mark of the upper wafer and the alignment mark of the lower wafer;
and 4, step 4: performing a fine alignment operation between the upper wafer and the lower wafer based on the positional deviation.
In one embodiment, step 2 comprises the following sub-steps:
step 21: moving the lower wafer to a preset position of the alignment station, adjusting the position of the visual recognition system until the lower objective lens recognizes the alignment mark of the lower wafer, and locking the positions of the visual recognition system and the lower wafer;
step 22: and moving the upper wafer to the upper part of the lower wafer, and adjusting the position of the upper wafer until the upper objective lens identifies the alignment mark of the upper wafer.
In one embodiment, in step 21, the preset position is a bonding position of the lower wafer.
In one embodiment, step 4 comprises the following sub-steps:
step 41: judging whether the position deviation acquired in the step 3 is within a preset deviation range,
if yes, judging that the fine alignment of the upper wafer and the lower wafer is finished, entering a bonding procedure,
if not, executing step 42 and step 43 in sequence;
step 42: performing one-time fine adjustment on the position and the posture of the upper wafer based on the position deviation, and recording the current times of performing the fine adjustment;
step 43: judging whether the current times of fine adjustment exceed the preset times,
if so, controlling the upper wafer and the lower wafer to exit from the alignment station so as to finish the alignment process;
if not, returning to execute the operation of the step 3.
In one embodiment, the fine adjustment of the position and orientation of the upper wafer based on the position deviation comprises:
and calculating a fine adjustment compensation value according to the position deviation, and performing fine adjustment on the position posture of the upper wafer according to the calculated fine adjustment compensation value so as to realize fine alignment of the upper wafer and the lower wafer.
In one embodiment, step 1 is preceded by the step of calculating a misalignment of the coaxiality between a lower objective lens and an upper objective lens of the vision recognition system:
step 0: enabling the upper objective lens to identify a first coaxial calibration mark on the top surface of the coaxial calibration device, and enabling the lower objective lens to identify a second coaxial calibration mark on the bottom surface of the coaxial calibration device so as to calculate the coaxiality deviation between the lower objective lens and the upper objective lens;
the first coaxial verification mark and the second coaxial verification mark are located on the same vertical straight line.
In one embodiment, step 3 further comprises: correcting the acquired positional deviation according to the coaxiality deviation between the lower objective lens and the upper objective lens calculated in step 0,
in step 4, a fine alignment operation between the upper wafer and the lower wafer is performed based on the corrected positional deviation.
In one embodiment, the axial thickness of the coaxial proof device is consistent with the distance between the top surface of the upper wafer and the bottom surface of the lower wafer during bonding.
In one embodiment, the coaxial verification device is made of a light-impermeable material.
The invention also provides an alignment device for realizing the wafer alignment method, which comprises the following steps:
a vision recognition system including a lower objective lens for recognizing an alignment mark of a lower wafer and an upper objective lens for recognizing an alignment mark of an upper wafer;
the lower wafer movement system is used for driving the lower wafer to move and comprises an upper wafer chuck for bearing the lower wafer, and the lower wafer chuck is provided with a first observation notch corresponding to the alignment mark position of the lower wafer so that the lower objective lens can identify the alignment mark of the lower wafer through the first observation notch;
the upper wafer movement system is used for driving an upper wafer to move and comprises an upper wafer chuck for bearing the upper wafer, and the upper wafer chuck is provided with a second observation notch corresponding to the alignment mark position of the upper wafer, so that the upper objective lens can identify the alignment mark of the upper wafer through the second observation notch;
the displacement control system is respectively connected with the visual identification system, the upper wafer movement system and the lower wafer movement system so as to control the visual identification system, the upper wafer movement system and the lower wafer movement system to execute corresponding operations; and
the coaxial checking device is used for obtaining the coaxiality deviation between a lower objective lens and an upper objective lens of the visual recognition system, a first coaxial checking mark is arranged on the top surface of the coaxial checking device, a second coaxial checking mark is arranged on the bottom surface of the coaxial checking device, the first coaxial checking mark and the second coaxial checking mark are located on the same vertical straight line, and the axial thickness of the coaxial checking device is consistent with the distance between the top surface of the upper wafer and the bottom surface of the lower wafer during bonding.
Compared with the prior art, the invention has the advantages that: in the invention, the alignment marks are arranged on the back surfaces of the upper wafer and the lower wafer, so that the vision recognition system does not need to move one wafer out of the field range of view to recognize the alignment mark of the other wafer, thereby eliminating the alignment error caused by the link of moving the lower wafer out and then in, and improving the alignment precision. Meanwhile, the visual recognition system can capture the alignment marks of the upper wafer and the lower wafer simultaneously, so that the position deviation between the alignment marks of the upper wafer and the lower wafer is analyzed and adjusted in an intervening manner in real time, accurate assessment of the alignment precision before the bonding process is realized, the qualification rate of the bonded wafer and the processing efficiency of wafer bonding are effectively improved, the risk of wafer fragmentation caused by poor bonding process is reduced, and remarkable economic benefits are achieved.
Drawings
The invention will be described in more detail hereinafter on the basis of embodiments and with reference to the accompanying drawings.
FIG. 1 is a flow chart of a wafer alignment method of one embodiment of the present invention;
FIG. 2 is a flow chart of a wafer alignment method according to another embodiment of the present invention;
FIG. 3 is a sub-flow diagram of step 2 of one embodiment of the present invention;
FIG. 4 is a sub-flow diagram of step 4 of one embodiment of the present invention;
fig. 5A-5D are process diagrams illustrating an alignment method performed by an alignment apparatus according to an embodiment of the present invention.
Reference numerals:
1. loading a wafer; 2. a lower wafer; 3. an upper objective lens; 4. a lower objective lens; 5. a coaxial calibration device;
6. an upper wafer chuck; 7. A lower wafer chuck;
11. a first mark of the upper wafer is marked; 12. A second mark of the upper wafer is marked;
21. a first mark of a lower wafer; 22. A second mark of the lower wafer;
51. a first coaxial verification mark; 52. a second coaxial verification mark.
Detailed Description
The invention will be further explained with reference to the drawings.
As shown in fig. 1, the wafer alignment method of the present invention includes the steps of:
step 1: alignment marks are provided on the back surface of the upper wafer 1 and the back surface of the lower wafer 2, respectively.
Step 2: the back surface of the upper wafer 1 faces upwards, the back surface of the lower wafer 2 faces downwards, and then the upper wafer 1 and the lower wafer 2 are moved to an alignment station until the alignment marks of the upper wafer 1 and the alignment marks of the lower wafer 2 are within the visual field range of the visual recognition system.
And step 3: the alignment mark of the upper wafer 1 is recognized by the upper objective lens 3 of the vision recognition system, and the alignment mark of the lower wafer 2 is recognized by the lower objective lens 4 of the vision recognition system, so as to obtain the position deviation between the alignment mark of the upper wafer 1 and the alignment mark of the lower wafer 2.
And 4, step 4: a fine alignment operation between the upper wafer 1 and the lower wafer 2 is performed based on the positional deviation.
In the invention, the alignment marks are arranged on the back surfaces of the upper wafer 1 and the lower wafer 2, so that a vision recognition system does not need to move one wafer out of the field range of view to recognize the alignment mark of the other wafer, thereby eliminating the alignment error caused by the link of moving the lower wafer 2 out and then in, and improving the alignment precision.
Meanwhile, the visual recognition system can capture the alignment marks of the upper wafer 1 and the lower wafer 2 at the same time, so that the position deviation between the alignment marks of the upper wafer 1 and the lower wafer 2 is analyzed and intervened and adjusted in real time, accurate assessment of alignment precision before the bonding process is realized, the qualification rate of the bonded wafer and the processing efficiency of wafer bonding are effectively improved, the risk of wafer fragmentation caused by poor bonding process resolution is reduced, and remarkable economic benefits are achieved.
The positional deviation may be a coordinate positional deviation of a cartesian coordinate system.
Step 1: alignment marks are provided on the back surface of the upper wafer 1 and the back surface of the lower wafer 2, respectively.
The front surface of the upper wafer 1 is opposite to the front surface of the lower wafer 2 to realize bonding, and the back surface of the upper wafer 1 and the back surface of the lower wafer 2 respectively adopt the existing wafer etching process to etch the alignment marks.
Specifically, the alignment marks of the upper wafer 1 include an upper wafer first mark 11 and an upper wafer second mark 12 which are disposed on the same scribe lane passing through the center of the wafer and have the same distance to the center of the wafer. The alignment mark of the lower wafer 2 includes a first lower wafer mark 21 and a second lower wafer mark 22 disposed on the same scribe lane passing through the center of the wafer and having the same distance to the center of the wafer. During wafer alignment, the upper wafer first mark 11 is aligned with the lower wafer first mark 21, and the upper wafer second mark 12 is aligned with the lower wafer second mark 22.
Step 2: the back surface of the upper wafer 1 faces upwards, the back surface of the lower wafer 2 faces downwards, and then the upper wafer 1 and the lower wafer 2 are moved to an alignment station until the alignment mark of the upper wafer 1 and the alignment mark of the lower wafer 2 are both within the field range of the vision recognition system.
And step 2 is a coarse alignment step of the upper wafer 1 and the lower wafer 2, wherein the upper wafer 1 and the lower wafer 2 are both moved to an alignment station, and after the alignment marks of the upper wafer 1 and the lower wafer 2 are identified by a visual identification system, the coarse alignment of the upper wafer 1 and the lower wafer 2 is realized.
Specifically, as shown in fig. 3, step 2 comprises the following sub-steps:
step 21: and moving the lower wafer 2 to a preset position of the alignment station, adjusting the position of the vision recognition system until the lower objective lens 4 recognizes the alignment mark of the lower wafer 2, and locking the vision recognition system and the position of the lower wafer 2.
Step 22: the upper wafer 1 is moved to the upper side of the lower wafer 2, and the position of the upper wafer 1 is adjusted until the upper objective lens 3 recognizes the alignment mark of the upper wafer 1.
The upper objective 3 of the vision recognition system recognizes the alignment mark of the upper wafer 1, and the lower objective 4 recognizes the alignment mark of the lower wafer 2. After the lower wafer 2 moves to the preset position of the alignment station, the alignment mark of the lower wafer is used as a reference point, after the lower objective lens 4 identifies the alignment mark of the lower wafer 2, the position of the visual identification system is locked and does not move any more, and then the coarse alignment of the upper wafer 1 and the lower wafer 2 is completed by adjusting the position of the upper wafer 1 until the upper objective lens 3 identifies the alignment mark of the upper wafer 1, so that the accuracy and the efficiency of the coarse alignment can be improved by the alignment mode of the single reference point.
Preferably, in step 21, the preset position is a bonding position of the lower wafer 2. In the alignment procedure, the lower wafer 2 is locked and does not move after moving to the bonding position, and after the alignment procedure is completed, the bonding procedure can be directly started, so that errors caused by links of moving the aligned upper wafer 1 and the aligned lower wafer 2 are avoided, and the alignment accuracy of the upper wafer 1 and the lower wafer 2 during bonding is ensured.
And step 3: the alignment mark of the upper wafer 1 is recognized by the upper objective lens 3 of the vision recognition system, and the alignment mark of the lower wafer 2 is recognized by the lower objective lens 4 of the vision recognition system, so as to obtain the position deviation between the alignment mark of the upper wafer 1 and the alignment mark of the lower wafer 2.
In step 3, the upper wafer 1 and the lower wafer 2 are aligned and overlapped after coarse alignment, and the vision recognition system can simultaneously recognize the alignment mark of the upper wafer 1 and the alignment mark of the lower wafer 2 through the upper objective lens 3 and the lower objective lens 4, so as to obtain the position deviation between the upper wafer 1 and the lower wafer 2 in real time.
And 4, step 4: a fine alignment operation between the upper wafer 1 and the lower wafer 2 is performed based on the positional deviation.
In step 4, the position deviation between the alignment marks of the upper wafer 1 and the lower wafer 2 is analyzed and adjusted in an intervening manner in real time, so that the alignment precision is improved, and the accurate assessment of the alignment precision before the bonding process is realized.
Specifically, as shown in fig. 4, step 4 comprises the following sub-steps:
step 41: judging whether the position deviation acquired in the step 3 is within a preset deviation range,
if yes, the fine alignment of the upper wafer 1 and the lower wafer 2 is determined to be completed, and the bonding process is performed,
if not, step 42 and step 43 are executed in sequence.
Step 42: and performing one-time fine adjustment on the position and the posture of the upper wafer 1 based on the position deviation, and recording the current times of performing the fine adjustment.
Step 43: judging whether the current times of fine adjustment exceed the preset times,
if so, controlling the upper wafer 1 and the lower wafer 2 to exit from the alignment station so as to finish the alignment process; if not, returning to execute the operation of the step 3.
In this embodiment, when the positional deviation between the upper wafer 1 and the lower wafer 2 is within the ideal predetermined deviation range, the alignment process is completed, and the bonding process is started. If the number of fine adjustment times reaches a preset number of times (a preset upper limit value), and if the position deviation between the upper wafer 1 and the lower wafer 2 still does not converge within an ideal preset deviation range, the alignment procedure is stopped, the bonding procedure is not started, the upper wafer 1 and the lower wafer 2 exit from the alignment station, and a technician intervenes to analyze the cause of the problem.
Further specifically, performing one fine adjustment on the position and posture of the upper wafer 1 based on the position deviation includes: and calculating a fine adjustment compensation value according to the position deviation, and performing fine adjustment on the position posture of the upper wafer 1 according to the calculated fine adjustment compensation value so as to realize fine alignment of the upper wafer 1 and the lower wafer 2.
The position and posture of the upper wafer 1 includes the coordinate position and the parallelism of the upper wafer 1.
Step 0 is specifically described below.
The first coaxial verification mark 51 and the second coaxial verification mark 52 of the coaxial verification device 5 are located on the same vertical straight line.
In other words, in step 0, the deviation of the coaxiality between the upper objective lens 3 and the lower objective lens 4 is measured by the coaxiality checking device 5, thereby being eliminated or compensated for in the subsequent operation.
Specifically, as shown in fig. 2, step 3 further includes: the acquired positional deviation is corrected based on the coaxiality deviation between the lower objective lens 4 and the upper objective lens 3 calculated in step 0. In step 4, a fine alignment operation between the upper wafer 1 and the lower wafer 2 is performed based on the corrected positional deviation.
Preferably, the axial thickness of the coaxial verification means 5 is identical to the distance between the top surface of the upper wafer 1 and the bottom surface of the lower wafer 2 when bonded.
In particular, the coaxial verification means 5 are made of a light-impermeable material, so that the upper objective 3 cannot identify the second coaxial verification mark 52 of the bottom face of the coaxial verification means 5 through the coaxial verification means 5,
it should be noted that the first coaxial calibration mark 51 and the second coaxial calibration mark 52 of the coaxial calibration device 5 should use the same etching process as the alignment mark of the upper wafer 1 and the calibration mark of the lower wafer 2 to ensure the consistency of the plane position, the pattern type and the size.
As shown in fig. 5A to 5D, the present invention further provides an alignment apparatus for implementing the wafer alignment method, including: the system comprises a visual identification system, a lower wafer 2 motion system, an upper wafer 1 motion system, a displacement control system and a coaxial calibration device 5. The displacement control system is respectively connected with the visual identification system, the upper wafer 1 movement system and the lower wafer 2 movement system so as to control the visual identification system, the upper wafer 1 movement system and the lower wafer 2 movement system to execute corresponding operations, and therefore alignment of the upper wafer 1 and the lower wafer 2 is achieved.
Wherein the vision recognition system includes a lower objective lens 4 for recognizing the alignment mark of the lower wafer 2 and an upper objective lens 3 for recognizing the alignment mark of the upper wafer 1.
The lower wafer 2 moving system is used for driving the lower wafer 2 to move. The lower wafer 2 moving system includes a lower wafer chuck 7 for carrying the lower wafer 2, and the lower wafer chuck 7 is provided with a first viewing slot corresponding to the alignment mark position of the lower wafer 2, so that the lower objective lens 4 recognizes the alignment mark of the lower wafer 2 through the first viewing slot. Further, the lower wafer 2 movement system includes a lower movement stage on which the lower wafer chuck 7 is disposed.
The upper wafer 1 moving system is used for driving the upper wafer 1 to move. The upper wafer 1 moving system includes an upper wafer chuck 6 for carrying the upper wafer 1, and the upper wafer chuck 6 is provided with a second viewing slot corresponding to the alignment mark position of the upper wafer 1, so that the upper objective lens 3 recognizes the alignment mark of the upper wafer 1 through the second viewing slot. Further, the upper wafer 1 moving system includes a fine alignment adjusting device, such as a nano positioning moving table, and the upper wafer chuck 6 is disposed on the fine alignment adjusting device, so as to achieve fine adjustment of the position and posture of the upper wafer 1 through the fine alignment adjusting device.
The coaxial checking device 5 is used for obtaining the coaxiality deviation between the lower objective lens 4 and the upper objective lens 3 of the visual recognition system, a first coaxial checking mark 51 is arranged on the top surface of the coaxial checking device 5, a second coaxial checking mark 52 is arranged on the bottom surface of the coaxial checking device 5, the first coaxial checking mark 51 and the second coaxial checking mark 52 are located on the same vertical straight line, and the axial thickness of the coaxial checking device 5 is consistent with the distance between the top surface of the upper wafer 1 and the bottom surface of the lower wafer 2 during bonding.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; may be a mechanical connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The descriptions of "upper" and "lower" mentioned in the present invention are defined in a general sense, for example, with reference to the direction of gravity, the direction of gravity is lower, the opposite direction is upper, similarly, the upper is the top, and the lower is the bottom, which is also clear for the convenience of description, and not used to limit the scope of the invention, and the changes or modifications of the relative relationship thereof should be regarded as the scope of the invention without substantial changes in the technical content. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
While the invention has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In particular, the technical features mentioned in the embodiments can be combined in any way as long as there is no structural conflict. It is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (10)
1. A wafer alignment method, comprising the steps of:
step 1: respectively arranging alignment marks on the back of the upper wafer and the back of the lower wafer;
step 2: enabling the back surface of the upper wafer to face upwards and the back surface of the lower wafer to face downwards, and then moving the upper wafer and the lower wafer to an alignment station until the alignment mark of the upper wafer and the alignment mark of the lower wafer are both in the field range of a visual identification system;
and step 3: identifying the alignment mark of the upper wafer through an upper objective lens of the visual identification system, and identifying the alignment mark of the lower wafer through a lower objective lens of the visual identification system to obtain the position deviation between the alignment mark of the upper wafer and the alignment mark of the lower wafer;
and 4, step 4: performing a fine alignment operation between the upper wafer and the lower wafer based on the positional deviation.
2. A wafer alignment method as claimed in claim 1, wherein the step 2 comprises the sub-steps of:
step 21: moving the lower wafer to a preset position of the alignment station, adjusting the position of the visual recognition system until the lower objective lens recognizes the alignment mark of the lower wafer, and locking the positions of the visual recognition system and the lower wafer;
step 22: and moving the upper wafer to the upper part of the lower wafer, and adjusting the position of the upper wafer until the upper objective lens identifies the alignment mark of the upper wafer.
3. The wafer alignment method as claimed in claim 2, wherein the predetermined position is a bonding position of the lower wafer in step 21.
4. A wafer alignment method as claimed in any one of claims 1 to 3, wherein step 4 comprises the sub-steps of:
step 41: judging whether the position deviation acquired in the step 3 is within a preset deviation range,
if yes, judging that the fine alignment of the upper wafer and the lower wafer is finished, entering a bonding procedure,
if not, sequentially executing the step 42 and the step 43;
step 42: performing one-time fine adjustment on the position and the posture of the upper wafer based on the position deviation, and recording the current times of performing the fine adjustment;
step 43: judging whether the current times of fine adjustment exceed the preset times,
if so, controlling the upper wafer and the lower wafer to exit from the alignment station so as to finish the alignment process;
if not, returning to execute the operation of the step 3.
5. The wafer alignment method as claimed in claim 4, wherein performing a fine adjustment of the position and orientation of the upper wafer based on the position deviation comprises:
and calculating a fine adjustment compensation value according to the position deviation, and performing fine adjustment on the position posture of the upper wafer according to the calculated fine adjustment compensation value so as to realize fine alignment of the upper wafer and the lower wafer.
6. A method as claimed in any one of claims 1 to 3, wherein step 1 is preceded by the step of calculating a misalignment of the coaxiality between the lower objective and the upper objective of the vision recognition system:
step 0: enabling the upper objective lens to identify a first coaxial calibration mark on the top surface of the coaxial calibration device, and enabling the lower objective lens to identify a second coaxial calibration mark on the bottom surface of the coaxial calibration device so as to obtain the coaxiality deviation between the lower objective lens and the upper objective lens;
the first coaxial verification mark and the second coaxial verification mark are located on the same vertical straight line.
7. The wafer alignment method as claimed in claim 6, wherein the step 3 further comprises: correcting the acquired position deviation according to the coaxiality deviation between the lower objective lens and the upper objective lens acquired in the step 0;
in step 4, a fine alignment operation between the upper wafer and the lower wafer is performed based on the corrected positional deviation.
8. The wafer alignment method as claimed in claim 6, wherein the coaxial verification device has an axial thickness corresponding to a distance between the top surface of the upper wafer and the bottom surface of the lower wafer during bonding.
9. The wafer alignment method as claimed in claim 6, wherein the coaxial verification device is made of an opaque material.
10. An alignment apparatus for implementing the wafer alignment method of any one of claims 1 to 9, comprising:
a vision recognition system including a lower objective lens for recognizing an alignment mark of a lower wafer and an upper objective lens for recognizing an alignment mark of an upper wafer;
the lower wafer movement system is used for driving the lower wafer to move and comprises a lower wafer chuck for bearing the lower wafer, and the lower wafer chuck is provided with a first observation notch corresponding to the alignment mark position of the lower wafer so that the lower objective lens can identify the alignment mark of the lower wafer through the first observation notch;
the upper wafer movement system is used for driving an upper wafer to move and comprises an upper wafer chuck for bearing the upper wafer, and the upper wafer chuck is provided with a second observation notch corresponding to the alignment mark position of the upper wafer, so that the upper objective lens can identify the alignment mark of the upper wafer through the second observation notch;
the displacement control system is respectively connected with the visual identification system, the upper wafer movement system and the lower wafer movement system so as to control the visual identification system, the upper wafer movement system and the lower wafer movement system to execute corresponding operations and realize the alignment of the upper wafer and the lower wafer; and
the coaxial checking device is used for obtaining the coaxiality deviation between a lower objective lens and an upper objective lens of the visual recognition system, a first coaxial checking mark is arranged on the top surface of the coaxial checking device, a second coaxial checking mark is arranged on the bottom surface of the coaxial checking device, the first coaxial checking mark and the second coaxial checking mark are located on the same vertical straight line, and the axial thickness of the coaxial checking device is consistent with the distance between the top surface of the upper wafer and the bottom surface of the lower wafer during bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211485561.6A CN115831844A (en) | 2022-11-24 | 2022-11-24 | Wafer alignment method and alignment device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211485561.6A CN115831844A (en) | 2022-11-24 | 2022-11-24 | Wafer alignment method and alignment device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115831844A true CN115831844A (en) | 2023-03-21 |
Family
ID=85531338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211485561.6A Pending CN115831844A (en) | 2022-11-24 | 2022-11-24 | Wafer alignment method and alignment device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115831844A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117080144A (en) * | 2023-10-16 | 2023-11-17 | 苏州芯慧联半导体科技有限公司 | High-precision wafer alignment device and method |
| CN117497475A (en) * | 2023-12-29 | 2024-02-02 | 迈为技术(珠海)有限公司 | Wafer alignment device and alignment method thereof |
| CN117497475B (en) * | 2023-12-29 | 2024-04-19 | 迈为技术(珠海)有限公司 | Wafer alignment device and alignment method thereof |
-
2022
- 2022-11-24 CN CN202211485561.6A patent/CN115831844A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117080144A (en) * | 2023-10-16 | 2023-11-17 | 苏州芯慧联半导体科技有限公司 | High-precision wafer alignment device and method |
| CN117080144B (en) * | 2023-10-16 | 2024-01-23 | 苏州芯慧联半导体科技有限公司 | High-precision wafer alignment device and method |
| CN117497475A (en) * | 2023-12-29 | 2024-02-02 | 迈为技术(珠海)有限公司 | Wafer alignment device and alignment method thereof |
| CN117497475B (en) * | 2023-12-29 | 2024-04-19 | 迈为技术(珠海)有限公司 | Wafer alignment device and alignment method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100619471B1 (en) | Bonding apparatus | |
| CN109906029B (en) | Electronic component mounting device and electronic component mounting method | |
| JPH04233245A (en) | System and method for inspection and alignment at semiconductor chip and conductor lead frame | |
| JP4768731B2 (en) | Flip chip mounting deviation inspection method and mounting apparatus | |
| JP4642565B2 (en) | Mounting method and mounting apparatus | |
| CN115831844A (en) | Wafer alignment method and alignment device | |
| CN105783710B (en) | A kind of method and device of location position | |
| KR100771496B1 (en) | Calibrating apparatus and method of marking for laser marking system | |
| US8100317B2 (en) | Method of teaching eyepoints for wire bonding and related semiconductor processing operations | |
| US11823938B2 (en) | Mounting device and mounting method | |
| CN112185870A (en) | High-precision bonding head positioning method and device | |
| CN108701678B (en) | Mark position correction device and method | |
| CN116759360B (en) | Wafer alignment device and lens error calibration method | |
| JP7293477B2 (en) | Mounting equipment | |
| CN115632018A (en) | Wafer alignment method and alignment device | |
| JP6600838B2 (en) | Alignment apparatus and alignment method | |
| CN112218517B (en) | Mounting device | |
| KR20220030454A (en) | Semiconductor substrate alignment device and semiconductor substrate bonding system using the same | |
| JP4264403B2 (en) | Bonding equipment | |
| JP2003077955A (en) | Bonding method and bonding apparatus | |
| JP7013400B2 (en) | Mounting device and mounting method | |
| JP4461714B2 (en) | Exposure shift measuring device | |
| KR102653108B1 (en) | Apparatus and method for aligniing a substrate | |
| JPH0435846A (en) | Positioning of semiconductor wafer | |
| JPH0766251A (en) | Ic chip positioning method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |