CN115831776A - Chip packaging method and packaging structure - Google Patents
Chip packaging method and packaging structure Download PDFInfo
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- CN115831776A CN115831776A CN202211612938.XA CN202211612938A CN115831776A CN 115831776 A CN115831776 A CN 115831776A CN 202211612938 A CN202211612938 A CN 202211612938A CN 115831776 A CN115831776 A CN 115831776A
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- 238000000034 method Methods 0.000 title claims abstract description 45
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- 239000000758 substrate Substances 0.000 claims abstract description 25
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 17
- 238000005520 cutting process Methods 0.000 claims abstract description 16
- 239000003292 glue Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000001259 photo etching Methods 0.000 claims abstract description 6
- 239000010931 gold Substances 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 238000004026 adhesive bonding Methods 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 6
- 238000005411 Van der Waals force Methods 0.000 claims description 4
- 238000002788 crimping Methods 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 4
- 238000003466 welding Methods 0.000 claims description 4
- 241000218202 Coptis Species 0.000 abstract description 4
- 235000002991 Coptis groenlandica Nutrition 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000005538 encapsulation Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 230000008569 process Effects 0.000 description 13
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- 230000001070 adhesive effect Effects 0.000 description 9
- SXHLTVKPNQVZGL-UHFFFAOYSA-N 1,2-dichloro-3-(3-chlorophenyl)benzene Chemical compound ClC1=CC=CC(C=2C(=C(Cl)C=CC=2)Cl)=C1 SXHLTVKPNQVZGL-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
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- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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- 238000006467 substitution reaction Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention belongs to the technical field of semiconductor manufacturing, and discloses a chip packaging method and a chip packaging structure. The chip packaging method comprises the following steps: s1, photoetching, namely photoetching on a glass sheet to form an etching area; s2, pasting, namely pasting a UV film on the lead pins of the wafer; s3, connecting, wherein the surface of the wafer is connected with the glass sheet at one side provided with the photosensitive area to form a bonding layer, and the photosensitive area and the UV film are opposite to the etching area; s4, cutting, namely cutting and removing the part of the glass sheet above the lead pin so as to expose the lead pin; s5, scribing, namely scribing the bonding layer into independent chip units; s6, removing the film, and removing the UV film from the lead pins; s7, wiring, wherein a gold wire is led out from the lead pin and is electrically connected with the substrate; and S8, plastic packaging, wherein plastic packaging glue is coated along the periphery of the chip unit. By the invention, the packaging difficulty of the chip is reduced; the glass sheet is prevented from being inclined, so that the light path deviation of the photosensitive area is avoided; avoid polluting gold thread and photosensitive area, promote the encapsulation quality.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a chip packaging method and a chip packaging structure.
Background
The chip packaging technology is a process technology for wrapping a memory chip to avoid the chip from contacting with the outside and prevent the chip from being damaged by the outside. Impurities and undesirable gases in the air, and even water vapor, can corrode the precision circuitry on the chip, thereby causing degradation of electrical performance. Different packaging technologies are widely different in manufacturing processes and technologies, and play a crucial role in performance of the memory chip after packaging.
In the prior art, please refer to fig. 1 for a chip package structure. Firstly, thinning and scribing a wafer according to design requirements and dividing the wafer into a plurality of first chips 1, then pasting the divided first chips 1 on a first substrate 6 through chip die attach adhesive (DA adhesive for short), and then enabling a lead 4 to electrically connect the first chips 1 with the first substrate 6 through a lead bonding process; after the electrical connection is completed, the dam adhesive 3 is arranged above the first chip 1 in a surrounding mode, and the first glass carrier 7 is bonded above the first light sensing area 2 of the first chip 1 through the dam adhesive 3; after the setting is finished, plastic packaging protection is carried out through the plastic packaging body 8, and finally the solder balls 5 are formed through a ball mounting process, so that preparation is provided for a subsequent welding process.
However, the elastic modulus of the box dam glue 3 is relatively low, so that the process requirements of operators on the box dam glue 3 and the plastic package body 8 are high, the process difficulty is high, and the economical efficiency is poor; once the box dam glue 3 is arranged, the height of the box dam glue 3 is not easy to appear due to poor process control, and the first glass carrier 7 is inclined, so that the path of light rays entering the first photosensitive area 2 is deviated; poor process control during dispensing of the dam paste 3 may also cause the dam paste 3 to contaminate the lead wire 4 and the first photosensitive region 2.
Disclosure of Invention
The invention aims to provide a chip packaging method and a chip packaging structure, which have low packaging difficulty and low requirement on the technical level of operators; the glass sheet is prevented from being inclined, so that the light path deviation of the photosensitive area is avoided; avoiding pollution to gold wires and photosensitive areas.
In order to achieve the purpose, the invention adopts the following technical scheme:
the chip packaging method comprises the following steps:
s1, photoetching, namely photoetching on a glass sheet to form an etching area;
s2, pasting, namely pasting a UV film on the lead pins of the wafer;
s3, connecting, wherein the surface of the wafer is connected with the glass sheet at one side provided with a photosensitive area to form a bonding layer, and the photosensitive area and the UV film are opposite to the etching area;
s4, cutting, namely cutting and removing the part of the glass sheet above the lead pin so as to expose the lead pin;
s5, scribing, namely scribing the bonding layer into independent chip units;
s6, removing the film, and removing the UV film from the lead pin;
s7, wiring, wherein a gold wire is led out from the lead pin and is electrically connected with the substrate;
and S8, plastic packaging, wherein plastic packaging glue is coated along the periphery of the chip unit.
The chip packaging method according to claim, wherein the step S5 further comprises:
s51, cleaning, namely cleaning the residual burrs of the scribing surface of the bonding layer.
As a preferable scheme of the chip packaging method, after the step S8, the method further includes the following steps:
s9, planting balls, and performing ball planting backflow on one side of the substrate, which is far away from the chip unit, so as to form a micro bump.
As a preferable scheme of the chip packaging method, after the step S9, the following steps are further included:
and S10, electrically connecting, and welding the substrate on a PCB (printed Circuit Board) through the micro-bumps.
As a preferable scheme of the chip packaging method, the cutting is performed by laser cutting or blade dicing in step S4.
As a preferable scheme of the chip packaging method, in step S3, the surface of the wafer and the glass sheet are connected in a pressing manner by van der waals force to form a bonding layer.
As a preferable scheme of the chip packaging method, in step S3, the surface of the wafer is bonded to the glass sheet by bonding glue to form a bonding layer.
The packaging structure is based on the chip packaging method of any scheme, and comprises the following steps:
the chip unit is provided with a photosensitive area;
the glass carrier is provided with a connecting boss and an avoiding groove formed by surrounding the connecting boss, the avoiding groove is arranged opposite to the photosensitive area, and the connecting boss is connected with one surface of the chip unit, which is provided with the photosensitive area;
the lead pins are arranged at two ends of the chip unit and are electrically connected with the substrate through gold wires;
and the sealing part is annularly arranged on the peripheries of the glass carrier and the chip unit.
As a preferable scheme of the package structure, the connection boss is connected to the chip unit by crimping or adhesive bonding.
As a preferred scheme of the packaging structure, the end face of the substrate far away from the chip unit is welded with the PCB.
Has the advantages that:
in the invention, a glass sheet is prepared in advance, a layer of photoresist is coated on the glass sheet, ultraviolet light penetrates through a mask to irradiate the glass sheet to a region needing developing, then the glass sheet is exposed and developed, and an etching region is formed on the glass sheet; next, pasting a UV film on the lead pins of the wafer to cover the lead pins; further, the surface of the wafer is connected with the glass sheet at one side provided with the photosensitive area to form a bonding layer, and the photosensitive area and the UV film are opposite to the etching area; cutting the glass sheet, and cutting off the part of the glass sheet above the lead pins to expose the lead pins; scribing the bonding layer into independent chip units, and forming cutting channels among the chip units after the bonding layer is cut; removing the UV film from the lead pins, leading out gold wires from the lead pins, and electrically connecting the gold wires with the substrate; and finally, coating a plastic sealant along the periphery of the chip unit, so that light rays can only enter the photosensitive area of the chip unit through the glass sheet. By the method, the dam adhesive in the prior art is completely avoided, and a series of process defects caused by point coating of the dam adhesive are naturally avoided, so that the process difficulty of chip packaging is reduced, the requirement on the technical level of operators is low, and the control of the operators on the chip packaging quality is facilitated; the glass sheet is prevented from being inclined, so that the light path deviation of the photosensitive area is avoided; and the gold thread and the photosensitive area can be prevented from being polluted, and the yield of packaged products is improved.
The packaging structure based on the method can effectively improve the yield of chip packaging products and reduce the cost.
Drawings
Fig. 1 is a schematic structural diagram of a conventional chip package structure;
FIG. 2 is a flowchart illustrating steps of a chip packaging method according to an embodiment of the present invention;
fig. 3-10 are schematic structural diagrams illustrating steps of a chip packaging method according to an embodiment of the present invention.
In the figure:
1. a first chip; 2. a first photosensitive region; 3. dam enclosing glue; 4. a lead; 5. a solder ball; 6. a first substrate; 7. a first glass carrier; 8. molding the body;
10. a substrate; 20. a PCB board; 30. a mask, 40, photoresist; 50. cutting a channel; 60. a UV film;
100. a chip unit; 110. a light sensing area; 120. a lead pin;
200. a glass carrier; 210. connecting the bosses; 220. an avoidance groove;
300. gold thread; 400. and a glue sealing part.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings, not all of them.
In the description of the present invention, unless expressly stated or limited otherwise, the terms "connected," "connected," and "fixed" are to be construed broadly, e.g., as meaning permanently connected, removably connected, or integral to one another; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature "on," "above" and "over" the second feature may include the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In the description of the present embodiment, the terms "upper", "lower", "right", etc. are used in an orientation or positional relationship based on that shown in the drawings only for convenience of description and simplicity of operation, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used only for descriptive purposes and are not intended to have a special meaning.
Referring to fig. 2, an aspect of the present embodiment relates to a chip packaging method, where the method is suitable for packaging a chip of a vehicle-mounted camera product but not limited to a vehicle-mounted camera chip, and the method includes the following steps:
referring to fig. 2 and 3, step S1, performing photolithography to form an etching region on the glass sheet;
referring to fig. 2 and 4, step S2 of pasting, a UV film 60 is pasted on the lead pins 120 of the wafer;
referring to fig. 2 and 5, in step S3, a bonding layer is formed by bonding the wafer surface to the glass sheet at the side where the photosensitive region 110 is located, and the photosensitive region 110 and the UV film 60 are both opposite to the etching region;
referring to fig. 2 and 6, in step S4, cutting is performed to cut off a portion of the glass sheet located above the lead pin 120, so as to expose the lead pin 120;
referring to fig. 2 and 7, step S5, dicing the bonding layer into individual chip units 100;
referring to fig. 2 and 8, step S6 is to remove the UV film 60 from the terminal pins 120;
referring to fig. 2 and 8, in step S7, wire connection is performed to draw out the gold wire 300 from the lead pin 120 and electrically connect the gold wire 300 with the substrate 10;
referring to fig. 2 and 9, in step S8, a molding compound is coated along the periphery of the chip unit 100.
In this embodiment, a glass sheet is prepared in advance, a layer of photoresist 40 is coated on the glass sheet, ultraviolet light is irradiated to a region of the glass sheet to be developed through a mask 30, and then the glass sheet is exposed and developed to form an etching region on the glass sheet; next, the UV film 60 is pasted on the lead pins 120 of the wafer, so that the lead pins 120 are covered; further, the wafer surface is connected with the glass sheet at the side provided with the photosensitive area 110 to form a bonding layer, and the photosensitive area 110 and the UV film 60 are opposite to the etching area; next, the glass sheet is cut, and the portion of the glass sheet above the lead pins 120 is cut and removed, so that the lead pins 120 are exposed; dicing the bonding layer into independent chip units 100, and forming dicing channels 50 between the divided chip units 100; removing the UV film 60 from the lead pins 120, drawing the gold wires 300 from the lead pins 120, and electrically connecting the gold wires 300 to the substrate 10; finally, a molding compound is coated along the periphery of the chip unit 100, so that light can enter the photosensitive area 110 of the chip unit 100 only through the glass sheet. By the method, the dam adhesive 3 in the prior art is completely avoided, and a series of process defects caused by point coating of the dam adhesive 3 are naturally avoided, so that the process difficulty of chip packaging is reduced, the requirement on the technical level of operators is low, and the control of the operators on the chip packaging quality is facilitated; the light path deviation of the photosensitive area caused by the inclination of the glass sheet is avoided; and the gold thread and the photosensitive area can be prevented from being polluted, and the yield of packaged products is improved.
Optionally, step S5 further includes:
s51, cleaning, namely cleaning the residual burrs on the section of the bonding layer. When the bonding layer is cut, burrs can be remained between the chip units 100, and the residual burrs need to be cleaned, so that the adhesion of the residual burrs to the subsequent plastic package process is avoided, and the residual burrs can be prevented from falling off to the UV film 60.
Optionally, as shown in fig. 2 and 10, the following steps are further included after step S8:
and S8, planting balls, namely planting the balls on one side of the substrate 10 far away from the chip unit 100 for backflow to form the micro-bumps.
Optionally, as shown in fig. 2 and 8, the following steps are further included after step S8:
and S9, electrically connecting, and welding the substrate 10 on the PCB 20 through the micro-bumps.
In this embodiment, the substrate 10 and the PCB 20 are electrically connected by the micro bumps formed by the ball-mounting reflow process in a soldering manner.
Optionally, the cutting in step 4 is performed by laser cutting or blade dicing. The cutting surface cut by laser is smooth, and the cutting efficiency is high; the cutting economy is good by adopting the blade.
Optionally, step S3 forms a bonding layer by pressing and connecting the surface of the wafer and the glass sheet by van der waals force. By applying a certain extrusion force between the surface of the wafer and the glass sheet, the wafer and the glass sheet can be connected through enough van der Waals force to form a stable bonding layer.
Optionally, step S3 forms a bonding layer by bonding the wafer surface and the glass sheet by bonding glue.
Further, when the surface of the wafer is bonded to the glass sheet by gluing to form a bonding layer, after the dicing step is completed, the residual adhesive needs to be cleaned in addition to the residual burrs between the chip units 100.
Referring to fig. 9, another aspect of the present embodiment further relates to a package structure based on the above chip packaging method, including: the chip unit 100, the glass carrier 200, the gold wire 300 and the sealing part 400; wherein, a photosensitive region 110 is disposed on the chip unit 100; the glass carrier 200 is provided with a connecting boss 210 and an avoiding groove 220 formed by the surrounding of the connecting boss 210, the avoiding groove 220 is arranged opposite to the photosensitive area 110, and the connecting boss 210 is connected with one surface of the chip unit 100, which is provided with the photosensitive area 110; the lead pins 120 are arranged at two ends of the chip unit 100, and the lead pins 120 are electrically connected with the substrate 10 through gold wires 300; the sealant 400 is disposed around the glass carrier 200 and the chip unit 100. Through this packaging structure, can avoid in prior art, use box dam to glue 3 and glue, make things convenient for the encapsulation shaping, have better economic nature.
Alternatively, the connection boss 210 is connected to the chip unit 100 by crimping or adhesive bonding. The crimping or gluing ensures the quality of the connection between the connection boss 210 and the chip unit 100, and the connection form is simple and easy to operate.
Alternatively, the end surface of the substrate 10 away from the chip unit 100 is soldered to the PCB board 20. Specifically, the end face of the substrate 10 can be soldered to the PCB 20 by a ball-mounting reflow process, so that the electrical signal connection between the substrate 10 and the PCB 20 is stable.
It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Numerous obvious variations, adaptations, and substitutions will occur to those skilled in the art without departing from the scope of the present invention. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (10)
1. The chip packaging method is characterized by comprising the following steps:
s1, photoetching, namely photoetching on a glass sheet to form an etching area;
s2, pasting, namely pasting a UV film (60) on the lead pins (120) of the wafer;
s3, connecting, wherein the surface of the wafer is connected with the glass sheet at one side provided with a photosensitive area (110) to form a bonding layer, and the photosensitive area (110) and the UV film (60) are opposite to the etching area;
s4, cutting, namely cutting and removing the part of the glass sheet above the lead pins (120) so as to expose the lead pins (120);
s5, scribing, namely scribing the bonding layer into independent chip units (100);
s6, removing the film, and removing the UV film (60) from the lead pins (120);
s7, wiring, wherein a gold wire (300) is led out from the lead pin (120), and the gold wire (300) is electrically connected with the substrate (10);
and S8, plastic packaging, wherein plastic packaging glue is coated along the periphery of the chip unit (100).
2. The chip packaging method according to claim 1, wherein step S5 further comprises:
s51, cleaning, namely cleaning the residual burrs of the scribing surface of the bonding layer.
3. The chip packaging method according to claim 1, further comprising the following steps after step S8:
s9, planting balls, and performing ball planting backflow on one side of the substrate (10) far away from the chip unit (100) to form a micro bump.
4. The chip packaging method according to claim 3, further comprising the following steps after the step S9:
and S10, electrically connecting, and welding the substrate (10) on a PCB (20) through the micro-bumps.
5. The chip packaging method according to claim 1, wherein the dicing in step S4 is performed by laser dicing or blade dicing.
6. The chip packaging method according to claim 1, wherein step S3 forms a bonding layer by bonding the surface of the wafer and the glass sheet by van der waals force.
7. The chip packaging method according to claim 1, wherein step S3 forms a bonding layer by gluing the surface of the wafer and the glass sheet with a bonding glue.
8. The packaging structure is characterized in that the chip packaging method according to any one of claims 1 to 7 comprises the following steps:
the chip unit (100), wherein a light-sensitive area (110) is arranged on the chip unit (100);
the glass carrier (200) is provided with a connecting boss (210) and an avoiding groove (220) formed by surrounding the connecting boss (210), the avoiding groove (220) is arranged opposite to the photosensitive area (110), and the connecting boss (210) is connected with one surface of the chip unit (100) provided with the photosensitive area (110);
lead pins (120) arranged at both ends of the chip unit (100), the lead pins (120) being electrically connected to the substrate (10) by gold wires (300);
and the sealing part (400) is arranged on the peripheries of the glass carrier (200) and the chip unit (100) in a surrounding manner.
9. The package structure according to claim 8, wherein the connection boss (210) is connected with the chip unit (100) by crimping or adhesive bonding.
10. The package structure according to claim 8, wherein an end surface of the substrate (10) remote from the chip unit (100) is soldered to a PCB (20).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211612938.XA CN115831776A (en) | 2022-12-15 | 2022-12-15 | Chip packaging method and packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211612938.XA CN115831776A (en) | 2022-12-15 | 2022-12-15 | Chip packaging method and packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115831776A true CN115831776A (en) | 2023-03-21 |
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| CN202211612938.XA Pending CN115831776A (en) | 2022-12-15 | 2022-12-15 | Chip packaging method and packaging structure |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006303481A (en) * | 2005-03-25 | 2006-11-02 | Fuji Photo Film Co Ltd | Solid-stage imaging device and manufacturing method thereof |
| US20080061425A1 (en) * | 2006-09-13 | 2008-03-13 | United Microdisplay Optronics Corp. | Chip package structure and fabricating method thereof |
| CN101359656A (en) * | 2007-08-01 | 2009-02-04 | 采钰科技股份有限公司 | Image sensor package and fabrication method thereof |
| CN104392958A (en) * | 2014-11-23 | 2015-03-04 | 北京工业大学 | Semiconductor packaging method of wafer level silicon-based through hole |
| KR20180072411A (en) * | 2016-12-21 | 2018-06-29 | (주) 엔지온 | Method for manufacturing semiconductor package |
| CN114823356A (en) * | 2021-01-29 | 2022-07-29 | 中芯集成电路（宁波）有限公司上海分公司 | Wafer level system packaging method and wafer level system packaging structure |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006303481A (en) * | 2005-03-25 | 2006-11-02 | Fuji Photo Film Co Ltd | Solid-stage imaging device and manufacturing method thereof |
| US20080061425A1 (en) * | 2006-09-13 | 2008-03-13 | United Microdisplay Optronics Corp. | Chip package structure and fabricating method thereof |
| CN101359656A (en) * | 2007-08-01 | 2009-02-04 | 采钰科技股份有限公司 | Image sensor package and fabrication method thereof |
| CN104392958A (en) * | 2014-11-23 | 2015-03-04 | 北京工业大学 | Semiconductor packaging method of wafer level silicon-based through hole |
| KR20180072411A (en) * | 2016-12-21 | 2018-06-29 | (주) 엔지온 | Method for manufacturing semiconductor package |
| CN114823356A (en) * | 2021-01-29 | 2022-07-29 | 中芯集成电路（宁波）有限公司上海分公司 | Wafer level system packaging method and wafer level system packaging structure |
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Application publication date: 20230321 |