CN115831047A

CN115831047A - Pixel circuit, driving method thereof, display substrate and display device

Info

Publication number: CN115831047A
Application number: CN202211641840.7A
Authority: CN
Inventors: 陈腾; 李硕; 李�杰; 卢玉群; 丁小琪; 孟维欣
Original assignee: BOE Technology Group Co Ltd; Chongqing BOE Display Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chongqing BOE Display Technology Co Ltd
Priority date: 2020-11-27
Filing date: 2020-11-27
Publication date: 2023-03-21
Also published as: CN112382237A

Abstract

The embodiment of the disclosure provides a pixel circuit, a driving method thereof, a display substrate and a display device, relates to the technical field of display, and can improve the phenomenon of brightness reduction caused by aging of a light-emitting element and prolong the service life of the light-emitting element. The pixel circuit includes a data writing sub-circuit, a driving sub-circuit, a storage sub-circuit, a first compensation sub-circuit, a second compensation sub-circuit, and a light emission control sub-circuit. The data write-in sub-circuit is coupled with the data signal terminal, the scanning signal terminal and the first node. The driving sub-circuit is coupled with the first voltage terminal, the second node and the third node. The storage sub-circuit is coupled between the first node and the second node. The first compensation sub-circuit is coupled with the first control signal terminal, the first node and the first pole of the light-emitting element. The second compensation sub-circuit is coupled to the second control signal terminal, the second node, and the third node. The light emitting control sub-circuit is coupled to the enable signal terminal, the third node, and the first pole of the light emitting element. The second pole of the light-emitting element is coupled with the second voltage end.

Description

Pixel circuit, driving method thereof, display substrate and display device

This application is a divisional application, filed on 27/11/2020, having application number 202011354558.1, the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, a display substrate, and a display device.

Background

Currently, display devices are often required to have high resolution, high image quality, and other characteristics. A self-Light Emitting display device represented by an Organic Light Emitting Diode (OLED) display device has advantages of self-Light emission, low power consumption, wide viewing angle, and fast response speed, and is one of the hot spots in the research field at present.

Disclosure of Invention

Embodiments of the present disclosure provide a pixel circuit, a driving method thereof, a display substrate and a display device, which can improve a luminance reduction phenomenon caused by aging of a light emitting element and prolong a service life of the light emitting element.

In order to achieve the purpose, the embodiment of the disclosure adopts the following technical scheme:

in a first aspect, embodiments of the present disclosure provide a pixel circuit. The pixel circuit includes a data writing sub-circuit, a driving sub-circuit, a storage sub-circuit, a first compensation sub-circuit, a second compensation sub-circuit, and a light emission control sub-circuit. The data writing sub-circuit is coupled with the data signal terminal, the scanning signal terminal and the first node; the data write subcircuit is configured to write a data signal received at the data signal terminal to the first node in response to a scan signal received at the scan signal terminal. The driving sub-circuit is coupled with a first voltage end, a second node and a third node; the driving sub-circuit is configured to generate a driving current in response to a voltage of the second node. The storage sub-circuit is coupled between the first node and the second node; the storage sub-circuit is configured to store a voltage. The first compensation sub-circuit is coupled with a first control signal terminal, the first node and a first pole of a light-emitting element; the first compensation sub-circuit is configured to transmit a second voltage from a second voltage terminal and a threshold voltage of the light emitting element to the first node in response to a first control signal received at the first control signal terminal. The second compensation sub-circuit is coupled to a second control signal terminal, the second node, and the third node; the second compensation sub-circuit is configured to transmit a first voltage from the first voltage terminal and a threshold voltage of the drive sub-circuit to the second node in response to a second control signal received at the second control signal terminal. The light-emitting control sub-circuit is coupled with an enable signal terminal, the third node and the first pole of the light-emitting element; the light emission control sub-circuit is configured to output the driving current transmitted to the third node to the light emitting element in response to an enable signal received at the enable signal terminal. The second pole of the light emitting element is coupled to the second voltage terminal.

In some embodiments, the pixel circuit further comprises a potential holding sub-circuit coupled between the first voltage terminal and the first node; the potential holding sub-circuit is configured to hold a potential of the first node.

In some embodiments, the potential holding sub-circuit includes a first capacitor; a first terminal of the first capacitor is coupled to the first node and a second terminal of the first capacitor is coupled to the first voltage terminal.

In some embodiments, the first compensation sub-circuit comprises a first transistor; a control electrode of the first transistor is coupled to the first control signal terminal, a first electrode of the first transistor is coupled to the first node, and a second electrode of the first transistor is coupled to the first electrode of the light emitting device.

In some embodiments, the second compensation sub-circuit comprises a second transistor; a control electrode of the second transistor is coupled to the second control signal terminal, a first electrode of the second transistor is coupled to the third node, and a second electrode of the second transistor is coupled to the second node.

In some embodiments, the first control signal terminal and the second control signal terminal are the same control signal terminal.

In some embodiments, the pixel circuit further comprises at least one of a first initialization sub-circuit, a second initialization sub-circuit, and a third initialization sub-circuit. The first initialization sub-circuit is coupled with a first reset signal terminal, a first initialization signal terminal and the first node; the first initialization sub-circuit is configured to transmit a first initialization signal received at the first initialization signal terminal to the first node to initialize a potential of the first node in response to a first reset signal received at the first reset signal terminal. The second initialization sub-circuit is coupled with a second reset signal terminal, a second initialization signal terminal and the second node; the second initialization sub-circuit is configured to transmit a second initialization signal received at the second initialization signal terminal to the second node to initialize a potential of the second node in response to a second reset signal received at the second reset signal terminal. The third initialization sub-circuit is coupled with a third reset signal terminal, a third initialization signal terminal and the first pole of the light-emitting element; the third initialization sub-circuit is configured to transmit a third initialization signal received at the third initialization signal terminal to the first pole of the light emitting element to initialize the potential of the first pole of the light emitting element in response to a third reset signal received at the third reset signal terminal.

In some embodiments, the pixel circuit includes the first, second, and third initialization sub-circuits. The first reset signal terminal, the second reset signal terminal and the third reset signal terminal are the same reset signal terminal, and/or the first initialization signal terminal, the second initialization signal terminal and the third initialization signal terminal are the same initialization signal terminal.

In some embodiments, the first initialization sub-circuit comprises a third transistor; a control electrode of the third transistor is coupled to the first reset signal terminal, a first electrode of the third transistor is coupled to the first initialization signal terminal, and a second electrode of the third transistor is coupled to the first node.

In some embodiments, the second initialization sub-circuit comprises a fourth transistor; a control electrode of the fourth transistor is coupled to the second reset signal terminal, a first electrode of the fourth transistor is coupled to the second initialization signal terminal, and a second electrode of the fourth transistor is coupled to the second node.

In some embodiments, the third initialization sub-circuit comprises a fifth transistor; a control electrode of the fifth transistor is coupled to the third reset signal terminal, a first electrode of the fifth transistor is coupled to the third initialization signal terminal, and a second electrode of the fifth transistor is coupled to the first electrode of the light emitting element.

In some embodiments, the data write sub-circuit comprises a sixth transistor; a control electrode of the sixth transistor is coupled to the scan signal terminal, a first electrode of the sixth transistor is coupled to the data signal terminal, and a second electrode of the sixth transistor is coupled to the first node.

In some embodiments, the storage sub-circuit comprises a second capacitor; a first terminal of the second capacitor is coupled to the first node and a second terminal of the second capacitor is coupled to the second node.

In some embodiments, the drive sub-circuit drives a transistor; the control electrode of the driving transistor is coupled to the second node, the first electrode of the driving transistor is coupled to the first voltage terminal, and the second electrode of the driving transistor is coupled to the third node.

In some embodiments, the emission control sub-circuit includes a seventh transistor; a control electrode of the seventh transistor is coupled to the enable signal terminal, a first electrode of the seventh transistor is coupled to the third node, and a second electrode of the seventh transistor is coupled to the first electrode of the light emitting device.

In a second aspect, an embodiment of the present disclosure provides a driving method of a pixel circuit, which is applied to the pixel circuit described in any of the above embodiments. The driving method includes: during a compensation phase of an image frame, the second compensation sub-circuit transmits a first voltage from the first voltage terminal and a threshold voltage of the driving sub-circuit to the second node in response to a second control signal received at the second control signal terminal; the first compensation sub-circuit transmits a second voltage from the second voltage terminal and a threshold voltage of the light emitting element to the first node in response to a first control signal received at the first control signal terminal; in a write phase of the image frame, the data write sub-circuit writes a data signal received at the data signal terminal into the first node in response to a scan signal received at the scan signal terminal; and, during the light emitting phase of the image frame, the driving sub-circuit is turned on in response to the voltage of the second node to generate a driving current; the light emitting control sub-circuit outputs the driving current transmitted to the third node to the light emitting element in response to an enable signal received at the enable signal terminal to drive the light emitting element to emit light.

In some embodiments, the pixel circuit further comprises: at least one of a first initialization sub-circuit, a second initialization sub-circuit, and a third initialization sub-circuit; the first initialization sub-circuit is coupled with a first reset signal terminal, a first initialization signal terminal and the first node; the second initialization sub-circuit is coupled with a second reset signal terminal, a second initialization signal terminal and the second node; the third initialization sub-circuit is coupled to a third reset signal terminal, a third initialization signal terminal, and the first pole of the light emitting element. Prior to the compensation phase of the image frame, the driving method further comprises at least one of the following steps: the first initialization sub-circuit transmits a first initialization signal received at the first initialization signal terminal to the first node in response to a first reset signal received at the first reset signal terminal to initialize a potential of the first node in a reset phase of the image frame; the second initialization sub-circuit transmits a second initialization signal received at the second initialization signal terminal to the second node in response to a second reset signal received at the second reset signal terminal to initialize a potential of the second node in the reset phase of the image frame; and, during the reset phase of the image frame, the third initialization sub-circuit transmits a third initialization signal received at the third initialization signal terminal to the first pole of the light emitting element in response to a third reset signal received at the third reset signal terminal to initialize the potential of the first pole of the light emitting element.

In a third aspect, embodiments of the present disclosure provide a display substrate. The display substrate comprises a substrate, a pixel circuit and a light-emitting element, wherein the pixel circuit is arranged on the substrate, and the light-emitting element is arranged on the substrate; the light emitting element is coupled to the pixel circuit.

In some embodiments, the pixel circuit further comprises a potential holding sub-circuit coupled to the first voltage terminal and the first node; the potential holding sub-circuit is configured to hold a potential of the first node; the potential holding sub-circuit includes a first capacitor. The storage sub-circuit in the pixel circuit includes a second capacitor. The display substrate further comprises a first conductor layer and a second conductor layer which are sequentially stacked on the substrate. The first conductor layer and the second conductor layer are insulated from each other; the first conductor layer includes: a first conductor pattern and a second conductor pattern which are not connected with each other; the second conductor layer includes: a third conductor pattern; an orthogonal projection of the third conductor pattern on the substrate has an overlapping area with an orthogonal projection of the first conductor pattern on the substrate to form the first capacitor; an orthogonal projection of the third conductor pattern on the substrate has an overlapping area with an orthogonal projection of the second conductor pattern on the substrate to form the second capacitor.

In a fourth aspect, embodiments of the present disclosure provide a display device. The display device comprises the display substrate and a driving chip coupled with the display substrate; the driving chip is configured to supply signals required to drive the pixel circuits to the pixel circuits in the display substrate.

Embodiments of the present disclosure provide a pixel circuit, a driving method thereof, a display substrate and a display device, wherein the pixel circuit is used for compensating a threshold voltage V of a light emitting element _{oled_th} So that the driving current finally flowing through the light emitting element and its own threshold voltage V _{oled_th} And (4) positively correlating. Thus, when the light emitting element is deteriorated due to aging, the light emitting luminance is lowered, that is, the threshold voltage V of the light emitting element is set _{oled_th} After the driving current is increased, the driving current flowing through the light emitting element is increased, so that the compensation of the driving current of the light emitting element is realized, the problem of brightness reduction of the light emitting element due to aging is solved, the service life of the light emitting element is prolonged, and the display quality is improved.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, however, the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1 is a graph of the lifetime decay characteristic of an OLED;

fig. 2 is a schematic diagram illustrating a routing of a display substrate in a self-luminous display device according to an embodiment;

FIG. 3 is a block diagram of a display device according to some embodiments;

FIG. 4 is a block diagram of a display substrate according to some embodiments;

FIG. 5 is a block diagram of a sub-pixel according to some embodiments;

FIG. 6 is a circuit diagram of a pixel circuit according to some embodiments;

FIG. 7 is a circuit diagram of a pixel circuit provided in accordance with further embodiments;

fig. 8A-8D are circuit diagrams of pixel circuits provided in accordance with still further embodiments;

fig. 9A to 9D are circuit diagrams of pixel circuits provided according to still further embodiments;

FIG. 10 is a circuit diagram of a pixel circuit provided in accordance with yet further embodiments;

FIG. 11 is a circuit diagram of a pixel circuit provided in accordance with yet further embodiments;

FIG. 12 is a signal timing diagram of the pixel circuit shown in FIG. 11;

FIG. 13A is a schematic diagram of the pixel circuit shown in FIG. 11 during a reset phase;

FIG. 13B is a diagram illustrating the operation of the pixel circuit shown in FIG. 11 during a compensation phase;

FIG. 13C is a diagram illustrating the operation of the pixel circuit shown in FIG. 11 during a writing phase;

FIG. 13D is a diagram illustrating the operation of the pixel circuit shown in FIG. 11 in a light-emitting phase;

FIG. 14 is a schematic feedback diagram of two pixel circuits provided in one embodiment;

fig. 15 is a graph comparing the feedback principle of a pixel circuit provided according to some embodiments with the feedback principle of a pixel circuit provided by an aspect;

FIG. 16 is a simulation model diagram of the pixel circuit shown in FIG. 11;

FIG. 17 is a schematic diagram of simulated signals for the pixel circuit shown in FIG. 11;

FIG. 18 is a block diagram of a display substrate according to further embodiments;

FIG. 19 is a schematic layout of a display substrate according to some embodiments;

FIGS. 20A-20D are schematic layouts of the layers of FIG. 19;

FIG. 21 is a flow chart of a method of driving a pixel circuit according to some embodiments; and the number of the first and second groups,

FIG. 22 is a flow chart of a method for driving a pixel circuit according to further embodiments.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, however, the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided in the present disclosure are within the scope of protection of the present disclosure.

Unless the context requires otherwise, throughout the description and the claims, the term "comprise" and its other forms, such as the third person's singular form "comprising" and the present participle form "comprising" are to be interpreted in an open, inclusive sense, i.e. as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified. Furthermore, as used in this specification and the appended claims, the singular forms "a," "an," and "the" may include plural referents unless the content clearly dictates otherwise. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

It will be understood that when a layer or an element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or one or more intervening layers or elements may also be present. It will also be understood that when a layer or an element is referred to as being "under" another layer or substrate, it can be directly under the other layer or substrate, or one or more intervening layers or elements may also be present. Similarly, it will also be understood that when a layer or an element is referred to as being between two layers or elements, it can be the only layer or element between the two layers or elements, or one or more intervening layers may also be present.

In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more components are in physical contact or that an electrical signal path exists, for example, two components are in electrical communication via a signal line, or that other electrical components or circuits may exist between two components, but a signal path exists between two components via other electrical components. However, the terms "coupled" or "communicatively coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

As used herein, the term "if" is optionally interpreted to mean "when 8230; \8230;" or "at 8230; \823030;" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrase "if it is determined \8230;" or "if [ a stated condition or event ] is detected" is optionally interpreted to mean "upon determining 8230; \8230, or" in response to determining 8230; \8230; "or" upon detecting [ a stated condition or event ], or "in response to detecting [ a stated condition or event ], depending on the context.

The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

As used herein, "about" or "approximately" includes the stated values as well as average values within an acceptable deviation range for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

A self-light emitting display device includes a plurality of light emitting elements, and has attracted attention because of their characteristics such as high luminance and wide color gamut. The photoelectric conversion characteristics (including photoelectric conversion efficiency, uniformity, color coordinates, and the like) of a light-emitting element change with a change in current flowing through the light-emitting element.

Taking an Organic Light Emitting Diode (OLED) as an example, since the OLED is under a dc bias state for a long time during the Light Emitting process, the polarization of the Light Emitting material in the OLED is accelerated, that is, the aging of the Light Emitting material is accelerated, so that the built-in electric field of the OLED (that is, the electric field formed by the semiconductor due to the internal action) is rapidly enhanced, and further the resistance and the threshold voltage of the OLED (that is, the threshold voltage at which the OLED can emit Light, which is also referred to as the critical voltage across the OLED) are increased, and finally the voltage difference between the anode and the cathode of the OLED is increased. Therefore, under the condition that the data signal is not changed, the current actually flowing in the OLED is reduced, so that the actual light-emitting brightness of the OLED is reduced, the set brightness is difficult to achieve, and the quality of a display picture of the self-luminous display device is reduced.

When the ratio of the actual brightness of the light that can be emitted by the OLED to the initial brightness (i.e., the maximum brightness of the light that can be emitted by the OLED at the beginning of use) is too low, for example, the ratio is reduced to 0.8 (i.e., the actual brightness of the light that can be emitted by the OLED is 80% of the initial brightness), the requirement of the display screen cannot be met, and it is difficult to continue to display the screen using the self-luminous display device, i.e., the lifetime of the self-luminous display device having the OLED is reduced. Therefore, as the threshold voltage of the OLED increases, the lifetime thereof may be greatly reduced.

Fig. 1 is a graph of life-time decay characteristics of an OLED. As shown in fig. 1, the abscissa represents time (hours, h), the ordinate on the left side represents the voltage (V) of the anode surface of the OLED obtained using the galvanostatic test, and the ordinate on the right side represents the lifetime (percentage) of the OLED.

Since the voltage applied to the cathode of the OLED is usually a constant dc voltage, the voltage difference between the anode and the cathode of the OLED can be characterized over time by testing the change of the voltage on the anode surface of the OLED over time, that is, the change of the threshold voltage of the OLED over time. As can be seen from fig. 1, as the service life of the OLED is prolonged, the threshold voltage of the OLED gradually increases, i.e., the lifetime of the OLED gradually decreases.

For some products with long service life, such as vehicle-mounted display, ship-mounted display and notebook computer, the lifetime problem of the light emitting element (such as the above OLED) itself limits its further application in the above long service life products, thereby limiting the application field of the self-luminous display device.

In order to extend the lifetime of the light emitting element, the related art provides a method of compensating for the current of the light emitting element. The method is characterized in that the current or the voltage of a light-emitting element (such as an OLED) in each sub-pixel in the light-emitting stage is tested, the deficiency of the current actually flowing in the OLED is compensated into a data signal input to the sub-pixel after corresponding calculation, so that the current of the OLED is improved, the light-emitting brightness of the OLED is improved, and the purpose of prolonging the service life of the OLED is achieved.

The above method is by compensating the current of the OLED from the outside of the sub-pixel, and thus is also referred to as an external compensation method.

Because the anode of the OLED and the sensing signal line need to be connected in series to test the current of the OLED, the process difficulty is high, and therefore, when an external compensation method is adopted, the anode of the OLED and the sensing signal line are usually connected in parallel.

Fig. 2 is a schematic diagram of a routing of a display substrate in a self-luminous display device according to a technical solution. As shown in fig. 2, the display substrate 100' has a display Area (AA) and a peripheral Area located at least one side outside the AA Area. A plurality of sub-pixels (e.g., a red sub-pixel P1, a green sub-pixel P2, a blue sub-pixel P3, etc.), a plurality of sensing signal lines (Sense) coupled to the plurality of sub-pixels, etc. are disposed in the AA region. The peripheral region includes a Bonding region (B), and the sensing signal line Sense extends to the Bonding region B and is coupled to an Integrated Circuit (IC) (not shown in fig. 2) to transmit a voltage signal of an anode surface of the OLED in the corresponding sub-pixel.

Thus, the number of ICs needs to be increased to calculate a data signal for compensating the current of the OLED, resulting in a great increase in cost. In addition, because the position for testing the voltage of the anode surface of the OLED in the external compensation method is the Pad end (Pad) in the binding region B, after the signal is transmitted through the longer sensing signal line Sense, the intensity of the signal may change, which affects the measurement result of the voltage of the anode surface of the OLED, thereby reducing the accuracy of the external compensation method and making it difficult to effectively improve the service life of the light-emitting element.

Therefore, the reduction of the light-emitting brightness of the light-emitting element (such as an OLED) caused by aging is improved, the service life of the OLED is prolonged, and the display quality of the display device with the OLED is improved. Embodiments of the present disclosure provide a display device.

Illustratively, the display device may be any device that displays text or images, whether in motion (e.g., video) or stationary (e.g., still images). More particularly, the display device may be one of a variety of electronic devices, which embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal Data Assistants (PDAs), handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), navigators, cockpit controls and/or displays, camera view displays (e.g., of a rear-view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., a display of an image for a piece of jewelry), and so forth. The embodiment of the present disclosure does not particularly limit the specific form of the display device.

FIG. 3 is a block diagram of a display device according to some embodiments. As shown in fig. 3, the display device 200 includes a display substrate 100.

The display substrate 100 has a display Area (AA) and a peripheral Area W. The peripheral area W is located on at least one side outside the AA area.

The display substrate 100 includes a plurality of subpixels P disposed in the AA region. Illustratively, the plurality of subpixels P may be arranged in an array. For example, the sub-pixels P arranged in a row along the X direction (e.g., row direction) in fig. 3 are referred to as the same row sub-pixels, and the sub-pixels P arranged in a row along the Y direction (e.g., column direction) in fig. 3 are referred to as the same column sub-pixels.

Fig. 4 is a block diagram of a display substrate according to some embodiments. As shown in fig. 4, the display base panel 100 further includes a substrate 100a. The aforementioned pixel circuit 101 and light-emitting element L are both provided over the substrate 100a.

It should be understood that, for the sake of illustration, in fig. 4, the pixel circuit 101 and the light emitting element L are represented by a single layer, and the specific structures of both will be specifically described in the following embodiments.

Illustratively, the substrate 100a may include: a rigid substrate (or referred to as a hard substrate) made of glass or the like, or a flexible substrate made of Polyimide (PI), polyethylene Terephthalate (PET), polycarbonate (PC), polymethyl Methacrylate (PMMA), or Polyether sulfone (PES) or the like.

Further, in some examples, the display substrate 100 further includes: a buffer layer or the like provided on the substrate 100a to block impurity ions possibly present in the substrate 100a from migrating toward the pixel circuit 101 in the process of manufacturing the pixel circuit 101. That is, the pixel circuit 101 is provided on a surface of a thin film such as a buffer layer facing away from the substrate 100a.

FIG. 5 is a block diagram of a sub-pixel according to some embodiments. As shown in fig. 5, each sub-pixel P includes: a light emitting element L, and a pixel circuit 101 coupled to the light emitting element L. The pixel circuit 101 is configured to supply a drive current to the light emitting element L to drive the light emitting element L to operate (i.e., emit light).

Illustratively, as shown in fig. 5, a first pole of the light emitting device L is coupled to the pixel circuit 101, and a second pole of the light emitting device L is coupled to the second voltage terminal V2. The second voltage terminal V2 is configured to transmit a second voltage. The second Voltage is a reference Voltage (V) of a direct current (dc) _SS ) E.g. second voltage V _SS is-3V. Alternatively, the second voltage V _SS Is 0V, i.e. the second voltage terminal V2 is grounded. The second voltage terminal V2 may supply 0V or a negative voltage to the second electrode of the light emitting element L.

Illustratively, the light emitting element L includes a current-driven type element. Further, the Light Emitting element L may be an electric current type Light Emitting Diode, such as a Micro Light Emitting Diode (Micro LED), a Mini Light Emitting Diode (Mini LED), a Quantum dot Light Emitting Diode (QLED), or an Organic Light Emitting Diode (OLED). Illustratively, the first and second poles of the light emitting element L are the anode and cathode of the light emitting diode, respectively.

Fig. 6 is a circuit diagram of a pixel circuit according to some embodiments. As shown in fig. 6, the pixel circuit 101 includes: a data writing sub-circuit 10, a driving sub-circuit 20, a storage sub-circuit 30, a first compensation sub-circuit 41, a second compensation sub-circuit 42, and a light emission control sub-circuit 50.

The Data writing sub-circuit 10 is coupled to the Data signal terminal Data, the Scan signal terminal Scan, and the first node N1. The Data writing sub-circuit 10 is configured to write the Data signal received at the Data signal terminal Data to the first node N1 in response to the Scan signal received at the Scan signal terminal Scan.

The driving sub-circuit 20 is coupled to the first voltage terminal V1, the second node N2 and the third node N3. The driving sub-circuit 20 is configured to generate the driving current I in response to the voltage of the second node N2.

The storage sub-circuit 30 is coupled between the first node N1 and the second node N2. The storage sub-circuit 30 is configured to store a voltage.

The first compensation sub-circuit 41 is coupled to the first control signal terminal Q1, the first node N1 and the first pole of the light emitting element L. The first compensation sub-circuit 41 is configured to transmit the second voltage from the second voltage terminal V2 and the threshold voltage of the light emitting element L to the first node N1 in response to the first control signal received at the first control signal terminal Q1.

The second compensation sub-circuit 42 is coupled to the second control signal terminal Q2, the second node N2, and the third node N3. The second compensation sub-circuit 42 is configured to transfer the first voltage from the first voltage terminal V1 and the threshold voltage Vth of the driving sub-circuit 20 to the second node N2 in response to a second control signal received at the second control signal terminal Q2.

The light emission control sub-circuit 50 is coupled with the enable signal terminal EM, the third node N3, and the first pole of the light emitting element L. The light emission control sub-circuit 50 is configured to output the driving current I transmitted to the third node N3 to the light emitting element L in response to the enable signal received at the enable signal terminal EM.

The second pole of the light emitting device L is coupled to the second voltage terminal V2.

It should be understood that in the pixel circuit 101 provided by the embodiment of the present disclosure, the nodes such as the first node N1, the second node N2, and the third node N3 do not necessarily represent actually existing components, and in some examples, these nodes represent junctions that are relatively coupled (i.e., electrically connected) in an equivalent circuit diagram of the pixel circuit, that is, these nodes are nodes that are equivalent to the junctions that are relatively electrically connected in the circuit diagram.

Illustratively, the light-emitting element L is an OLED, and the threshold voltage of the light-emitting element L is the threshold voltage V of the OLED _{oled_th} . The operation of the pixel circuit 101 is described below by taking the light emitting element L as an OLED as an example, but it should be understood that the light emitting element L may be other current driving elements such as a Micro LED, a Mini LED, or a QLED, and the embodiment of the disclosure is not limited thereto.

The pixel circuit 101 provided by the embodiment of the present disclosure is operated:

during a compensation phase U2 of an image frame F, the second compensation sub-circuit 42 responds to a second control signal received at the second control signal terminal Q2 to apply a first Voltage (e.g., a power supply Voltage) from the first Voltage terminal V1 _DD ) And the threshold voltage Vth of the driving sub-circuit 20 is transferred to the second node N2. And, in the compensation phase U2 of the image frame F, the first compensation sub-circuit 41 responds to the first control signal received at the first control signal terminal Q1 to apply the second voltage V from the second voltage terminal V2 _SS And threshold voltage V of light emitting element L _{oled_th} To the first node N1.

Illustratively, a first voltage V from a first voltage terminal V1 _DD Is a dc voltage, e.g., a dc high level voltage. At a first voltage V from a first voltage terminal V1 _DD A second voltage V from a second voltage terminal V2 under the condition of high level voltage _SS Is a low level voltage; for example, the first voltage V _DD Is 4.6V, and the second voltage V _SS is-3V.

Thus, during the compensation phase U2, the voltage V of the second node N2 _N2 Is equal to V _DD + Vth, first sectionVoltage V of point N1 _N1 Is equal to V _SS +V _{oled_th} . Since the memory sub-circuit 30 is coupled between the first node N1 and the second node N2, that is, the voltage difference Δ V between the two ends of the memory sub-circuit 30 is V _N2 -V _N1 I.e. Δ V equals V _DD +Vth-V _SS -V _{oled_th} 。

In the writing phase U3 of the image frame F, the Data writing sub-circuit 10 responds to the Scan signal received at the Scan signal terminal Scan, the Data signal V to be received at the Data signal terminal Data _data The first node N1 is written.

In the write phase U3, due to the data signal V _data Directly writing to the first node N1 through the data writing sub-circuit 10, thereby causing the voltage V of the first node N1 _N1 Is directly changed into V _data I.e. V _N1 ＝V _data 。

Since the storage sub-circuit 30 stores the voltage by virtue of the capacitor, the voltage V at the first node N1 is obtained by utilizing the bootstrap effect of the capacitor (i.e. the effect that the voltage across the capacitor cannot change abruptly and the voltage at one end is still kept at the voltage difference with the former end when the voltage at the other end rises) _N1 Becomes V _data I.e. V _N1 ＝V _data Then, the voltage V of the second node N2 is enabled _N2 Finally stabilize to V _N2 ＝V _data +ΔV＝V _data +V _DD +Vth-V _SS -V _{oled_th} 。

Due to the voltage difference (V) between the first voltage terminal V1 and the second node N2 _data +Vth-V _SS -V _{oled_th} ) Greater than the threshold voltage Vth of the driving sub-circuit 20, and thus, the driving sub-circuit 20 responds to the voltage V of the second node N2 _N2 Conducting and generating a driving current I which satisfies the following formula:

I＝1/2·μ·C _ox ·W/L·(V _gs -Vth) ² ；

＝1/2·μ·C _ox ·W/L·(V _N2 -V _DD -Vth) ² ；

＝1/2·μ·C _ox ·W/L·(V _data +V _DD +Vth-V _SS -V _{oled_th} -V _DD -Vth) ² ；

＝1/2·μ·C _ox ·W/L·(V _data -V _SS -V _{oled_th} ) ² ；

＝1/2·μ·C _ox ·W/L·(V _SS +V _{oled_th} -V _data ) ² ；

wherein, mu and C _ox W and L are fixed constants related to the process parameters and the geometry of the drive sub-circuit 20. In particular, μ, C _ox W and L are the field effect mobility, gate insulating layer unit area capacitance, channel width and channel length, respectively, of the drive transistor in the drive sub-circuit 20. V _gs Is the gate-source voltage difference of the drive transistors in the drive sub-circuit 20.

In the light emitting phase U4 of the image frame F, the light emitting control sub-circuit 50 outputs the driving current I transmitted to the third node N3 to the light emitting element L in response to the enable signal received at the enable signal terminal EM to drive the light emitting element L to emit light.

As can be seen from the above formula, the driving current I finally flowing through the light emitting element L is not related to the threshold voltage Vth of the driving sub-circuit 20, but is related to the threshold voltage V of the light emitting element L _{oled_th} And (4) positively correlating. Thus, as the lifetime of the light-emitting element L increases, the light-emitting efficiency of the light-emitting element L decreases due to the aging of the material, and the threshold voltage V of the light-emitting element L _{oled_th} Will rise and the threshold voltage V will rise _{oled_th} The increase of the voltage level will drive the driving current I flowing through the light-emitting device L to increase correspondingly (in the case of the data signal V) _data Without change), i.e. compensation of the current of the light emitting element L is achieved.

Based on this, the pixel circuit 101 provided by the embodiment of the disclosure can improve the phenomenon of reduction of the light emitting luminance of the light emitting element L (e.g. OLED) due to aging by using the circuit structure of the pixel circuit 101 through the timing control of each signal, so that the driving current I finally flowing through the OLED and the threshold voltage V of the driving current I and the threshold voltage V are finally obtained _{oled_th} Positive correlation is made so that when the threshold voltage V is _{oled_th} At the rise, the driving current I flowing through the OLED followsThe service life of the OLED is prolonged, and the display quality of the display device with the OLED is improved.

Since the above-described pixel circuit 101 provided by the embodiment of the present disclosure compensates the current of the light emitting element L from the inside of the sub-pixel using the circuit structure of the pixel circuit 101 itself, the compensation method using this pixel circuit 101 may be referred to as an internal compensation method. Compared with the external compensation method in the related art, when the pixel circuit 101 provided by the embodiment of the disclosure is used for compensating the current of the light emitting element L, an IC does not need to be added in the display device, and the compensation cost is lower; and the light emitting element L coupled to each pixel circuit 101 can be independently compensated, and the compensation accuracy is higher.

In addition, the light-emitting material in the OLED is usually made by an evaporation process, and the threshold voltage V of the OLED is limited due to the limited precision of the evaporation process _{oled_th} Non-uniformity may occur due to the influence of the evaporation process. With the above-described pixel circuit 101 provided by the embodiment of the present disclosure, the driving current I finally flowing through the OLED and its own threshold voltage V are due to _{oled_th} Positive correlation between the driving current I flowing through the OLED and the threshold voltage V of the OLED _{oled_th} Synchronously changes, thereby improving the threshold voltage V of the OLED _{oled_th} Non-uniform light emission.

And, the driving current I and the first voltage V finally flow through the OLED _DD Independent of the threshold voltage Vth of the drive sub-circuit 20, such that the drive current I of the OLED is not transferred by the first voltage V _DD First power line L _V1 The voltage drop (i.e., the potential difference across the resistor, IR drop) and the threshold voltage Vth of the driving sub-circuit 20, the pixel circuit 101 can improve the uniformity of the driving current flowing through the OLED and achieve the uniformity of the emission luminance.

Since the second compensation sub-circuit 42 will receive the first voltage V from the first voltage terminal V1 during the compensation phase U2 _DD And the threshold voltage Vth of the driving sub-circuit 20 is transferred to the second node N2 to compensate for the threshold voltage Vth of the driving sub-circuit 20; and the first compensation sub-circuit 41 will be from the second voltage terminal V2A second voltage V _SS And threshold voltage V of light emitting element L _{oled_th} Transmitted to the first node N1 to compensate the threshold voltage V of the light emitting element L _{oled_th} . Since both compensation sub-circuits operate during the compensation phase U2 of the image frame, the first compensation sub-circuit 41 is arranged to apply a threshold voltage V to the light-emitting element L _{oled_th} May be set to be the same as the compensation time of the second compensation sub-circuit 42 for the threshold voltage Vth of the driving sub-circuit 20 to simplify the timing control process of the signals.

For example, as shown in fig. 6, the first control signal terminal Q1 and the second control signal terminal Q2 may be the same control signal terminal Q, and the control signal terminal Q is coupled to a control signal line L _Q . That is, the first compensation sub-circuit 41 and the second compensation sub-circuit 42 are turned on simultaneously, and the turn-on time is the same. As follows, the number of signal lines in the display substrate 100 can also be simplified, so that the display substrate 100 has a looser wiring space in order to realize the display apparatus 200 with higher resolution.

Fig. 7 is a circuit diagram of a pixel circuit provided in accordance with further embodiments. As shown in fig. 7, the pixel circuit 101 includes: a data writing sub-circuit 10, a driving sub-circuit 20, a storage sub-circuit 30, a first compensation sub-circuit 41, a second compensation sub-circuit 42, a light emission control sub-circuit 50, and a potential holding sub-circuit 60. The voltage holding sub-circuit 60 is coupled between the first voltage terminal V1 and the first node N1. The potential holding sub-circuit 60 is configured to hold the potential of the first node N1.

The functions and mutual coupling of the data writing sub-circuit 10, the driving sub-circuit 20, the storage sub-circuit 30, the first compensation sub-circuit 41, the second compensation sub-circuit 42 and the light-emitting control sub-circuit 50 are the same as those of the previous embodiments, and are not repeated herein.

Since the voltage holding sub-circuit 60 is coupled to the first voltage terminal V1 and the first node N1, on one hand, the voltage of the first node N1 can be kept stable at V during the light emitting period U4 _data Preventing the light-emitting element from being in a floating state to avoid influencing the compensation of the driving current I of the light-emitting element L; on the other hand, at a voltage from the first voltage terminal V1A first voltage V _DD The voltages of the first node N1 and the second node N2 can be equal to the first voltage V when a droop or ripple condition occurs _DD The transition is the same so that Vgs of the driving sub-circuit 20 is constant, thereby keeping the light emission luminance of the light emitting element L constant.

Fig. 8A to 8D are circuit diagrams of pixel circuits provided according to still further embodiments. As shown in fig. 8A to 8D, the pixel circuit 101 includes: the data writing sub-circuit 10, the driving sub-circuit 20, the storage sub-circuit 30, the first compensation sub-circuit 41, the second compensation sub-circuit 42, the light emission control sub-circuit 50, and at least one of the first initialization sub-circuit 71, the second initialization sub-circuit 72, and the third initialization sub-circuit 73.

Fig. 9A to 9D are circuit diagrams of pixel circuits provided according to still further embodiments. As shown in fig. 9A to 9D, the pixel circuit 101 includes: the data writing sub-circuit 10, the driving sub-circuit 20, the storage sub-circuit 30, the first compensation sub-circuit 41, the second compensation sub-circuit 42, the light emission control sub-circuit 50, the potential holding sub-circuit 60, and at least one of the first initialization sub-circuit 71, the second initialization sub-circuit 72, and the third initialization sub-circuit 73.

The functions and the coupling manners of the data writing sub-circuit 10, the driving sub-circuit 20, the storage sub-circuit 30, the first compensation sub-circuit 41, the second compensation sub-circuit 42, the light-emitting control sub-circuit 50 and the voltage holding sub-circuit 60 are the same as those of the previous embodiments, and are not repeated herein.

As shown in fig. 8A, 8D, 9A, and 9D, the first initialization sub-circuit 71 is coupled to the first reset signal terminal Rst1, the first initialization signal terminal Init1, and the first node N1. The first initialization sub-circuit 71 is configured to transmit a first initialization signal received at the first initialization signal terminal Init1 to the first node N1 in response to a first reset signal received at the first reset signal terminal Rst1 to initialize the potential of the first node N1, i.e., pull down the potential of the first node N1.

The first initialization sub-circuit 71 operates in a reset phase U1 prior to the compensation phase U2 of the image frame F, and plays a role in setting the first node N1.

In the reset phase U1, the data voltage V of the first node N1 in the previous image frame is cleared by the first initialization signal _data So that the potential of the first node N1 is initialized to avoid signal interference. The voltage of the first initialization signal may be selected according to actual conditions, and is not limited herein. For example, the first initialization signal is a low level signal. For example, the first initialization signal is-3V.

As shown in fig. 8B, 8D, 9B, and 9D, the second initialization sub-circuit 72 is coupled to the second reset signal terminal Rst2, the second initialization signal terminal Init2, and the second node N2. The second initialization sub-circuit 72 is configured to transmit a second initialization signal received at the second initialization signal terminal Init2 to the second node N2 in response to a second reset signal received at the second reset signal terminal Rst2 to initialize the potential of the second node N2, i.e., pull down the potential of the second node.

The second initialization sub-circuit 72 operates in a reset phase U1 prior to the compensation phase U2 of the image frame F, acting on the second node N2.

In the reset phase U1, the voltage (V) in the previous image frame on the second node N2 is cleared by the second initialization signal _data +V _DD +Vth-V _SS -V _{oled_th} ) So that the potential of the second node N2 is initialized to avoid signal interference. The voltage of the second initialization signal may be selected according to actual conditions, and is not limited herein. For example, the second initialization signal is a low level signal. For example, the second initialization signal is-3V.

As shown in fig. 8C, 8D, 9C, and 9D, the third initialization sub-circuit 73 is coupled with the third reset signal terminal Rst3, the third initialization signal terminal Init3, and the first pole of the light emitting element L. The third initialization sub-circuit 73 is configured to transmit a third initialization signal received at the third initialization signal terminal Init3 to the first pole of the light emitting element L to initialize, i.e., pull down, the potential of the first pole of the light emitting element L in response to a third reset signal received at the third reset signal terminal Rst 3.

The third initialization sub-circuit 73 operates in a reset phase U1 prior to the compensation phase U2 of the image frame F and acts on the first pole of the light emitting element L.

In the reset phase U1, the third initialization sub-circuit 73 clears the voltage of the first electrode of the light-emitting element L, so that the potential of the first electrode of the light-emitting element L is initialized, the light-emitting element L is prevented from emitting light in a dark state due to the influence of the leakage current of the light-emitting control sub-circuit 50, and the display quality of the display device with the pixel circuit 101 is improved.

It should be noted that, in the compensation phase U2 after the reset phase U1, the second compensation sub-circuit 42 is turned on in response to the second control signal received at the second control signal terminal Q2, so that the line between the second node N2 and the third node N3 is also turned on, and thus, the first voltage V from the first voltage terminal V1 is also turned on _DD Can be transmitted to the second node N2 through the second compensation sub-circuit 42 and the driving sub-circuit 20, thereby raising the potential of the second node N2. Due to the bootstrap effect of the storage sub-circuit 30, the potential of the first node N1 is driven, that is, the potential of the first node N1 is raised synchronously, and then the charge of the first node N1 flows into the first pole of the light emitting device L through the first compensation sub-circuit 41, so as to compensate the threshold voltage V of the light emitting device L _{oled_th} . Finally, the voltage V of the second node N2 in the steady state _N2 Is a V _DD + Vth, which is irrelevant to the potential of the second node N2 in the reset phase U1; voltage V selected by first node N1 in stable state _N1 Is a V _SS +V _{oled_th} This voltage is not related to the potential of the first node N1 during the reset phase U1.

That is, since the first node N1 is in the compensation phase U2, the charge is transferred to the first electrode of the light emitting element L before the steady state (i.e. the threshold voltage V of the light emitting element L is compensated) _{oled_th} ) Therefore, in the compensation phase U2, the two ends of the storage sub-circuit 30 are not maintained at the potential difference of the previous reset phase U1.

Based on the above analysis process, it can be known whether the initialization signals from the initialization signal terminals are the same or not, and the compensation phase U2 is not affected. That is, the initialization signals at the respective initialization signal terminals may be the same, in this case, in the reset phase U1, the potentials of the first node N1 and the second node N2 are the same, and the potential difference between the two terminals of the storage sub-circuit 30 is zero; alternatively, the initialization signals at the respective initialization signal terminals may be different, in this case, in the reset phase U1, the potentials of the first node N1 and the second node N2 are different, and the potential difference between the two terminals of the storage sub-circuit 30 is not zero. Neither of the two situations will affect the compensation phase U2.

Further, in some embodiments, as shown in fig. 8D and 9D, the pixel circuit 101 includes the first, second, and

third initialization sub-circuits

71, 72, 73 described above. These three initialization sub-circuits all operate in the reset phase of the image frame F, and therefore, the first initialization sub-circuit 71, the second initialization sub-circuit 72, and the third initialization sub-circuit 73 can be set to have the same on-time to simplify the timing control process of the signals.

For example, the first reset signal terminal Rst1, the second reset signal terminal Rst2 and the third reset signal terminal Rst3 may be the same reset signal terminal Rst, so that the first initialization sub-circuit 71, the second initialization sub-circuit 72 and the third initialization sub-circuit 73 may be simultaneously turned on for the same turn-on time. The reset signal terminal RST is coupled to a reset signal line L _RST In this way, the number of signal lines in the display substrate 100 can be simplified, so that the display substrate 100 has a looser wiring space, so as to realize the display device 200 with higher resolution.

Also, in some embodiments, in the case that the pixel circuit 101 includes the first initialization sub-circuit 71, the second initialization sub-circuit 72, and the third initialization sub-circuit 73, the first initialization signal terminal Init1, the second initialization signal terminal Init2, and the third initialization signal terminal Init3 may be the same initialization signal terminal Init, so as to omit a reference voltage terminal (Vref) in the pixel circuit provided in the related art, so as to simplify a timing control process of signals. The initialization signal terminal INIT is coupled to an initialization signal line L _INIT As such, the number of signal lines in the display substrate 100 can also be simplified, so thatThe display substrate 100 has a relatively loose wiring space in order to realize the display device 200 with higher resolution.

In the pixel circuit 101 provided in the embodiment of the present disclosure, the specific implementation manner of each sub-circuit is not limited to the above-described manner, and may be any implementation manner, for example, a conventional connection manner known to those skilled in the art, and a circuit that can implement the function of the pixel circuit 101 only by ensuring that each sub-circuit can implement the corresponding function, for example, a circuit that can provide the driving current I to the light emitting element L, is within the protection scope of the present disclosure. Also, the above examples or embodiments do not limit the scope of the present disclosure. In practical applications, a skilled person may select to use or not use one or more of the above sub-circuits according to circumstances, and various combination modifications based on the above sub-circuits do not depart from the principle of the present disclosure, and are not described in detail herein.

Fig. 10 is a circuit diagram of a pixel circuit provided in accordance with yet other embodiments. As shown in fig. 10, the specific structure of the pixel circuit 101 is as follows:

the drive sub-circuit 20 comprises a drive transistor DT. A control electrode of the driving transistor DT is coupled to the second node N2, a first electrode of the driving transistor DT is coupled to the first voltage terminal V1, and a second electrode of the driving transistor DT is coupled to the third node N3.

The first compensation sub-circuit 41 includes a first transistor M1. A control electrode of the first transistor M1 is coupled to the first control signal terminal Q1, a first electrode of the first transistor M1 is coupled to the first node N1, and a second electrode of the first transistor M1 is coupled to the first electrode of the light emitting element L.

The second compensation sub-circuit 42 includes a second transistor M2. A control electrode of the second transistor M2 is coupled to the second control signal terminal Q2, a first electrode of the second transistor M2 is coupled to the third node N3, and a second electrode of the second transistor M2 is coupled to the second node N2.

The first initialization sub-circuit 71 includes a third transistor M3. A control electrode of the third transistor M3 is coupled to the first reset signal terminal Rst1, a first electrode of the third transistor M3 is coupled to the first initialization signal terminal Init1, and a second electrode of the third transistor M3 is coupled to the first node N1.

The second initialization sub-circuit 72 includes a fourth transistor M4. A control electrode of the fourth transistor M4 is coupled to the second reset signal terminal Rst2, a first electrode of the fourth transistor M4 is coupled to the second initialization signal terminal Init2, and a second electrode of the fourth transistor M4 is coupled to the second node N2.

The third initialization sub-circuit 73 includes a fifth transistor M5. A control electrode of the fifth transistor M5 is coupled to the third reset signal terminal Rst3, a first electrode of the fifth transistor M5 is coupled to the third initialization signal terminal Init3, and a second electrode of the fifth transistor M5 is coupled to the first electrode of the light emitting element L.

The data writing sub-circuit 10 includes a sixth transistor M6. A control electrode of the sixth transistor M6 is coupled to the Scan signal terminal Scan, a first electrode of the sixth transistor M6 is coupled to the Data signal terminal Data, and a second electrode of the sixth transistor M6 is coupled to the first node N1.

The light emission control sub-circuit 50 includes a seventh transistor M7. A control electrode of the seventh transistor M7 is coupled to the enable signal terminal EM, a first electrode of the seventh transistor M7 is coupled to the third node N3, and a second electrode of the seventh transistor M7 is coupled to the first electrode of the light emitting element L.

The potential holding sub-circuit 60 includes a first capacitor C1. A first terminal of the first capacitor C1 is coupled to the first node N1, and a second terminal of the first capacitor C1 is coupled to the first voltage terminal V1.

The storage sub-circuit 30 includes a second capacitor C2. A first terminal of the second capacitor C2 is coupled to the first node N1, and a second terminal of the second capacitor C2 is coupled to the second node N2.

Since the first capacitor C1 only needs to hold the potential of the first node N1, and does not need to have a large capacitance, the capacitance of the first capacitor C1 may be smaller than that of the second capacitor C2 in some examples.

Thus, some embodiments provide the above-described pixel circuit 101 with a structure of "8T 2C". Here, "T" denotes a transistor, and the preceding number thereof denotes the number of transistors in the pixel circuit 101; "C" denotes a capacitor, and the preceding numbers thereof denote the number of capacitors in the pixel circuit 101. The remaining transistors other than the driving transistor DT are switching transistors.

Fig. 11 is a circuit diagram of a pixel circuit provided in accordance with yet other embodiments. As shown in fig. 11, in the pixel circuit 101, the first control signal terminal Q1 coupled to the first compensation sub-circuit 41 and the second control signal terminal Q2 coupled to the second compensation sub-circuit 42 may be the same control signal terminal Q. Thus, the first control signal received at the first control signal terminal Q1 and the second control signal received at the second control signal terminal Q2 are the same control signal V _Q 。

Similarly, the first reset signal terminal Rst1 coupled to the first initialization sub-circuit 71, the second reset signal terminal Rst2 coupled to the second initialization sub-circuit 72, and the third reset signal terminal Rst3 coupled to the third initialization sub-circuit 73 may be the same reset signal terminal Rst. In this way, the first reset signal received at the first reset signal terminal Rst1, the second reset signal received at the second reset signal terminal Rst2, and the third reset signal received at the third reset signal terminal Rst3 are the same reset signal Rst.

Similarly, the first initialization signal terminal Init1 coupled to the first initialization sub-circuit 71, the second initialization signal terminal Init2 coupled to the second initialization sub-circuit 72, and the third initialization signal terminal Init3 coupled to the third initialization sub-circuit 73 may be the same initialization signal terminal Init. In this way, the first initialization signal received at the first initialization signal terminal Init1, the second initialization signal received at the second initialization signal terminal Init2, and the third initialization signal received at the third initialization sub-circuit 73 are the same initialization signal Vint.

As such, the number of signal lines in the display substrate 100 may be significantly simplified, so that the display substrate 100 has a looser wiring space, so as to realize the display device 200 with higher resolution.

The specific structure and the connection relationship between each sub-circuit in the pixel circuit 101 shown in fig. 11 can refer to the foregoing description of the pixel circuit 101 shown in fig. 10, and will not be described herein again.

In the pixel circuit 101 provided in the above embodiment, each Transistor may be a Thin Film Transistor (TFT), a Field Effect Transistor (FET), or another switching device with the same characteristics, which is not limited in the embodiments of the present disclosure.

In some embodiments, the control electrode of each transistor in the pixel circuit 101 is a gate electrode of the transistor, the first electrode is one of a source electrode and a drain electrode of the transistor, and the second electrode is the other of the source electrode and the drain electrode of the transistor. Since the source and drain of the same transistor may be symmetrical in structure, the source and drain thereof may not be differentiated in structure, that is, the first and second poles of the transistor in the embodiment of the present disclosure may not be differentiated in structure.

Illustratively, in the case where the transistor is a P-type transistor, such as a P-type Metal Oxide Semiconductor field effect transistor (PMOS), the first pole of the transistor is a source and the second pole is a drain. Illustratively, in the case where the transistor is an N-type transistor, such as an N-type Metal Oxide Semiconductor (NMOS), the first pole of the transistor is a drain and the second pole is a source.

In some embodiments, as shown in fig. 10 and 11, the transistors in the pixel circuit 101 are all P-type transistors, for example, all P-type transistors are PMOS, that is, each transistor is turned on in response to a low-level signal received on its control electrode, that is, the condition for turning on each transistor is that the active-level signal is a low-level signal.

Fig. 12 is a signal timing diagram of the pixel circuit shown in fig. 11. Hereinafter, the operation of one pixel circuit 101 at different stages in one image frame F will be described by taking the case where each transistor in the pixel circuit 101 is a P-type transistor as an example.

Table 1 shows the voltages V of the first node N1 in different phases _N1 And a voltage V of a second node N2 _N2 And the operating state of the pixel circuit 101 at different stages.

TABLE 1

Fig. 13A is a schematic diagram illustrating an operation state of the pixel circuit shown in fig. 11 in a reset phase. As shown in fig. 12 and 13A, in the reset phase U1 of the image frame F, the reset signal RST provided from the reset signal terminal RST is a low level signal, and the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are simultaneously turned on.

The initialization signal Vint provided by the initialization signal terminal INIT is a low level signal. The third transistor M3 transmits the initialization signal Vint to the first node N1 (the transmission path is shown by a dotted arrow a in fig. 13A) to initialize the potential of the first node N1, so that the potential of the first node N1 is restored to the Vint state. The second transistor M2 transmits the initialization signal Vint to the second node N2 (the transmission path is shown by a dotted arrow b in fig. 13A) to initialize the potential of the second node N2, so that the potential of the second node N2 is restored to the Vint state. The fifth transistor M5 transmits the initialization signal Vint to the first pole of the light emitting element L (the transmission path is shown by a dotted arrow c in fig. 13A) to initialize the first pole of the light emitting element L.

Thus, in the reset phase U1, the first node N1, the second node N2, the first electrode of the light emitting element L, the first capacitor C1, and the second capacitor C2 are all reset.

Fig. 13B is a schematic diagram illustrating an operation state of the pixel circuit shown in fig. 11 in a compensation phase. As shown in fig. 12 and 13B, upon entering the compensation phase U2 of the image frame F, the voltage V due to the second node N2 _N2 Vint state is maintained, thereby turning on the driving transistor DT. In the compensation phase U2, the control signal V provided by the control signal terminal Q _Q The first transistor M1 and the second transistor M2 are simultaneously turned on for a low level signal. Since the second transistor M2 is turned on, the line between the second node N2 and the third node N3 is turned on, that is, the line between the control electrode and the second electrode of the driving transistor DT is turned on, so that the driving transistor DT is turned into a diode connection state in the compensation phase U2. This is achieved byA first voltage V from a first voltage terminal V1 _DD Is transmitted to the second node N2 through the turned-on driving transistor DT and the second transistor M2 (the transmission path is shown by a dotted arrow d in fig. 13B), so that the potential of the second node N2 rises. Due to the bootstrap effect of the second capacitor C2 coupled between the second node N2 and the first node N1, the potential of the first node N1 is driven to rise accordingly (as shown by the dotted arrow e in fig. 13B). Subsequently, the charge of the first node N1 flows into the first pole of the light emitting element L through the first transistor M1 (the transmission path is shown by the dotted arrow f in fig. 13B), thereby compensating the threshold voltage V of the light emitting element L _{oled_th} 。

Finally, the voltage V of the second node N2 in the steady state _N2 Is a V _DD + Vth, voltage V at which the first node N1 is selected in a stable state _N1 Is a V _SS +V _{oled_th} 。

Fig. 13C is a schematic diagram illustrating an operation state of the pixel circuit shown in fig. 11 during a writing phase. As shown in fig. 12 and 13C, in the writing phase U3 of the image frame F, the Scan signal S provided by the Scan signal terminal Scan is a low level signal, the sixth transistor M6 is turned on, and the Data signal V received at the Data signal terminal Data is transmitted _data Writing into the first node N1 (transmission path is shown by the dotted arrow g in FIG. 13C) causes the voltage V of the first node N1 _N1 Is directly changed into V _data . Due to the bootstrap effect of the second capacitor C2, the potential of the second node N2 changes (as shown by the dotted arrow h in fig. 13C), and finally, the voltage V of the second node N2 _N2 Is stabilized to V _data +V _DD +Vth-V _SS -V _{oled_th} 。

Fig. 13D is a schematic diagram of an operation state of the pixel circuit shown in fig. 11 in a light-emitting stage. As shown in fig. 12 and 13D, in the lighting phase U4 of the image frame F, the voltages of the first node N1 and the second node N2 are the same as in the compensation phase U2. The enable signal EM provided by the enable signal terminal EM is a low level signal, and the seventh transistor M7 is turned on. Thus, the first voltage V _DD After transmission of the driving transistor DT, the driving transistor DT generates a driving current I =1/2 · μ · C _ox ·W/L·(V _SS +V _{oled_th} -V _data ) ² The driving current I is transmitted to the light emitting element L through the seventh transistor M7 (the transmission path is shown by a dotted arrow I in fig. 13D), and the light emitting element L is driven to emit light.

Since the threshold voltage V of the light emitting element L is increased with the increase of the use time of the light emitting element L _{oled_th} The absolute value of Vgs of the driving transistor DT is raised, i.e. pulled up (since Vgs of the P-type transistor is a negative voltage, typically-5V to-10V, it can also be understood that Vgs is lowered, i.e. Vgs is more negative), thereby driving the driving current I flowing through the light emitting element L to increase accordingly.

Fig. 14 is a feedback schematic diagram of two pixel circuits provided in one embodiment. As shown in fig. 14, the Data signal terminal Data is coupled to the positive electrode of an Amplifier (AMP) equivalent to a transistor in the pixel circuit, and the power supply voltage terminal VDD and the first electrode of the light emitting element L are coupled to the two negative electrodes of the Amplifier AMP. The second pole of the light emitting device L is coupled to the reference voltage terminal VSS.

As shown in fig. 14 (a), in a feedback method of a pixel circuit, in order to feed back a voltage on the surface of the first electrode (typically, the anode electrode) of the light emitting element L to the pixel circuit for compensation, the voltage is fed back to the Data signal V supplied from the Data signal terminal Data _data The above.

As shown in fig. 14 (b), in another feedback method of the pixel circuit, in order to feed back the voltage on the surface of the first electrode (usually, the anode) of the light emitting element L to the pixel circuit for compensation, the voltage is fed back to the voltage V provided from the power supply voltage terminal VDD _DD The above.

Because the voltage V provided by the power supply voltage end VDD at present _DD Is a dc voltage, no feedback can be formed. Therefore, referring to the feedback principle shown in (a) of fig. 14, the above-described pixel circuit 101 provided by the embodiment of the present disclosure adopts the compensation principle of feeding back the voltage of the first pole surface of the light emitting element L to the data signal V _data The above.

Fig. 15 is a diagram comparing the feedback principle of a pixel circuit provided according to some embodiments with the feedback principle of a pixel circuit provided by an aspect. As shown in fig. 15, the Data signal terminal Data is coupled to a positive electrode of an Amplifier (AMP) equivalent to a transistor in the pixel circuit, and the power supply voltage terminal VDD (i.e., the first voltage terminal V1 in the embodiment of the present disclosure) and a first electrode of the light emitting element L are coupled to two negative electrodes of the Amplifier AMP. The second pole of the light emitting device L is coupled to the reference voltage terminal VSS (i.e. the second voltage terminal V2 in the embodiment of the disclosure).

The manner of feedback may be divided into a first type of feedback as shown in (a) of fig. 15 and a second type of feedback as shown in (b) of fig. 15.

In the first feedback mode, a capacitor C for storing a voltage is coupled between the Data signal terminal Data and the first pole of the light emitting element L. The voltage of the first pole surface of the light emitting element L is fed back to the Data signal V provided by the Data signal terminal Data in the light emitting phase _data The feedback path is shown by a dotted arrow in (a) in fig. 15. When the transistors in the pixel circuit are mainly P-type transistors (for example, PMOS), since the amplifier AMP equivalent to these transistors is a reverse amplification circuit, when the voltage of the first electrode surface of the light emitting element L is a forward voltage, negative feedback is finally caused, that is, the voltage of the amplifier AMP is reduced, which reduces the current flowing through the light emitting element L, and thus the problem of low light emission luminance of the light emitting element L due to aging cannot be solved.

The pixel circuit 101 provided by the embodiment of the present disclosure adopts a second feedback manner, that is: as shown by a dotted arrow (1) in fig. 15 (b), the voltage of the first electrode surface of the light-emitting element L is written into the second capacitor C2; as shown by the dotted arrow (2) in fig. 15 (b), the voltage on the first electrode surface of the light emitting element L and the V of the data signal are further converted _data The voltages are written together to the control electrode of the drive transistor DT.

In this way, in the pixel circuit 101 provided by the embodiment of the present disclosure, the voltage on the first electrode surface of the light emitting element L is fed back to the second capacitor C2, and then V is obtained by using the bootstrap effect of the capacitor _data And V _{oled_th} Simultaneously writing in the control electrode of the driving transistor DT to finally form a positive feedback circuit, thereby improving the current flowing through the light-emitting element L and realizing the use of the light-emitting element LThe compensation effect of the life.

Fig. 16 is a schematic diagram of a simulation model of the pixel circuit shown in fig. 11. Fig. 17 is a schematic diagram of a simulation signal of the pixel circuit shown in fig. 11.

In fig. 16, a first voltage V is provided from a first voltage terminal V1 _DD Is 4.6V, and the second voltage V provided by the second voltage terminal V2 _SS Data signal V supplied for-3V, data signal terminal Data _data The initialization signal Vint provided by the initialization signal terminal INIT is-3V, the capacitance of the first capacitor C1 is 0.05 picofarad (pf), the capacitance of the second capacitor C2 is 0.1 picofarad (pf), each transistor is PMOS, the threshold voltage Vth of the driving transistor DT is set to-2V, and the threshold voltage V of the analog light emitting element L is-3V _{oled_th} The pressure was set to 0.4V at the beginning of use.

As shown in fig. 17, during the simulation, the potentials of the first node N1 and the second node N2 are both-3V (i.e., a voltage equal to the initialization signal Vint) during the reset phase U1. During the compensation phase U2, the voltage V of the second node N2 _N2 Is 2.6V, equal to V _DD + Vth (i.e., 4.6V + (-2V)), the voltage V of the first node N1 _N is-2.6V, equal to V _SS +V _{oled_th} (i.e., -3V + 0.4V). In the write phase U3, the voltages of the first node N1 and the second node N2 are simultaneously decreased.

Obviously, through the simulation process, the respective potentials of the first node N1 and the second node N2 in the reset phase U1, the compensation phase U2, and the write phase U3 are verified, and it is fully explained that the pixel circuit 101 provided by the embodiment of the present disclosure compensates the driving current I flowing through the light emitting element L, and the service life of the light emitting element L is prolonged.

Fig. 18 is a block diagram of a display substrate according to further embodiments. As shown in fig. 18, the display substrate 100 includes a plurality of sub-pixels P disposed in the AA region, each of the sub-pixels P including a pixel circuit 101. In the case where the plurality of sub-pixels P are arranged in an array, the pixel circuits 101 arranged in a row in the X direction are referred to as the same row of pixel circuits 101, and the pixel circuits 101 arranged in a row in the Y direction are referred to as the same column of pixel circuits 101.

In this case, the sameThe initialization signal terminal INIT of the row pixel circuit 101 may be coupled to the same initialization signal line L extending along the X direction (or substantially extending along the X direction) _INIT The reset signal terminals RST of the pixel circuits 101 in the same row may be coupled to the same reset signal line L extending along the X direction (or substantially extending along the X direction) _RST The control signal terminals Q of the pixel circuits 101 in the same row may be coupled to the same control signal line L extending along the X direction (or substantially extending along the X direction) _Q The Scan signal terminals Scan of the pixel circuits 101 in the same row may be coupled to the Scan signal lines SL extending along the X direction (or extending substantially along the X direction), and the enable signal terminals EM of the pixel circuits 101 in the same row may be coupled to the enable signal lines L extending along the X direction (or extending substantially along the X direction) _EM 。

Similarly, the Data signal terminals Data of the pixel circuits 101 in the same column may be coupled to the Data signal lines DL extending along the Y direction (or substantially extending along the Y direction), and the first voltage terminals V1 of the pixel circuits 101 in the same column may be coupled to the first power lines L extending along the Y direction (or substantially extending along the Y direction) _V1 The second voltage terminal V2 of the pixel circuits 101 in the same column may be coupled to a second power line L extending along the Y direction (or substantially extending along the Y direction) _V2 。

Thus, when the plurality of pixel circuits 101 are arranged in an array, the display substrate 100 can have a relatively loose wiring space, so as to achieve a higher resolution of the display device 200.

In some examples, the display substrate 100 further includes one scan driving circuit located in the peripheral region W. The scan driving circuit can be connected with the initialization signal line L _INIT And a reset signal line L _RST And a control signal line L _Q A scan signal line SL and an enable signal line L _EM Coupled to the pixel circuit 101, and respectively transmitting the initialization signal Vint, the reset signal Rst and the control signal V to the pixel circuit through the signal lines _Q A scan signal S and an enable signal Em.

Illustratively, the scan driving circuit is a Gate Driver on Array (GOA) driving circuit.

In other examples, the display substrate 100 further includes a plurality of scan driving circuits in the peripheral region W. A part of the plurality of scan driving circuits is located at one of opposite sides of the display area AA, and another part is located at the other of the opposite sides of the display area AA. Multiple scan driving circuits can be connected to the initialization signal line L _INIT And a reset signal line L _RST And a control signal line L _Q A scan signal line SL and an enable signal line L _EM Coupled to the pixel circuit 101, and respectively transmitting the initialization signal Vint, the reset signal Rst and the control signal V to the pixel circuit through the signal lines _Q Scan signal S, and enable signal Em.

Illustratively, each scan driving circuit is a GOA (Gate Driver on Array) driving circuit.

The embodiment of the present disclosure does not limit the specific structure of the scan driving circuit (e.g., GOA) as long as it can transmit a corresponding signal to the pixel circuit 101.

Fig. 19 is a schematic Layout (Layout) of a display substrate according to some embodiments. Fig. 20A to 20D are schematic layout views of the layers in fig. 19.

The display substrate 100 illustrated in fig. 19 has a pixel circuit 101 as illustrated in fig. 11.

Note that, for convenience of illustration, fig. 19 illustrates only one pixel circuit 101 located on the substrate 100a and a portion where each signal line passes through a region where the pixel circuit 101 is located (i.e., a sub-pixel region), and does not illustrate the remaining pixel circuits 101 and the entire signal lines.

As shown in fig. 20A, a semiconductor layer Act is formed over a substrate 100A. Illustratively, a polysilicon (p-si) film may be formed using a Chemical Vapor Deposition (CVD) process, and the polysilicon film may be subjected to a first patterning process to form one semiconductor layer Act in each sub-pixel region.

A gate insulating layer covering the semiconductor layer Act is formed on the substrate 100a. Illustratively, the gate insulating layer is made of at least one insulating material of silicon nitride, silicon oxide, and silicon oxynitride using a CVD process.

As shown in fig. 20B, a first conductor layer G1 is formed on the gate insulating layer (not illustrated in fig. 20B). For example, a metal thin film made of copper (Cu), aluminum (Al) may be formed using a sputtering process, and the first conductor layer G1 in each sub-pixel region may be formed by performing a second patterning process on the metal thin film.

In the same sub-pixel region, a portion of the first conductor layer G1 having an overlap region with the orthographic projection of the semiconductor layer Act on the substrate 100a forms a control electrode of each transistor.

That is, the first conductor layer G1 includes: a control electrode DTg of the driving transistor DT, a control electrode M1g of the first transistor M1, a control electrode M2g of the second transistor M2, a control electrode M3g of the third transistor M3, a control electrode M4g of the fourth transistor M4, a control electrode M5g of the fifth transistor M5, a control electrode M6g of the sixth transistor M6, and a control electrode M7g of the seventh transistor M7.

Since the second terminal of the second capacitor C2 and the control electrode DTg of the driving transistor DT are both coupled to the second node N2, that is, the second terminal of the second capacitor C2 and the control electrode DTg of the driving transistor DT are coupled together, the control electrode DTg of the driving transistor DT can be multiplexed as the second terminal of the second capacitor C2 (i.e., the lower electrode plate of the second capacitor C2) as one second conductor pattern R2, so as to simplify the layout of the pixel circuit 101.

The first conductor layer G1 further includes: a first conductor pattern R1 not connected to the second conductor pattern R2, the first conductor pattern R1 being a second terminal of the first capacitor C1 (i.e., a lower electrode plate of the first capacitor C1).

The first conductor layer G1 further includes: reset signal line L _RST A control signal line L passing through the sub-pixel region _Q A portion passing through the sub-pixel region, a portion of the scan signal line SL passing through the sub-pixel region, and an enable signal line L _EM Through a portion of the sub-pixel region.

Reset signal line L _RST With the control electrode M3g of the third transistor M3, the control electrode M4g of the fourth transistor M4, andthe control electrode M5g of the fifth transistor M5 is connected to be a unitary structure.

Control signal line L _Q The gate M1g of the first transistor M1 and the gate M2g of the second transistor M2 are connected to form an integrated structure.

The scanning signal line SL is integrally connected to the gate M6g of the sixth transistor M6.

Enable signal line L _EM And a control electrode M7g of the seventh transistor M7.

The portion of the semiconductor layer Act having an overlap region of the orthographic projection on the substrate 100a and the orthographic projection of the control electrode of each transistor on the substrate 100a forms an active layer of the corresponding transistor (i.e., a channel region when the transistor is turned on).

With the first conductor layer G1 as a Mask, ion implantation processing is performed on a region of the semiconductor layer Act other than the respective active layers (i.e., a region of the semiconductor layer Act not covered with the first conductor layer G1) so that the region becomes a conductor. The conductive region Act-a may be a first pole or a second pole of each transistor, or may be a part of the first pole or a part of the second pole of each transistor. The first and second poles for each transistor will be explained in detail in the following description.

Note that although the gate insulating layer is provided between the semiconductor layer Act and the first conductor layer G1, by controlling parameters of ion implantation (for example, a speed of ion implantation), ions can be made to pass through the gate insulating layer into a region of the semiconductor layer Act which is not covered with the first conductor layer G1, thereby making the region conductive.

A first interlayer insulation covering the above-described respective structures is formed on the substrate 100a. Illustratively, the first interlayer insulating layer is made of at least one insulating material of silicon nitride, silicon oxide, and silicon oxynitride using a CVD process.

As shown in fig. 20C, a second conductor layer G2 is formed on the first interlayer insulating layer (not illustrated in fig. 20C). For example, a metal thin film made of copper (Cu), aluminum (Al) may be formed using a sputtering process, and the second conductor layer G2 in each sub-pixel region may be formed by performing a third patterning process on the metal thin film.

The second conductor layer G2 includes a third conductor pattern R3. An orthogonal projection of the third conductor pattern R3 on the substrate 100a has an overlapping area with an orthogonal projection of the first conductor pattern R1 in the first conductor layer G1 on the substrate 100a to form the first capacitor C1. An orthogonal projection of the third conductor pattern R3 on the substrate 100a has an overlapping area with an orthogonal projection of the second conductor pattern R2 on the substrate 100a to form the second capacitor C2.

Since the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are both coupled to the first node N1, that is, the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are coupled together, the first terminal of the first capacitor C1 (i.e., the upper electrode plate of the first capacitor C1) and the first terminal of the second capacitor C2 (i.e., the upper electrode plate of the second capacitor C2) may be connected to form an integral structure, so as to simplify the layout of the pixel circuit 101.

In other examples, the first end of the first capacitor C1 and the first end of the second capacitor C2 may be two independent electrode plates, which is not limited by the embodiments of the disclosure.

The third conductor pattern R3 has an opening O, and an orthogonal projection of the opening O on the substrate 100a and an orthogonal projection of the second conductor pattern R2 below on the substrate 100a have an overlapping region, so that a second pole of the fourth transistor M4 to be formed subsequently is coupled to the second terminal of the second capacitor C2, in a manner that will be described in detail in the following description.

The second conductor layer G2 further includes an initialization signal line L not connected to the third conductor pattern R3 _INIT 。

A second interlayer insulation covering the above-described respective structures is formed on the substrate 100a. Illustratively, the second interlayer insulating layer is made of at least one insulating material of silicon nitride, silicon oxide, and silicon oxynitride using a CVD process.

As shown in fig. 20D, a third conductor layer SD is formed on the second interlayer insulating layer (not illustrated in fig. 20D). For example, a sputtering process may be used to form a metal thin film made of copper (Cu) or aluminum (Al), and the metal thin film may be subjected to a fourth patterning process to form the third conductor layer SD in each sub-pixel region.

The third conductor layer SD includes: first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth connection patterns SD-1, SD-2, SD-3, SD-4, SD-5, SD-6, SD-7, SD-8, and SD-9, a data signal line DL, a first power line L _V1 And a second power supply line L _V2 (not shown in FIG. 20D).

As shown in fig. 19 and 20D, the respective connection patterns described above and the coupling relationship between each connection pattern and the corresponding circuit structure will be specifically described below.

The first and second poles DT-1 and DT-2 of the driving transistor DT are portions of the conductive region Act-a located on both sides of the control electrode DTg of the driving transistor.

First power line L _V1 The first electrode DT-1 of the driving transistor DT is connected through a via hole H15 penetrating the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. In this way, the coupling between the first pole DT-1 of the driving transistor DT and the first voltage terminal V1 is achieved (the first voltage terminal V1 is coupled to the first power line LV 1). And, the first power line L _V1 And also connected to the first conductor pattern R1 (i.e., the second end of the first capacitor C1) through a via hole H16 penetrating the first interlayer insulating layer and the second interlayer insulating layer. Thus, the coupling between the second terminal of the first capacitor C1 and the first voltage terminal V1 is realized (the first voltage terminal V1 is coupled to the first power line L) _V1 )。

The first pole M6-1 and the second pole M6-2 of the sixth transistor M6 are portions of the region Act-a that is made conductive and located on both sides of the control pole M6g of the sixth transistor M6.

The first connection pattern SD-1 is connected to the data signal line DL in an integrated structure, and the first connection pattern SD-1 is connected to the first pole M6-1 of the sixth transistor M6 through a via hole H13 penetrating the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. Thus, the coupling between the first pole M6-1 of the sixth transistor M6 and the Data signal terminal Data (the Data signal terminal Data is coupled to the Data signal line DL) is realized.

The second connection pattern SD-2 is connected to the second pole M6-2 of the sixth transistor M6 through a via hole H12 penetrating the gate insulating layer, the first interlayer insulating layer, and the second connection pattern SD-2 is also connected to the third conductor pattern R3 (i.e., the first end of the first capacitor C1 and the first end of the second capacitor C2) through a via hole H11 penetrating the second interlayer insulating layer. In this way, a coupling between the second pole M6-2 of the sixth transistor M6 and the first terminal of the first capacitor C1, the first terminal of the second capacitor C2 is achieved.

The first pole M7-1 and the second pole M7-2 of the seventh transistor M7 are portions of the region Act-a that is made conductive and located on both sides of the control pole M7g of the seventh transistor M7.

The first pole M1-1 and the second pole M1-2 of the first transistor M1 are portions of the region Act-a made of conductor, which are located on both sides of the control pole M1g of the first transistor M1.

The third connection pattern SD-3 is connected to the second pole M7-2 of the seventh transistor M7 through a via hole H14 penetrating the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, and the third connection pattern SD-3 is also connected to the second pole M1-2 of the first transistor M1 through a via hole H19 penetrating the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. In this way, a coupling between the second pole M7-2 of the seventh transistor M7 and the second pole M1-2 of the first transistor M1 is achieved.

The first pole M5-1 and the second pole M5-2 of the fifth transistor M5 are portions of the conductive region Act-a located on both sides of the control pole M5g of the fifth transistor M5.

The fourth connection pattern SD-4 passes through the via hole H17 penetrating the second interlayer insulating layer and the initialization signal line L _INIT And, the fourth connection pattern SD-4 is also connected to the first pole M5-1 of the fifth transistor M5 through a via hole H18 penetrating the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. Thus, the coupling between the first electrode M5-1 of the fifth transistor M5 and the initialization signal terminal INIT is realized (the initialization signal terminal INIT is coupled to the initialization signal line L) _INIT )。

The first pole M3-1 and the second pole M3-2 of the third transistor M3 are portions of the region Act-a made of conductor, which are located on both sides of the control pole M3g of the third transistor M3.

The fifth connection pattern SD-5 passes through the via hole H7 penetrating the second interlayer insulating layer and the initialization signal line L _INIT And, the fifth connection pattern SD-5 is also connected to the first pole M3-1 of the third transistor M3 through a via hole H8 penetrating the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. Thus, the coupling between the first pole M3-1 of the third transistor M3 and the initialization signal terminal INIT is realized (the initialization signal terminal INIT is coupled to the initialization signal line L) _INIT )。

The first pole M4-1 and the second pole M4-2 of the fourth transistor M4 are portions of the region Act-a that is made conductive and located on both sides of the control pole M4g of the fourth transistor M4.

The sixth connection pattern SD-6 passes through the via hole H1 penetrating the second interlayer insulating layer and the initialization signal line L _INIT And, the sixth connection pattern SD-6 is also connected to the first pole M4-1 of the fourth transistor M4 through a via hole H2 penetrating the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. Thus, the coupling between the first pole M4-1 of the fourth transistor M4 and the initialization signal terminal INIT is realized (the initialization signal terminal INIT is coupled to the initialization signal line L) _INIT )。

The seventh connection pattern SD-7 is connected to the second pole M4-2 of the fourth transistor M4 through a via hole H3 penetrating the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, and the seventh connection pattern SD-7 is also connected to the second conductor pattern R2 (the second end of the second capacitor C2) through a via hole H4 penetrating the first interlayer insulating layer and the second interlayer insulating layer. In this way, a coupling between the second pole M4-2 of the fourth transistor M4 and the second terminal of the second capacitor C2 is achieved. The orthographic projection of the via hole H4 on the substrate 100a is located within the range of the orthographic projection of the opening O of the third conductor pattern R3 on the substrate 100a, so as to avoid the seventh connecting pattern SD-7 contacting the third conductor pattern R3 to generate signal confusion.

The first pole M2-1 and the second pole M2-2 of the second transistor M2 are portions of the region Act-a that is made conductive and located on both sides of the control pole M2g of the second transistor M2.

The eighth connection pattern SD-8 is connected to the second pole M3-2 of the third transistor M3 through a via hole H9 penetrating the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, the eighth connection pattern SD-8 is also connected to the first pole M1-1 of the first transistor M1 through a via hole H20 penetrating the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, and the eighth connection pattern SD-8 is also connected to the third conductor pattern R3 (i.e., the first end of the second capacitor C2 and the first end of the first capacitor C1) through a via hole H10 penetrating the second interlayer insulating layer. In this way, a coupling between the second pole M3-2 of the third transistor M3, the first pole M1-1 of the first transistor M1, the first terminal of the second capacitor C2 and the first terminal of the first capacitor C1 is achieved.

In addition, in order to avoid formation of a gate other than the "8T2C" structure required in the pixel circuit 101, the orthographic projection of the scanning signal line SL on the substrate 100a does not overlap the orthographic projection of the semiconductor layer Act on the substrate 100a. Therefore, when the scanning signal lines SL are formed, there may be portions of the scanning signal lines SL that are not connected to each other. The third conductor layer SD further includes a ninth connection pattern SD-9. The ninth connection pattern SD-9 is connected to the scan signal line SL through a via hole H5 penetrating the first and second interlayer insulating layers and a via hole H6 penetrating the first and second interlayer insulating layers, thereby coupling portions of the scan signal line SL that are not connected to each other together so that the scan signal line SL can transmit a scan signal.

A planarization layer (typically made of an organic insulating material, not shown in fig. 19) covering the above structures is formed on the display substrate 100 shown in fig. 19, and the light emitting element L coupled to the pixel circuit 101 may be formed on the planarization layer.

The light emitting element L is, for example, a top emission type OLED, that is, emits light upward with respect to the substrate 100a, and the emitted light does not pass through the substrate 100a. The first pole (e.g., anode) of the OLED is connected to the second pole M7-2 of the seventh transistor M7 by a via through the planar layer, the via of the planar layer corresponding in position to the aforementioned via H14, i.e., in a direction away from the substrate 100a, with the via H14 below, and the via of the planar layer connecting the first pole of the OLED to the second pole M7-2 of the seventh transistor M7 above the via H14.

The OLED comprises a light emitting layer and a second pole, which are sequentially distant from the first pole. In the case where the first pole is an anode, the second pole is a cathode. In this case, in some examples, the OLED may further include a hole transport layer and/or a hole injection layer between the light emitting layer and the first pole; in some examples, the OLED may further include an electron transport layer and/or an electron injection layer between the light emitting layer and the second pole.

In some examples, the display substrate 100 includes a plurality of pixel circuits 101, and the second poles of the light emitting elements L coupled to the plurality of pixel circuits 101 may be connected in an integrated structure, i.e., form one electrode layer, to simplify the structure of the display substrate 100.

Since the layout is limited, the light-emitting element L is not illustrated in fig. 19.

It should be understood that in describing the coupling relationship between the above structures, a description is used that "a certain structure is connected to another structure through a via penetrating one or more insulating layers", and in this description, the orthographic projection of the structure on the substrate 100a necessarily has an overlapping region with the orthographic projection of the other structure on the substrate 100a, so that the structure located above is in direct contact with, i.e., connected to, the other structure through the via.

It should be noted that the "patterning process" mentioned in the above embodiments may be a process of processing a film layer (one or more film layers) to form a specific pattern or patterns, and a typical patterning process is a process of exposing a partial region of a photoresist covering the film layer by using a Mask (Mask), developing the exposed portion of the photoresist, etching the exposed portion of the film layer, and removing the remaining photoresist to obtain a desired pattern.

In some embodiments, as shown in fig. 3, the display device 200 provided by the embodiments of the present disclosure further includes a driving chip 210. The driving chip 210 is coupled to the display substrate 100. The driving chip 210 is configured to supply signals required to drive the pixel circuit 101 in the display substrate 100 to the pixel circuit 101. For example, the driving chip 210 is a Driver Integrated Circuit (Driver IC).

Illustratively, the driving chip 210 may provide the initialization signal Vint, the reset signal Rst, and the control signal V to the pixel circuit 101 in the display substrate 100 _Q A scan signal S, an enable signal Em, a data signal Vdata, a first voltage V _DD And a second voltage V _SS Etc. necessary for driving the pixel circuit 101. In addition, the embodiment of the present disclosure does not limit the number of driving chips in the display device 200 as long as signals required for driving the pixel circuit 101 can be provided.

In some examples, the display device 200 further includes a thin film encapsulation layer or an encapsulation substrate disposed on the display substrate 100 to isolate the light emitting elements L in the display substrate 100 from moisture and oxygen in the external environment.

In some examples, the light emitted by the light emitting elements L in the display substrate 100 is white light, in which case, the display device 200 further includes a color filter substrate disposed on the light emitting side of the display substrate 100 to realize that the display device displays a color image. The light conversion layer in the color filter substrate may be a color filter layer and/or a quantum dot light emitting layer, which is not limited in this embodiment of the disclosure.

Fig. 21 is a flow chart of a driving method of a pixel circuit according to some embodiments. The driving method is applied to the pixel circuit 101, and the detailed structure of the pixel circuit 101 is not described herein. As shown in fig. 21, the driving method includes steps S2 to S4.

S2, during a compensation phase U2 of an image frame F, the second compensation sub-circuit 42 responds to the second control signal received at the second control signal terminal Q2 to apply the first voltage V from the first voltage terminal V1 _DD And the threshold voltage Vth of the driving sub-circuit 20 is transmitted to the second node N2; the first compensation sub-circuit 41 responds to the first control signal received at the first control signal terminal Q1 to provide the second voltage V from the second voltage terminal V2 _SS And threshold voltage V of light emitting element L _{oled_th} To the first node N1.

Thus, during the compensation phase U2, the voltage V of the second node N2 _N2 ＝V _DD + Vth, voltage V of the first node N1 _N1 ＝V _SS +V _{oled_th} 。

S3, in the writing phase U3 of the image frame F, the Data writing sub-circuit 10 responds to the scanning signal received at the scanning signal terminal Scan, and the Data signal V received at the Data signal terminal Data _data The first node N1 is written.

S4, in a light-emitting stage U4 of the image frame F, the driving sub-circuit 20 responds to the voltage conduction of the second node N2 to generate a driving current I; the light emission control sub-circuit 50 outputs the driving current I transmitted to the third node N3 to the light emitting element L in response to the enable signal received at the enable signal terminal EM to drive the light emitting element L to emit light.

The drive current I = 1/2. Mu. C _ox ·W/L·(V _SS +V _{oled_th} -V _data ) ² 。

The driving current I finally flowing through the light emitting element L is not related to the threshold voltage Vth of the driving sub-circuit 20 but is related to the threshold voltage V of the light emitting element L _{oled_th} And (4) positively correlating. Thus, as the lifetime of the light-emitting element L increases, the light-emitting efficiency of the light-emitting element L decreases due to the aging of the material, and the threshold voltage V of the light-emitting element L _{oled_th} Will rise and the threshold voltage V will rise _{oled_th} The increase of the voltage level will drive the driving current I flowing through the light-emitting device L to increase correspondingly (in the case of the data signal V) _data Without change), i.e. compensation of the current of the light emitting element L is achieved.

In some embodiments, the pixel circuit 101 further comprises: at least one of the first, second and

third initialization sub-circuits

71, 72, 73. The first initialization sub-circuit 71 is coupled to the first reset signal terminal Rst1, the first initialization signal terminal Init1, and the first node N1. The second initialization sub-circuit 72 is coupled to the second reset signal terminal Rst2, the second initialization signal terminal Init2, and the second node N2. The third initialization sub-circuit 73 is coupled to the third reset signal terminal Rst3, the third initialization signal terminal Init3, and the first pole of the light emitting element L.

FIG. 22 is a flow chart of a method for driving a pixel circuit according to further embodiments. Before the compensation phase U2 of the image frame F, as shown in fig. 22, the driving method further comprises at least one of the following steps S11-S13:

s11, in the reset phase U1 of the image frame F, the first initialization sub-circuit 71 transmits the first initialization signal received at the first initialization signal terminal Init1 to the first node N1 in response to the first reset signal received at the first reset signal terminal Rst1 to initialize the potential of the first node N1.

Thus, in the reset phase U1, the data voltage V of the first node N1 in the previous image frame is cleared by the first initialization signal _data So that the potential of the first node N1 is initialized to avoid signal interference.

S12, in the reset phase U1 of the image frame F, the second initialization sub-circuit 72 transmits the second initialization signal received at the second initialization signal terminal Init2 to the second node in response to the second reset signal received at the second reset signal terminal Rst2 to initialize the potential of the second node N2.

Thus, in the reset phase U1, the voltage (V) of the second node N2 in the previous image frame is cleared by the second initialization signal _data +V _DD +Vth-V _SS -V _{oled_th} ) So that the potential of the second node N2 is initialized to avoid signal interference.

S13, in the reset phase U1 of the image frame F, the third initialization sub-circuit 73 transmits the third initialization signal received at the third initialization signal terminal Init3 to the first pole of the light emitting element L in response to the third reset signal received at the third reset signal terminal Rst3 to initialize the potential of the first pole of the light emitting element L.

In this way, in the reset phase U1, the third initialization sub-circuit 73 clears the voltage of the first electrode of the light-emitting element L, so that the potential of the first electrode of the light-emitting element L is initialized, the light-emitting element L is prevented from emitting light in a dark state due to the influence of the leakage current of the light-emitting control sub-circuit 50, and the display quality of the display device having the pixel circuit 101 is improved.

The driving method of the pixel circuit has the same beneficial effects as the pixel circuit, and the specific driving principle is not described herein again.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art will appreciate that changes or substitutions within the technical scope of the present disclosure are included in the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A display substrate, comprising:

a substrate;

a pixel circuit stack disposed on the substrate, the pixel circuit stack configured to form a pixel circuit; wherein the pixel circuit stack comprises a first conductor layer and a second conductor layer; the first conductor layer includes a first conductor pattern and a second conductor pattern that are not connected to each other; the second conductor layer is arranged on one side, far away from the substrate, of the first conductor layer and is insulated from the first conductor layer; the second conductor layer includes a third conductor pattern; an orthographic projection of the third conductor pattern on the substrate and an orthographic projection of the first conductor pattern on the substrate have an overlapping area to form a first capacitor; an orthographic projection of the third conductor pattern on the substrate and an orthographic projection of the second conductor pattern on the substrate have an overlapping area to form a second capacitor;

a light emitting element disposed on the substrate, the light emitting element coupled with the pixel circuit;

the pixel circuit comprises a data writing sub-circuit, a driving sub-circuit, a storage sub-circuit, a second compensation sub-circuit, a light-emitting control sub-circuit and a potential holding sub-circuit;

the data writing sub-circuit is coupled with the data signal terminal, the scanning signal terminal and the first node; the data write subcircuit is configured to write a data signal received at the data signal terminal to the first node in response to a scan signal received at the scan signal terminal;

the driving sub-circuit is coupled with a first voltage end, a second node and a third node; the driving sub-circuit is configured to generate a driving current in response to a voltage of the second node;

the storage sub-circuit is coupled between the first node and the second node; the storage sub-circuit is configured to store a voltage; the storage sub-circuit comprises the second capacitor, a first terminal of the second capacitor being coupled to the first node; the second compensation sub-circuit is coupled to a second control signal terminal, the second node, and the third node; the second compensation sub-circuit is configured to transmit a first voltage from the first voltage terminal and a threshold voltage of the drive sub-circuit to the second node in response to a second control signal received at the second control signal terminal;

the light emitting control sub-circuit is coupled with an enable signal terminal, the third node and the first pole of the light emitting element; the light emission control sub-circuit is configured to output the driving current transmitted to the third node to the light emitting element in response to an enable signal received at the enable signal terminal;

the potential holding sub-circuit is coupled between the first voltage terminal and the first node; the potential holding sub-circuit is configured to hold a potential of the first node; the potential holding sub-circuit includes the first capacitor, and a first terminal of the first capacitor is coupled to the first node.

2. The display substrate according to claim 1, wherein the second conductor layer further comprises an initialization signal line not connected to the third conductor pattern.

3. The display substrate of claim 1, wherein the second terminal of the first capacitor is coupled to the first voltage terminal.

4. The display substrate of claim 1, wherein the second compensation sub-circuit comprises a second transistor; a control electrode of the second transistor is coupled to the second control signal terminal, a first electrode of the second transistor is coupled to the third node, and a second electrode of the second transistor is coupled to the second node.

5. The display substrate of claim 1, wherein the pixel circuit further comprises:

a first initialization sub-circuit coupled to a first reset signal terminal, a first initialization signal terminal, and the first node; the first initialization sub-circuit is configured to transmit a first initialization signal received at the first initialization signal terminal to the first node to initialize a potential of the first node in response to a first reset signal received at the first reset signal terminal.

6. The display substrate of claim 1, wherein the pixel circuit further comprises:

a second initialization sub-circuit coupled to a second reset signal terminal, a second initialization signal terminal, and the second node; the second initialization sub-circuit is configured to transmit a second initialization signal received at the second initialization signal terminal to the second node to initialize a potential of the second node in response to a second reset signal received at the second reset signal terminal.

7. The display substrate of claim 1, wherein the pixel circuit further comprises:

a third initialization sub-circuit coupled to a third reset signal terminal, a third initialization signal terminal, and the first pole of the light emitting element; the third initialization sub-circuit is configured to transmit a third initialization signal received at the third initialization signal terminal to the first pole of the light emitting element in response to a third reset signal received at the third reset signal terminal to initialize the potential of the first pole of the light emitting element.

8. The display substrate according to any one of claims 5 to 7, wherein in the case where the pixel circuit includes a first initialization sub-circuit, a second initialization sub-circuit, and a third initialization sub-circuit,

the first reset signal end, the second reset signal end and the third reset signal end are the same reset signal end, and/or the first initialization signal end, the second initialization signal end and the third initialization signal end are the same initialization signal end.

9. The display substrate according to claim 5, wherein the first initialization sub-circuit comprises a third transistor; a control electrode of the third transistor is coupled to the first reset signal terminal, a first electrode of the third transistor is coupled to the first initialization signal terminal, and a second electrode of the third transistor is coupled to the first node.

10. The display substrate of claim 6, wherein the second initialization sub-circuit comprises a fourth transistor; a control electrode of the fourth transistor is coupled to the second reset signal terminal, a first electrode of the fourth transistor is coupled to the second initialization signal terminal, and a second electrode of the fourth transistor is coupled to the second node.

11. The display substrate of claim 7, wherein the third initialization sub-circuit comprises a fifth transistor; a control electrode of the fifth transistor is coupled to the third reset signal terminal, a first electrode of the fifth transistor is coupled to the third initialization signal terminal, and a second electrode of the fifth transistor is coupled to the first electrode of the light emitting element.

12. The display substrate according to claim 1, wherein the data writing sub-circuit comprises a sixth transistor; a control electrode of the sixth transistor is coupled to the scan signal terminal, a first electrode of the sixth transistor is coupled to the data signal terminal, and a second electrode of the sixth transistor is coupled to the first node.

13. The display substrate of claim 1, wherein a second terminal of the second capacitor is coupled to the second node.

14. The display substrate of claim 1, wherein the driving sub-circuit comprises a driving transistor; the control electrode of the driving transistor is coupled to the second node, the first electrode of the driving transistor is coupled to the first voltage terminal, and the second electrode of the driving transistor is coupled to the third node.

15. The display substrate of claim 1, wherein the emission control subcircuit comprises a seventh transistor; a control electrode of the seventh transistor is coupled to the enable signal terminal, a first electrode of the seventh transistor is coupled to the third node, and a second electrode of the seventh transistor is coupled to the first electrode of the light emitting device.

16. A driving method of a pixel circuit, which is applied to the pixel circuit included in the display substrate according to any one of claims 1 to 15; the driving method includes:

during a compensation phase of an image frame, the second compensation sub-circuit transmits a first voltage from the first voltage terminal and a threshold voltage of the driving sub-circuit to the second node in response to a second control signal received at the second control signal terminal;

in a write phase of the image frame, the data write sub-circuit writes a data signal received at the data signal terminal into the first node in response to a scan signal received at the scan signal terminal; and the number of the first and second groups,

the driving sub-circuit is turned on in response to the voltage of the second node in a light emitting phase of the image frame to generate a driving current; the light emitting control sub-circuit outputs the driving current transmitted to the third node to the light emitting element in response to an enable signal received at the enable signal terminal to drive the light emitting element to emit light.

17. The driving method according to claim 16, wherein the pixel circuit further comprises: at least one of a first initialization sub-circuit, a second initialization sub-circuit, and a third initialization sub-circuit; wherein the first initialization sub-circuit is coupled to a first reset signal terminal, a first initialization signal terminal, and the first node; the second initialization sub-circuit is coupled with a second reset signal terminal, a second initialization signal terminal and the second node; the third initialization sub-circuit is coupled with a third reset signal terminal, a third initialization signal terminal and the first pole of the light-emitting element;

prior to the compensation phase of the image frame, the driving method further comprises at least one of the following steps:

the first initialization sub-circuit transmits a first initialization signal received at the first initialization signal terminal to the first node in response to a first reset signal received at the first reset signal terminal to initialize a potential of the first node in a reset phase of the image frame;

the second initialization sub-circuit transmits a second initialization signal received at the second initialization signal terminal to the second node in response to a second reset signal received at the second reset signal terminal to initialize a potential of the second node in the reset phase of the image frame; and the number of the first and second groups,

in the reset phase of the image frame, the third initialization sub-circuit transmits a third initialization signal received at the third initialization signal terminal to the first pole of the light emitting element in response to a third reset signal received at the third reset signal terminal to initialize the potential of the first pole of the light emitting element.

18. A display device, comprising:

the display substrate of any one of claims 1 to 15; and (c) a second step of,

a driving chip coupled with the display substrate; the driving chip is configured to supply signals required to drive the pixel circuits to the pixel circuits in the display substrate.