CN115825951A - High-speed signal processing device of rockfall monitoring radar - Google Patents
High-speed signal processing device of rockfall monitoring radar Download PDFInfo
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Abstract
The invention discloses a rockfall monitoring radar high-speed signal processing device, which relates to the technical field of geological disaster safety monitoring and early warning, and comprises a power supply system, an SDRAM (synchronous dynamic random access memory) system, an intermediate frequency signal acquisition and storage system, a gigabit Ethernet interface and a control and signal processing unit which is constructed by taking an FPGA (field programmable gate array) as a core processing unit and combining an ARM (advanced RISC machine) core; the control and signal processing unit is used for realizing parameter setting and command downloading, data storage, reading and data processing of the phased array radar; the SDRAM system is used for storing radar data and video data processed in real time; the intermediate frequency signal acquisition and storage system is used for acquiring and storing intermediate frequency phased array radar monitoring echo data; the power supply system is used for providing power for the control and signal processing unit, the SDRAM system, the intermediate frequency signal acquisition and storage system and the gigabit Ethernet interface. According to the invention, the FPGA hardware is used as a core processing unit, and the ARM kernel is combined to realize the high-efficiency operation of the radar data processing algorithm, so that the rockfall early warning response speed is increased.
Description
Technical Field
The invention relates to the technical field of geological disaster safety monitoring and early warning, in particular to a rockfall monitoring radar high-speed signal processing device.
Background
The collapse rockfall disaster has the characteristics of sudden, high-speed movement, high impact energy, multiple occurrence, randomness, difficult predictability, complex movement process and the like, the rockfall movement speed is high (generally 5-200 m/s), and early warning and forecasting are difficult, so a device capable of improving the rockfall early warning response speed is urgently needed.
Disclosure of Invention
The present invention aims to provide a rockfall monitoring radar high-speed signal processing apparatus which can alleviate the above problems.
In order to alleviate the above problems, the technical scheme adopted by the invention is as follows:
the invention provides a high-speed signal processing device of a rockfall monitoring radar, which comprises a power supply system, an SDRAM (synchronous dynamic random access memory) system, an intermediate-frequency signal acquisition and storage system, a gigabit Ethernet interface and a control and signal processing unit, wherein the control and signal processing unit is constructed by taking an FPGA (field programmable gate array) as a core processing unit and combining an ARM (advanced RISC machine) core; the control and signal processing unit is used for realizing parameter setting and command downloading, data storage, reading and data processing of the phased array radar; the SDRAM system is used for storing radar data and video data processed in real time; the intermediate frequency signal acquisition and storage system is used for acquiring and storing intermediate frequency phased array radar monitoring echo data; the gigabit Ethernet interface is used for transmitting the intermediate frequency phased array radar monitoring echo data and the video monitoring data in real time; the power supply system is used for providing power for the control and signal processing unit, the SDRAM system, the intermediate frequency signal acquisition and storage system and the gigabit Ethernet interface.
In a preferred embodiment of the present invention, the power supply system includes a DC-DC chip and an LDO chip; the input power supply voltage of the DC-DC chip is 5V, and the output power supply voltage comprises 1.0V, 1.35V, 1.8V and 3.3V; the input power supply voltage of the LDO chip is 5V, and the output power supply voltage comprises 3.3V.
In a preferred embodiment of the invention, the models of the DC-DC chip and the LDO chip are EA3059 and SPX3819M5-3-3 respectively.
In a preferred embodiment of the invention, the SDRAM system comprises two 4Gbit DDR3 memories, both of which are NT5CB256M16EP-DI.
In a preferred embodiment of the present invention, after receiving the synchronous trigger, the intermediate frequency signal acquisition and storage system acquires intermediate frequency phased array radar monitoring echo data by using the ADC, stores the intermediate frequency phased array radar monitoring echo data in Flash, and reads the intermediate frequency phased array radar monitoring echo data to a computer hard disk through a gigabit ethernet interface, so as to perform post-processing on radar echo signals.
In a preferred embodiment of the present invention, the gigabit ethernet interface is of type YT8521S.
In a preferred embodiment of the present invention, the control unit of the control and signal processing unit uses the FPGA as a hardware platform, and includes an ADC intermediate frequency acquisition memory board and a DAC baseband signal board, and its control software is developed by using phtony software, so as to implement a human-computer interaction interface design and directly communicate with the ADC intermediate frequency acquisition memory board.
In a preferred embodiment of the present invention, the ADC intermediate frequency acquisition and storage board receives a control command from the control and signal processing unit through the network port, implements man-machine interaction of parameter setting and command downloading, and transmits the command parameters to the DAC baseband signal board through the serial port.
In a preferred embodiment of the present invention, the control unit of the control and signal processing unit is configured to send a chirp control command to the system through the network interface, analyze the command parameter to form a system control parameter, send a waveform calculated according to the system control parameter and required by the user to the chirp module, set a control parameter of the transceiver system according to a user instruction, and send alarm information of a system fault to the upper computer through the gigabit ethernet interface.
In a preferred embodiment of the present invention, the control unit of the control and signal processing unit is further configured to operate the intermediate frequency signal acquisition and storage system, erase the original data, store the new sampled data, read the acquired and stored data into a computer hard disk, and read and draw a waveform according to a data format.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides a high-speed signal processing device of a rockfall monitoring radar, aiming at the characteristics of a collapse rockfall disaster and combining the development current situation of a phased array radar technology, wherein the high-speed signal processing device is characterized in that FPGA hardware is used as a core processing unit, and an ARM kernel is combined to realize the efficient operation of a radar data processing algorithm, so that the rockfall early warning response speed is improved, the rockfall distance, speed, movement track and the like can be quickly obtained, the monitoring range is large, all-weather, high-precision and large-range rockfall monitoring and early warning can be realized, and the monitoring result can be uploaded to a cloud end in real time for recording and inquiring.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a block diagram schematically illustrating the construction of a high-speed signal processing board;
FIG. 2 is a block diagram schematically illustrating the construction of a control system;
FIG. 3 is a block diagram schematically illustrating the structure of a power supply system;
FIG. 4 is a block diagram of a schematic structure of an SDRAM system;
FIG. 5 is a block diagram schematically illustrating the structure of an intermediate frequency signal acquisition and storage system;
fig. 6 is a control software interface diagram of the high-speed signal processing device of the rockfall monitoring radar.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention discloses a rockfall monitoring radar high-speed signal processing device which comprises a power supply system, an SDRAM (synchronous dynamic random access memory) system, an intermediate frequency signal acquisition and storage system, a gigabit Ethernet interface, a control and signal processing unit which is constructed by taking an FPGA (field programmable gate array) as a core processing unit and combining an ARM (advanced RISC machine) kernel, and schematic block diagrams of the high-speed signal processing unit and the control unit of the control and signal processing unit in figures 1 and 2 respectively.
Referring to fig. 3, the power needed by the power system includes 1.0V, 1.35V, 1.8V, 3.3V, and VCCIO (3.3V), the DC-DC chip selected in the system is EA3059, which can convert 5V input voltage into 1.0V, 1.35V, 1.8V, and 3.3V, the ldo chip is SPX3819M5-3-3, which can convert 5V voltage into 3.3V, and is specially used for providing power to the BANK34 of the FPGA. Meanwhile, the FPGA has requirements on the power supply sequence, and the generation sequence of all the power supplies conforms to the power-on requirements of the FPGA.
Referring to fig. 4, the sdram system is configured with two 4gbit ddrr 3 memories, the model is: NT5CB256M16EP-DI, total capacity 8G. The memory running speed can reach 533MHz, and simultaneously, because DDR3 is double data sampling, the data sampling rate can reach 1066Mbps. Each DDR3 has a data bit width of 16 bits, two DDR3 constitute a 32-bit-width DDR3 system, the maximum IO clock frequency is 533MHz, the corresponding equivalent data transmission frequency is 1066MHz, and the maximum physical bandwidth which can be provided by two DDR3 is 1066MHz 32bit 0.9=30.7Gbit/s. The storage requirement of real-time processing of radar data and video data is met.
Referring to fig. 5, the intermediate frequency signal acquisition and storage system adopts ADC intermediate frequency sampling and an EMMC Flash storage scheme, and performs data reading by using a network interface and human-computer interface interaction through the network interface. The intermediate frequency signal acquisition and storage system receives synchronous trigger, acquires intermediate frequency signals by using the ADC, stores the intermediate frequency signals in Flash, and can read acquired data into a computer hard disk through a network port so as to perform post-processing on radar echo signals. The ADC collects the storage board card, receives computer control by using the network port, realizes man-machine interaction of parameter setting and command downloading, and transmits command parameters to the baseband system through the serial port, thereby realizing control of the radar host.
The invention is carrying a gigabit Ethernet interface, the type is: YT8521S can realize 1000M Ethernet physical layer function, provides interface support for real-time transmission of radar data and video data.
Referring to fig. 2, the control unit of the control and signal processing unit uses the FPGA as a hardware platform, and includes an ADC intermediate frequency acquisition and storage board and a DAC baseband signal board, so as to implement the functions of parameter setting and command downloading, data storage and reading of the radar host. As shown in fig. 6, the control software is developed by phtony software, so as to realize human-computer interaction interface design, and directly communicate with the ADC acquisition board, and the program control protocol meets the system setting requirements and user requirements. The control unit mainly has two functions, namely, the system sends a linear frequency modulation control command through the network port, and command parameters are analyzed to form system control parameters; and sending the waveform which is calculated according to the control parameters and is required by the user to a linear frequency modulation module; setting control parameters of a transceiving system according to a user instruction, wherein the control parameters comprise a numerical control attenuation control command, an intermediate frequency waveband switch selection command and a phase-locked source control command; and sending alarm information of system faults, such as phase-locked source unlocking information, to the upper computer through the network port so as to facilitate a user to preliminarily judge the system faults. And secondly, operating the intermediate frequency acquisition and storage system, erasing the original data, storing the new sampled data, reading the acquired and stored data into a computer hard disk, reading according to a data format and drawing a waveform.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A high-speed signal processing device of a rockfall monitoring radar is characterized by comprising a power supply system, an SDRAM (synchronous dynamic random access memory) system, an intermediate-frequency signal acquisition and storage system, a gigabit Ethernet interface and a control and signal processing unit which is constructed by taking an FPGA (field programmable gate array) as a core processing unit and combining an ARM (advanced RISC machine) kernel; the control and signal processing unit is used for realizing parameter setting and command downloading, data storage, reading and data processing of the phased array radar; the SDRAM system is used for storing radar data and video data processed in real time; the intermediate frequency signal acquisition and storage system is used for acquiring and storing intermediate frequency phased array radar monitoring echo data; the gigabit Ethernet interface is used for transmitting the intermediate frequency phased array radar monitoring echo data and the video monitoring data in real time; the power supply system is used for providing power for the control and signal processing unit, the SDRAM system, the intermediate frequency signal acquisition and storage system and the gigabit Ethernet interface.
2. The high-speed signal processing apparatus of claim 1, wherein the power supply system comprises a DC-DC chip and an LDO chip; the input power supply voltage of the DC-DC chip is 5V, and the output power supply voltage comprises 1.0V, 1.35V, 1.8V and 3.3V; the input power supply voltage of the LDO chip is 5V, and the output power supply voltage comprises 3.3V.
3. The high-speed signal processing device of claim 2, wherein the models of the DC-DC chip and the LDO chip are EA3059 and SPX3819M5-3-3, respectively.
4. The high-speed signal processing device according to claim 3, wherein the SDRAM system comprises two 4Gbit DDR3 memories, both NT5CB256M16EP-DI.
5. The high-speed signal processing device according to claim 4, wherein the intermediate frequency signal acquisition and storage system acquires intermediate frequency phased array radar monitoring echo data by using the ADC after receiving the synchronous trigger, stores the intermediate frequency phased array radar monitoring echo data in Flash, and reads the intermediate frequency phased array radar monitoring echo data into a computer hard disk through a gigabit Ethernet interface so as to perform post-processing of radar echo signals.
6. The apparatus of claim 5, wherein the gigabit Ethernet interface is of type YT8521S.
7. The high-speed signal processing device according to claim 6, wherein the control unit of the control and signal processing unit uses FPGA as a hardware platform and includes an ADC intermediate frequency acquisition memory board and a DAC baseband signal board, and the control software is developed by using phtony software to realize human-computer interaction interface design and directly communicate with the ADC intermediate frequency acquisition memory board.
8. The high-speed signal processing device according to claim 7, wherein the ADC intermediate frequency acquisition memory board receives control commands from the control and signal processing unit through the network port, realizes man-machine interaction of parameter setting and command downloading, and transmits command parameters to the DAC baseband signal board through the serial port.
9. The apparatus of claim 8, wherein the control unit of the control and signal processing unit is configured to send a chirp control command to the system through the network interface, analyze the command parameters to form system control parameters, send a waveform calculated according to the system control parameters and required by the user to the chirp module, set control parameters of the transceiver system according to a user instruction, and send alarm information of system faults to the host computer through the gigabit ethernet interface.
10. The high-speed signal processing device according to claim 9, wherein the control unit of the control and signal processing unit is further configured to operate the intermediate frequency signal acquisition and storage system, erase original data, store new sampled data, read the acquired and stored data into a computer hard disk, and read and draw a waveform according to a data format.
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