CN110109074A - Radar signal preprocess method based on RFSoC chip - Google Patents
Radar signal preprocess method based on RFSoC chip Download PDFInfo
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- CN110109074A CN110109074A CN201910313025.XA CN201910313025A CN110109074A CN 110109074 A CN110109074 A CN 110109074A CN 201910313025 A CN201910313025 A CN 201910313025A CN 110109074 A CN110109074 A CN 110109074A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/41—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00 using analysis of echo signal for target characterisation; Target signature; Target cross-section
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/41—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00 using analysis of echo signal for target characterisation; Target signature; Target cross-section
- G01S7/418—Theoretical aspects
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- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Radar Systems Or Details Thereof (AREA)
Abstract
The invention discloses a kind of radar signal preprocess method based on RFSoC chip, mainly solve that the existing radar signal pretreatment system development cycle is long, and hardware link design is complicated, the big problem of power consumption.Implementation step is: generating Radar Analog Echo signal with Radar Analog Echo device, and is transmitted to the RF sampled data switch input of RFSoC chip；Relative parameters setting is carried out to RF data converter configuration software in host computer, realizes the RF sampling direct to Radar Analog Echo signal of RF sampled data converter；Down-converted is made to sampled signal, and the data after down coversion are subjected to pulse compression in the FPGA architecture of RFSoC chip, completes the pretreatment of radar signal.This invention simplifies the structures of Radar Signal Processing System, shorten the development cycle, reduce the power consumption of Radar Signal Processing System, can be used for acquisition and the pulse compression to radar return data.
Description
Technical field
The invention belongs to digital signal processing technique field, in particular to a kind of radar signal preprocess method can be used for
Acquisition and pulse compression to radar return data.
Background technique
Radar Signal Processing System includes multiple modules, can control transmitting signal and answers radar return data
Miscellaneous processing, wherein radar pretreatment system includes the output for controlling radiofrequency signal, to the ADC of radar return data acquisition and
The FPGA of pulse compression algorithm is realized.
Traditional radar signal pretreatment system is mostly A/D chip+fpga chip structure, and hardware link design is complicated,
Development cycle is long, and power consumption is larger, and a large amount of discrete converters are established connection and challenged very big I/O is faced, and is not able to satisfy instantly
The low-power consumption of Radar Signal Processing System, short development cycle etc. require.Wherein all used mostly with A/D chip acquisition radar return
The HSSI High-Speed Serial Interface of 12.5Gb/s based on JESD204B agreement, but there are many problems for this scheme.Firstly,
The realization of JESD204B IP kernel needs the time, to use valuable FPGA architecture, and consume a large amount of power consumption.Secondly, serial i/
O power consumption can dramatically increase under more high data rate, and the serial link of foundation also can inevitably be believed under 12.5Gb/s speed
Number distortion.In addition, traditional radar signal pretreatment system mostly all using the simulated scheme of referred to as if sampling, need by
Original signal is down-converted to the sample frequency of ADC support, and down coversion analog circuit needs the design of highly-specialised and complexity
Device selection, comparatively less flexibly.
Summary of the invention
Present invention aims in view of the above shortcomings of the prior art, propose that a kind of radar signal based on RFSoC locates in advance
Reason method, to shorten the development cycle, simplied system structure reduces the power consumption of radar system.
In order to achieve the above objectives, technical scheme is as follows:
A kind of radar signal preprocess method based on RFSoC chip, RFSoC integrated chip RF sampled data turn
Parallel operation, reliable and stable ARM grade processing system and FPGA architecture, the RF sampled data converter subsystem include frequency mixer,
Digital controlled oscillator, extraction/interpolation filter support the complex signal for IQ processing, can be right directly to the RF signal sampling of inflow
Signal after sampling carries out down-converted in the digital domain, which is characterized in that realizes that step includes:
(1) be arranged radar signal carrier frequency, pulse recurrence frequency, modulating bandwidth, target and radar vertical range,
Radar Analog Echo is generated in radar echo simulator, and the pulse compression fit of radar return is generated in software MATLAB
The data of function；
(2) RF signal sampling is directly carried out to Radar Analog Echo using RFSoC chip, generates digit data stream:
(3) data acquired in step (2) are subjected to Orthogonal Decomposition, are divided into I, Q two paths of signals, and respectively in RFSoC core
Do Digital Down Convert processing in RF sampled data converter in piece, then to treated data carry out M times of integer of extraction, with
The sample frequency of signal is reduced, data volume is reduced；
(4) it in the FPGA architecture in RFSoC chip, according to the gate signal of radar return, extracts in data and adopts from M times
Collect the data accordingly counted, and reads I, Q two-way when data are soon filled in FIFO with the data after FIFO caching acquisition
Data, and to the FFT transform that this two paths of data is accordingly counted；
(5) by data and the pulse compression fit function data complex multiplication corresponding in (1) after FFT transform, then by phase
Multiply result and carry out inverse FFT transform, finally the data of I, Q two-way are merged, obtain pulse compression result, are completed to radar return number
According to pretreatment.
Compared with the prior art, the invention has the following advantages:
1. first may be programmed RFSoC chip entirely in the whole world that the present invention uses Xilinx match company, Sentos to release, due to the core
Piece uses RF grades of analogue techniques, is integrated with communication stage RF sampled data converter, ARM grades of processing systems and FPGA architecture, bright
The aobvious structure design for simplifying Radar Signal Processing System.
2. the present invention replaces discrete data converter by integrating direct RF sampling technique, the power consumption of 50-75% is reduced
And package dimension, integrated converter just no longer need to substantially reduce exploitation using JESD204B IP kernel and serial transceiver later
Period.
3. the present invention can sample the radar echo signal of entrance in die terminals " direct ", without using simulator in advance
Part does any Signal Regulation, without carrying out down coversion in advance, and after signal is digitized, utilizes Digital Signal Processing
Down coversion and signal processing are completed in programmable digital domain, are reduced noise, are improved flexibility ratio.
4. since RF sampled data conversion module includes frequency mixer, digital controlled oscillator, extraction/interpolation in RFSoC chip
Filter, thus Digital Down Convert can be realized in RF sampled data converter, filtered data can be directly entered logic frame
Structure reduces the occupancy to FPGA resource, simplifies Radar Signal Processing calculating process.
Detailed description of the invention
Fig. 1 is the structural block diagram of existing RFsOC chip；
Implementation flow chart Fig. 2 of the invention.
Specific embodiment
The present invention will be further described with reference to the accompanying drawing.
Referring to Fig.1, the RFSoC chip that the present invention uses is that global first that Xilinx match company, Sentos releases may be programmed entirely
RFSoC chip, the RFSoC integrated chip RF sampled data converter, reliable and stable ARM grade processing system and FPGA frame
Structure, wherein RF sampled data converter includes ADC module, frequency mixer, digital controlled oscillator, extraction/interpolation filter, supports to be used for
The complex signal of IQ processing, can be directly to the radar echo simulation signal sampling of inflow, to the signal after sampling in RF sampled data
In converter carry out down coversion and filtering extraction processing, later in the FPGA architecture of RFSoC chip to radar return data into
Row process of pulse-compression completes the pretreatment to radar signal.
Referring to Fig. 2, implementation steps of the invention are as follows:
Step 1. generates the arteries and veins of Radar Analog Echo and radar return by radar echo simulator and MATLAB software
Punching press contracting adaptation function data.
The carrier frequency f of (1a) setting radar signalc, modulating bandwidth B, pulse width T, target radial speed v and mesh
The parameters such as the vertical range R of radar are marked, radar emission signal is obtained are as follows:
S (t)=a*exp (j2 π fct)*exp(jπKt2)
Wherein, a is the amplitude of radar emission signal,For the frequency modulation rate of radar emission signal, j indicates imaginary number list
Position；
(1b) obtains thunder according to the lag characteristic of radar emission signal S (t) when pulse Doppler effect and radar return
Up to analog echo signal are as follows:
Sr(t)=a1*exp(j2πfc(t-τ))*exp(jπK(t-τ)2)
Wherein, a1For the amplitude of radar echo signal,For the time delay of radar return, exp () table
Show and takes exponent arithmetic；
(1c) generates radar echo pulse compression fit function S by MATLAB softwarea(t):
Sa(t)=SH(- t)=a*exp (j2 π fct)*exp(-jπKt2),
Wherein, SH(- t) indicates that the conjugation of radar emission signal S (t) is symmetrical.
Step 2. directly carries out RF signal sampling to Radar Analog Echo using RFSoC chip, generates digit data stream.
Radar Analog Echo signal is sent at the radar signal of the chip containing RFSoC by (2a) by SMA RF connection
The SMP interface of plate is managed, and passes through the pin configuration of RFSoC chip, transmits a signal to the input terminal of RF sampled data converter；
(2b) carries out frequency parameter to the ADC module in RFSoC chip using RF sampled data converter configuration software and sets
It sets, to generate the sampling clock of high frequency, realizes and the direct RF of radar echo signal is sampled.
Step 3. does Digital Down Convert and data pick-up in the RF data converter in RFSoC chip.
Gain, phase mismatch parameter, realization pair is arranged by RF sampled data converter configuration software in host computer in (3a)
The amplitude and phase correction of sampled signal；
Frequency parameter is arranged by RF sampled data converter configuration software in host computer in (3b), by RFSoC chip
Digital controlled oscillator generate radar return intermediate frequency local oscillation signal；
Signal after amplitude and phase correction is mixed in the frequency mixer of RFSoC chip by (3c) with the local oscillation signal of intermediate frequency, is generated
I, Q two paths of signals of Orthogonal Decomposition, and this two paths of signals of I, Q is filtered by low-pass filter, filter out high frequency section signal；
(3d) is by the RF sampled data converter configuration software in RFSoC chip to the filtering extraction in RFSoC chip
The extraction yield parameter of device is configured, and is realized that M times to filtered signal is extracted, to reduce the sample frequency of signal, is reduced phase
The data volume answered.
Step 4. acquires data after M times of extraction, and carry out quick Fu to acquisition data according to the gate signal of radar return
In leaf transformation.
The data of (4a) in the FPGA architecture of RFSoC chip, according to the gate signal of radar return, after being extracted to M times
It is acquired:
When gate signal is high, acquire accordingly count M times extract after data, and by acquire M times extract after number
According to caching into FIFO；
When gate signal is low, data are not acquired；
(4b) reads I, Q two paths of data when FIFO is soon filled with, and the FFT core inside FPGA is called, to I, Q of reading
Two paths of data carries out first time Fast Fourier Transform (FFT) respectively.
Step 5. obtains pulse pressure result according to Fast Fourier Transform data and pulse compression fit function data.
(5a) calls the ROM core inside FPGA, imports the pulse compression fit function data generated in MATLAB；
(5b) call FPGA inside complex multiplication IP kernel, by the pulse compression fit function data of importing respectively with (4b)
Middle I, Q two-way first time Fast Fourier Transform (FFT) result complex multiplication；
(5c) by previous step complex multiplication result carry out transposition, call FPGA inside FFT core, to after transposition I,
Q two paths of data carries out second of Fast Fourier Transform (FFT), and second of Fast Fourier Transform (FFT) result of I, Q two-way is merged,
Final pulse compression result is obtained, the pretreatment of radar signal is completed.
Above description is only a specific example of the invention, does not constitute any limitation of the invention, it is clear that for
It, all may be without departing substantially from the principle of the invention, structure after having understood the content of present invention and principle for one of skill in the art
In the case where, carry out various modifications and change in form and details, but these modifications and variations based on inventive concept
Still within the scope of the claims of the present invention.
Claims (3)
1. a kind of radar signal preprocess method based on RFSoC chip, RFSoC integrated chip RF sampled data conversion
Device, reliable and stable ARM grade processing system and FPGA architecture, the RF sampled data converter include frequency mixer, numerical control oscillation
Device, extraction/interpolation are supported to exist to the signal after sampling directly to the RF signal sampling of inflow for the complex signal of IQ processing
Down-converted is carried out in numeric field, which is characterized in that realize that step includes the following:
(1) be arranged radar signal carrier frequency, pulse recurrence frequency, modulating bandwidth, target and radar vertical range, in thunder
Up to generating Radar Analog Echo in echo simulator, and generate in MATLAB software the pulse compression fit function of radar return
Data；
(2) RF signal sampling is directly carried out to Radar Analog Echo using RFSoC chip, generates digit data stream:
(3) data acquired in step (2) are subjected to Orthogonal Decomposition, are divided into I, Q two paths of signals, and respectively in RFSoC chip
RF sampled data converter in do Digital Down Convert processing, then to treated data carry out M times of integer of extraction, with reduction
The sample frequency of signal reduces data volume；
(4) it in the FPGA architecture in RFSoC chip, according to the gate signal of radar return, is extracted from M times and acquires phase in data
The data that should be counted, and I, Q two paths of data are read when data are soon filled in FIFO with the data after FIFO caching acquisition,
And to the FFT transform that this two paths of data is accordingly counted；
(5) it by data and the pulse compression fit function data complex multiplication corresponding in (1) after FFT transform, then ties being multiplied
Fruit carries out inverse FFT transform, obtains pulse compression result, completes the pretreatment to radar return data.
2. according to the method described in claim 1, wherein (3) using RFSoC chip directly carry out RF letter to Radar Analog Echo
Number sampling, realize steps are as follows:
Radar Analog Echo signal is sent to the Radar Signal Processing plate of the chip containing RFSoC by SMA RF connection by (2a)
SMP interface transmit a signal to the input terminal of RF sampled data converter and by the pin configuration of RFSoC chip；
(2b), to the ADC clock module parameter setting in RFSoC chip, is generated high using RF sampled data converter configuration software
The sampling clock of frequency is realized and is sampled to the direct RF of radar echo signal.
3. according to the method described in claim 1, wherein (2) are done in the RF sampled data converter in RFSoC chip respectively
Digital Down Convert processing, then treated data are carried out with M times of integer of extraction, steps are as follows for realization:
Frequency parameter is arranged by RF sampled data converter configuration software in host computer in (3a), passes through the number in RFSoC chip
Control the local oscillation signal that oscillator generates radar return carrier frequency；
The digital sampled signal of (3b) radar return is mixed in the frequency mixer of RFSoC chip with local oscillation signal, the letter after mixing
Number by low-pass filter, high frequency section signal is filtered out；
(3c) is according to extraction yield of the RF sampled data converter configuration software to decimation filter in RFSoC chip in host computer
Parameter setting realizes that M times to filtered signal is extracted.
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Cited By (6)
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| CN111145539A (en) * | 2019-12-12 | 2020-05-12 | 南京理工大学 | Traffic information data acquisition system and method based on ARM processor |
| CN111896919A (en) * | 2020-06-15 | 2020-11-06 | 安徽金帅洗衣机有限公司 | Echo signal acquisition device |
| CN113030873A (en) * | 2021-03-31 | 2021-06-25 | 成都汇蓉国科微系统技术有限公司 | PD radar pulse pressure matching coefficient self-adaptation device based on FPGA |
| CN113740706A (en) * | 2021-08-18 | 2021-12-03 | 中国科学院新疆天文台 | RFSoC signal capturing and spectrum analyzing device and method |
| CN114860647A (en) * | 2022-03-18 | 2022-08-05 | 北京遥感设备研究所 | SoC chip applied to radar |
| CN115825951A (en) * | 2022-11-14 | 2023-03-21 | 华能澜沧江水电股份有限公司 | High-speed signal processing device of rockfall monitoring radar |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111145539A (en) * | 2019-12-12 | 2020-05-12 | 南京理工大学 | Traffic information data acquisition system and method based on ARM processor |
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| CN115825951A (en) * | 2022-11-14 | 2023-03-21 | 华能澜沧江水电股份有限公司 | High-speed signal processing device of rockfall monitoring radar |
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