CN204145474U - A kind of Digital Intermediate Frequency Receiving System - Google Patents
A kind of Digital Intermediate Frequency Receiving System Download PDFInfo
- Publication number
- CN204145474U CN204145474U CN201420526361.5U CN201420526361U CN204145474U CN 204145474 U CN204145474 U CN 204145474U CN 201420526361 U CN201420526361 U CN 201420526361U CN 204145474 U CN204145474 U CN 204145474U
- Authority
- CN
- China
- Prior art keywords
- digital
- signal
- fpga
- matching circuit
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
The utility model discloses a kind of Digital Intermediate Frequency Receiving System, comprise the receiver module, the first radio frequency matching circuit, analog to digital converter, FPGA, digital to analog converter, the second radio frequency matching circuit and the power amplifier module that connect successively; Described FPGA domination number weighted-voltage D/A converter produces intermediate-freuqncy signal, this signal is sent into power amplifier module through the second radio frequency matching circuit and is carried out up-conversion to tranmitting frequency, and launch after this signal power is pushed into transmitting power, receiver module receives its echo-signal and becomes intermediate-freuqncy signal through frequency down-converts, intermediate-freuqncy signal is sent into analog to digital converter through the first radio frequency matching circuit and is carried out digital quantization, then the digital signal feeding FPGA after digital quantization is carried out signal transacting.The utility model can complete the data acquisition of intermediate-frequency receiver, signal transacting, transfer of data and waveform generation high-speed and high-efficiency, improves the overall performance of radar system.
Description
Technical field
The utility model belongs to Radar Technology field, particularly a kind of Digital Intermediate Frequency Receiving System.
Background technology
Along with the application scenario of modern radar increases, Radar Technology is also developing thereupon.Multi-functional, small size, high performance radar become the trend of development.Adopt all solid state physique radar transmit-receive parts very ripe, radar based on solid state transmitter physique be meet high resolution, multipulse signal waveform that the Effect on Detecting of little blind area needs frequency of utilization diversity, time diversity, and in receiver signal process, use complicated matched filter to realize pulse compression.The module performances such as this data acquisition to digital if receiver, signal transacting, transfer of data and waveform generation propose high requirement.
Utility model content
In order to solve the technical problem that background technology exists, the utility model aims to provide a kind of Digital Intermediate Frequency Receiving System, the data acquisition of intermediate-frequency receiver, signal transacting, transfer of data and waveform generation can be completed high-speed and high-efficiency, improve the overall performance of radar system.
A kind of Digital Intermediate Frequency Receiving System, comprises the receiver module, the first radio frequency matching circuit, analog to digital converter, FPGA, digital to analog converter, the second radio frequency matching circuit and the power amplifier module that connect successively; Described FPGA domination number weighted-voltage D/A converter produces intermediate-freuqncy signal, this signal is sent into after power amplifier module carries out up-conversion to tranmitting frequency through the second radio frequency matching circuit and is transmitted, receiver module receives its echo-signal and becomes intermediate-freuqncy signal through frequency down-converts, intermediate-freuqncy signal is sent into analog to digital converter through the first radio frequency matching circuit and is carried out digital quantization, then the digital signal feeding FPGA after digital quantization is carried out signal transacting.
Wherein, the model of above-mentioned FPGA is XC6VSX475T.
Wherein, above-mentioned analog to digital converter adopts AD9467.
Wherein, above-mentioned digital to analog converter adopts AD9783.
Wherein, also comprise the netting twine communication interface and fiber optic data communication interface that are connected with FPGA respectively, realize the data interaction of FPGA and host computer.
Adopt the beneficial effect that technique scheme is brought:
(1) the utility model is using FPGA as main control chip, coordinates digital to analog converter to produce complicated wave form, meets the necessary waveform requirements of advanced capabilities radar; Coordinate high performance analog to digital converter simultaneously, the harmless collection of complicated wave form signal and sophisticated signal work for the treatment of can be completed, the signal transacting work of completely compatible as linear in pulse and the waveform such as nonlinear frequency modulation continuous wave, the pulse of simple fixed frequency;
(2) receiver adopts the Double Data transmission of optical fiber communication and network service, transmitted by two interfaces after radar initial data being decomposed in chip based on high-performance FPGA simultaneously, to solve the mass data transmission problem that complicated wave form signal processing results brings, substantially increase the integrity degree that terminal obtains data, can according to circumstances select any interface in the occasion that data transportation requirements is lower simultaneously, improve applicability.
Accompanying drawing explanation
Fig. 1 is system architecture diagram of the present utility model.
Fig. 2 is the utility model flow chart of data processing figure.
Embodiment
Below with reference to accompanying drawing, the technical solution of the utility model is described in detail.
System architecture diagram of the present utility model as shown in Figure 1, a kind of Digital Intermediate Frequency Receiving System, comprises the receiver module, the first radio frequency matching circuit, analog to digital converter, FPGA, digital to analog converter, the second radio frequency matching circuit and the power amplifier module that connect successively; Described FPGA domination number weighted-voltage D/A converter produces intermediate-freuqncy signal, this signal is sent into after power amplifier module carries out up-conversion to tranmitting frequency through the second radio frequency matching circuit and is transmitted, receiver module receives its echo-signal and becomes intermediate-freuqncy signal through frequency down-converts, intermediate-freuqncy signal is sent into analog to digital converter through the first radio frequency matching circuit and is carried out digital quantization, then the digital signal feeding FPGA after digital quantization is carried out signal transacting.
In the present embodiment, the model of FPGA is XC6VSX475T.Analog to digital converter adopts AD9467.Digital to analog converter adopts AD9783.Native system also comprises the netting twine communication interface and fiber optic data communication interface that are connected with FPGA respectively, realizes the data interaction of FPGA and host computer.The switch of receiver module and power amplifier module controls by FPGA.The clock of AD9467, AD9783 is all benchmark with Timing Signal, and Timing Signal is produced by inner or outside, thus realizes full coherent system.
Operation principle of the present utility model: FPGA domination number weighted-voltage D/A converter produces an intermediate-freuqncy signal, its frequency is pushed to tranmitting frequency by up-conversion by power amplifier module, launch this radar signal, the echo-signal of this radar signal is received module reception and is intermediate-freuqncy signal through frequency down-converts, this intermediate-freuqncy signal is converted to digital signal through analog to digital converter and sends FPGA to carries out Digital Signal Processing, baseband signal is extracted from this digital signal, and this baseband signal feeding matched filter is carried out process of pulse-compression, obtain the signal of high s/n ratio Sidelobe.Wherein, the method extracting baseband signal from digital signal is: echo-signal may comprise the signal of multiple frequency band, and this sentences signal (first paragraph frequency signal and the second segment frequency signal) explanation that echo-signal comprises 2 frequency bands.F1 is the local oscillation signal of first paragraph frequency signal corresponding frequencies section, f2 is the local oscillation signal of second segment frequency signal corresponding frequencies section, first paragraph frequency signal and local oscillation signal f1 are carried out mixed quadrature and IQ decomposes, obtain the baseband signal of first paragraph frequency, also other frequency contents are created after second segment frequency signal and local oscillation signal f1 mixed quadrature and IQ decompose, but these frequency contents are all outside the modulating bandwidth of local oscillation signal f1, the low pass filter of modulating bandwidth is less than by cut-off frequency, can by these frequency content filterings, namely the baseband signal of first paragraph frequency is extracted.Same method extracts the baseband signal of second segment frequency.The digital signal processing of FPGA as shown in Figure 2.
Above embodiment is only and technological thought of the present utility model is described; protection range of the present utility model can not be limited with this; every technological thought according to the utility model proposes, any change that technical scheme basis is done, all falls within the utility model protection range.
Claims (5)
1. a Digital Intermediate Frequency Receiving System, is characterized in that: comprise the receiver module, the first radio frequency matching circuit, analog to digital converter, FPGA, digital to analog converter, the second radio frequency matching circuit and the power amplifier module that connect successively; Described FPGA domination number weighted-voltage D/A converter produces intermediate-freuqncy signal, this signal is sent into after power amplifier module carries out up-conversion to tranmitting frequency through the second radio frequency matching circuit and is transmitted, receiver module receives its echo-signal and becomes intermediate-freuqncy signal through frequency down-converts, intermediate-freuqncy signal is sent into analog to digital converter through the first radio frequency matching circuit and is carried out digital quantization, then the digital signal feeding FPGA after digital quantization is carried out signal transacting.
2. a kind of Digital Intermediate Frequency Receiving System according to claim 1, is characterized in that: the model of described FPGA is XC6VSX475T.
3. a kind of Digital Intermediate Frequency Receiving System according to claim 1, is characterized in that: described analog to digital converter adopts AD9467.
4. a kind of Digital Intermediate Frequency Receiving System according to claim 1, is characterized in that: described digital to analog converter adopts AD9783.
5. a kind of Digital Intermediate Frequency Receiving System according to claim 1, is characterized in that: also comprise the netting twine communication interface and fiber optic data communication interface that are connected with FPGA respectively, realize the data interaction of FPGA and host computer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420526361.5U CN204145474U (en) | 2014-09-15 | 2014-09-15 | A kind of Digital Intermediate Frequency Receiving System |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420526361.5U CN204145474U (en) | 2014-09-15 | 2014-09-15 | A kind of Digital Intermediate Frequency Receiving System |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204145474U true CN204145474U (en) | 2015-02-04 |
Family
ID=52422135
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420526361.5U Expired - Fee Related CN204145474U (en) | 2014-09-15 | 2014-09-15 | A kind of Digital Intermediate Frequency Receiving System |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204145474U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105353363A (en) * | 2015-11-25 | 2016-02-24 | 四川九洲空管科技有限责任公司 | Method for improving the target resolution by means of time diversity and frequency diversity |
| CN115951105A (en) * | 2023-03-09 | 2023-04-11 | 苏州联讯仪器股份有限公司 | Electric signal sampling channel device and sampling oscilloscope |
-
2014
- 2014-09-15 CN CN201420526361.5U patent/CN204145474U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105353363A (en) * | 2015-11-25 | 2016-02-24 | 四川九洲空管科技有限责任公司 | Method for improving the target resolution by means of time diversity and frequency diversity |
| CN105353363B (en) * | 2015-11-25 | 2017-06-09 | 四川九洲空管科技有限责任公司 | A kind of method that utilization time diversity and frequency diversity improve target discrimination |
| CN115951105A (en) * | 2023-03-09 | 2023-04-11 | 苏州联讯仪器股份有限公司 | Electric signal sampling channel device and sampling oscilloscope |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110824507B (en) | Simulator of upper note receiving processor of navigation satellite | |
| EP3618305A3 (en) | Dual-mode low-power wide-area network chip, method for data transmission, and terminal | |
| US10560132B2 (en) | Reconfigurable transmitter and receiver, and methods for reconfiguring | |
| CN104079310A (en) | Ultrashort wave data transmission receiving system based on software radio architecture and receiving method thereof | |
| CN105338666B (en) | Portable multiband base station equipment | |
| CN107819490A (en) | A kind of pulse ultra-broad band Terahertz receives and dispatches framework | |
| CN108649967A (en) | A kind of more servicing transceiver systems in broadband based on zero intermediate frequency chip | |
| CN204145474U (en) | A kind of Digital Intermediate Frequency Receiving System | |
| CN104158561B (en) | A kind of HF frequency hopping processing method | |
| CN106130594A (en) | Co-channel full duplex communication means and device while suppressing based on frequency domain self-interference | |
| CN108964741B (en) | Satellite-borne X-frequency-band high-speed data transmission system | |
| CN110824437A (en) | High-frequency ground wave radar simultaneous multi-frequency networking MIMO all-digital receiver | |
| CN206023750U (en) | A kind of antenna assembly of integrated RF front-end circuit | |
| CN205039805U (en) | End device before shortwave is received | |
| CN203643599U (en) | Secondary radar high- and intermediate-frequency digital receiver | |
| CN204177972U (en) | Beidou satellite navigation single/double mode hand-hold radio frequency component | |
| CN202094887U (en) | Aeronautical telemetering system based on receiving machine array | |
| RU2394372C1 (en) | Method of transmission and receiving of digital information in tropospheric communication lines | |
| CN103136147A (en) | Signal collection system and method | |
| CN210123969U (en) | Super large developments up-converter | |
| CN104426557A (en) | High-speed frequency hopping transmitter | |
| CN103138776A (en) | Multiple output Zigbee launcher | |
| CN207427153U (en) | A kind of same frequency while Full-duplex wireless communications device | |
| CN202940804U (en) | Missile-borne coherent multi-station triggering working pulse transponder | |
| CN206498403U (en) | A kind of satellite communication apparatus of achievable various mode transmission |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20160926 Address after: Jiangning Development Zone in Nanjing City, Jiangsu province 211153 Evergreen Street No. 32 Patentee after: CSIC PRIDE (NANJING) ATMOSPHERE MARINE INFORMATION SYSTEM Co.,Ltd. Patentee after: NANJING PRIDE SYSTEMS ENGINEERING INSTITUTE Patentee after: CSIC PRIDE(Nanjing)Intelligent Equipment System Co.,Ltd Patentee after: 724TH RESEARCH INSTITUTE OF CHINA SHIPBUILDING INDUSTRY Corp. Address before: Jiangning Development Zone in Nanjing City, Jiangsu province 211153 Evergreen Street No. 32 Patentee before: CSIC PRIDE (NANJING) ATMOSPHERE MARINE INFORMATION SYSTEM Co.,Ltd. Patentee before: NANJING PRIDE SYSTEMS ENGINEERING INSTITUTE Patentee before: NANJING PRIDE TECHNOLOGY Co.,Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150204 Termination date: 20210915 |