CN115810656B - Silicon carbide MOSFET device, preparation method thereof and chip - Google Patents

Abstract

The invention relates to the technical field of semiconductors, in particular to a silicon carbide MOSFET device, a preparation method thereof and a chip. The invention provides a silicon carbide MOSFET device, comprising: the semiconductor device comprises a drift region of silicon carbide doped with a first conductive type semiconductor material, a Schottky contact metal buried layer, a body region of silicon carbide doped with a second conductive type semiconductor material, an electrode connecting metal, a source region of silicon carbide doped with the first conductive type semiconductor material, a gate oxide layer and a gate electrode. The Schottky buried metal layer is led in at the bottom of the body region, and electrode connection metal is arranged to lead out the Schottky buried metal layer and connect the Schottky buried metal layer to an external electrode, the buried metal layer forms Schottky contact with the drift region and forms ohmic contact with the body region, so that the conduction of a parasitic transistor can be effectively inhibited, and the dv/dt capacity and avalanche energy of the device are improved.

Description

Silicon carbide MOSFET device, preparation method thereof and chip

Technical Field

The invention relates to the technical field of semiconductors, in particular to a silicon carbide MOSFET device, a preparation method thereof and a chip.

Background

Silicon Carbide (SiC) is one of the third generation semiconductor materials, and has a larger forbidden bandwidth, so that the Silicon Carbide device can bear higher working temperature, has lower leakage current, stronger irradiation resistance and lower on-resistance, and has a wide application prospect in the field of power semiconductors. MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor) are field effect transistors widely used in analog circuits and digital circuits, and have the advantages of high input impedance, low noise, good thermal stability, simple manufacturing process, strong radiation, and the like, so they are generally used in amplifying circuits or switching circuits.

In a conventional silicon carbide MOSFET device, due to its structure, there is a parasitic PN junction body diode in the reverse direction through which current will flow when there is a reverse current in the circuit. However, the diode has higher conduction voltage drop and reverse recovery, so that the device has the situation that the body diode freewheels in practical application, which causes larger loss and reduces the system efficiency. In order to solve the problem of parasitic diode, the research and development personnel consider a method of adopting a packaged integrated external anti-parallel schottky diode (SBD) as a free-wheeling diode of a MOSFET, but the method is not ideal in cost, performance and area.

Disclosure of Invention

Based on the above, it is necessary to provide a silicon carbide MOSFET device, a preparation method thereof and a chip thereof, so as to solve the problems of large device area, poor performance and high cost in the conventional technology.

In a first aspect of the present invention, there is provided a silicon carbide MOSFET device comprising: the semiconductor device comprises a drift region of a silicon carbide doped first conductivity type semiconductor material, a Schottky contact metal buried layer, a body region of a silicon carbide doped second conductivity type semiconductor material, an electrode connecting metal, a source region of the silicon carbide doped first conductivity type semiconductor material, a gate oxide layer and a gate electrode;

in each cell:

the drift region comprises at least two first groove structures, and the Schottky contact metal buried layer is arranged on the inner bottom surface of the first groove structures;

the body region is arranged on one side surface of the Schottky contact metal buried layer, which is far away from the drift region;

the body region comprises at least two second groove structures and at least one through hole, the second groove structures are not connected with the Schottky contact metal buried layer, one side of the through hole is connected with the Schottky contact metal buried layer, the source region is filled in the second groove structures, and the electrode connecting metal is filled in the through hole;

the surface of the interval region of two adjacent first groove structures in the drift region is sequentially provided with the gate oxide layer and the grid electrode, and the gate oxide layer partially covers the body region and the source region;

wherein the first conductive type semiconductor is a P-type semiconductor and the second conductive type semiconductor is an N-type semiconductor, or the first conductive type semiconductor is an N-type semiconductor and the second conductive type semiconductor is a P-type semiconductor.

In some embodiments, the buried schottky metal layer is made of one or more of Ti, mo, ni, au and Pt.

In some embodiments, the thickness of the schottky metal buried layer is 50 nm-5000 nm.

In some embodiments, the electrode connection metal material includes one or more of Ti, mo, ni, W, cu and Al.

In some embodiments, the through holes have a length of 0.2 μm to 10 μm and a diameter of 0.05 μm to 5 μm.

In some embodiments, the drift region further includes one or more sub-doped regions, and the material of the sub-doped regions is silicon carbide doped with a semiconductor of the second conductivity type.

In some embodiments, the gate oxide layer comprises one or more of silicon dioxide, hafnium oxide, titanium oxide, aluminum oxide, and tantalum oxide.

In some embodiments, the gate electrode material includes one or more of polysilicon, tungsten silicide, titanium silicide, and nickel silicide.

In a second aspect of the present invention, there is provided a method of forming a silicon carbide MOSFET device according to one or more of the embodiments described above, comprising the steps of:

a. providing a silicon carbide epitaxial wafer doped with a first conductive type semiconductor, and etching the silicon carbide epitaxial wafer doped with the first conductive type semiconductor to form a first groove structure to obtain a drift region;

b. depositing schottky metal on the inner bottom surface of the first groove structure to form a schottky metal buried layer;

c. preparing a body region in the first groove structure formed with the schottky metal buried layer;

d. photoetching and ion implantation are carried out on the body region to form a source region; preparing a gate oxide layer on a plane formed by the drift region, the body region and the source region, and enabling the gate oxide layer to partially cover the drift region, the body region and the source region; preparing a grid electrode on the surface of one side of the grid oxide layer far away from the drift region;

e. etching the body region to form a through hole connected with the Schottky metal buried layer, and depositing metal in the through hole to form electrode connection metal;

wherein, step d and step e are separated in no sequence.

In a third aspect of the present invention, a chip is provided that includes a silicon carbide MOSFET device according to one or more of the embodiments described above.

According to the invention, the Schottky metal buried layer is led in at the bottom of the body region, and is led out and connected to an external electrode by arranging the electrode connection metal, the Schottky metal buried layer forms Schottky contact with the drift region and forms ohmic contact with the body region, so that the conduction of a parasitic transistor can be effectively inhibited, and the dv/dt capacity and avalanche energy of a device are greatly improved; and avoid the traditional technology to need to encapsulate the mode of the external anti-parallel schottky diode of integration, but introduce the schottky contact surface into the device inside, can effectively reduce the chip area, reduce the chip cost.

Drawings

Fig. 1 is a schematic structural diagram of a silicon carbide MOSFET device according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a silicon carbide MOSFET device of a comparative embodiment;

FIG. 3 is a schematic view of a silicon carbide MOSFET device according to another embodiment of the present invention;

fig. 4 to 8 are schematic structural diagrams corresponding to devices obtained by different steps in the preparation process of the silicon carbide MOSFET device of the present invention;

fig. 9 is a schematic structural diagram of a silicon carbide MOSFET device prepared in comparative example 1.

Detailed Description

In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. The drawings show a preferred experimental example of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these experimental examples are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular experimental examples only and is not intended to be limiting of the invention.

In the invention, the technical characteristics described in an open mode comprise a closed technical scheme composed of the listed characteristics and also comprise an open technical scheme comprising the listed characteristics.

In the present invention, the numerical ranges are referred to as continuous, and include the minimum and maximum values of the ranges, and each value between the minimum and maximum values, unless otherwise specified. Further, when a range refers to an integer, each integer between the minimum and maximum values of the range is included. Further, when multiple range description features or characteristics are provided, the ranges may be combined. In other words, unless otherwise indicated, all ranges disclosed herein are to be understood to include any and all subranges subsumed therein.

In the present invention, "at least one" may represent one, two, three, four … … "at least two" may represent two, three, four, five … … "a plurality" may represent two, three, four, five … …

In a first aspect of the present invention, a silicon carbide MOSFET device is provided.

In one embodiment, a schematic structure of a silicon carbide MOSFET device can be referred to in fig. 1, comprising: a drift region 1 of the silicon carbide doped semiconductor material of the first conductivity type, a Schottky contact metal buried layer 6, a body region 2 of the silicon carbide doped semiconductor material of the second conductivity type, an electrode connecting metal 7, a source region 3 of the silicon carbide doped semiconductor material of the first conductivity type, a gate oxide layer 5 and a gate electrode 4;

a cell refers to a MOSFET cell, and in one embodiment, a schematic view of the MOSFET cell can be seen in the dashed box of fig. 1. The MOSFET device may be formed by an array of one or more cells, two of which are shown in fig. 1.

In each cell:

the drift region 1 comprises at least two first groove structures, and the Schottky contact metal buried layer 6 is arranged on the inner bottom surface of each first groove structure;

the body region 2 is arranged on one side surface of the Schottky contact metal buried layer 6, which is far away from the drift region 1;

the body region 2 comprises at least two second groove structures and at least one through hole, the second groove structures are not connected with the Schottky contact metal buried layer 6, one side of the through hole is connected with the Schottky contact metal buried layer 6, the source region 3 is filled in the second groove structures, and the electrode connecting metal 7 is filled in the through hole; optionally, the source region 3 is connected or disconnected with the electrode connection metal 7;

a gate oxide layer 5 and a gate electrode 4 are sequentially arranged on the surfaces of the interval areas of two adjacent first groove structures in the drift region 1, and the gate oxide layer 5 partially covers the body region 2 and the source region 3;

wherein the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor, or the first conductivity type semiconductor is an N-type semiconductor and the second conductivity type semiconductor is a P-type semiconductor.

It will be appreciated that in the present invention, when dividing each cell, the via hole of the filler electrode connecting metal 7 at the boundary of the cell is divided into two parts, which are respectively arranged on both sides of each cell in the form of half via holes, and thus, it should be considered that each cell has at least one via hole therein.

The Schottky metal buried layer is led in at the bottom of the body region, and is led out and connected to an external electrode by arranging electrode connection metal, the metal buried layer forms Schottky contact with the drift region and forms ohmic contact with the body region, so that the conduction of a parasitic transistor can be effectively inhibited, and the dv/dt capacity and avalanche energy of the device are greatly improved; and avoid the traditional technology to need to encapsulate the mode of the external anti-parallel schottky diode of integration, but introduce the schottky contact surface into the device inside, can effectively reduce the chip area, reduce the chip cost.

In some embodiments, the material of the schottky metal buried layer includes one or more of Ti, mo, ni, au and Pt. Preferably, the material of the schottky metal buried layer is one or two of Ti and Mo. The proper material can enable the Schottky buried layer and the drift region to form Schottky contact better, so that the device performance is further improved.

In some embodiments, the schottky metal buried layer has a thickness of 50 a nm a to 5000 a nm a. Alternatively, the process may be carried out in a single-stage, the thickness of the buried schottky metal layer may be, for example, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1000 nm, 1100 nm, 1150 nm, 1200 nm, 1250 nm, 1300 nm, 1350 nm, 1400 nm, 1450 nm, 1500 nm, 1550 nm, 1600 nm, 1650 nm, 1700 nm, 1750 nm, 1800 nm, 1850 nm, 521900 nm, 1950 nm, 2000 nm, 2100 nm, 2150 nm, 2200 nm, 2250 nm, 2300 nm, 2350 nm, 2400 37, 2450 nm 2500 nm, 2550 nm, 2600 nm, 2650 nm, 2700 nm, 2750 nm, 2800 nm, 2850 nm, 2900 nm, 2950 nm, 3000 nm, 3100 nm, 3150 nm, 3200 nm, 3250 nm, 3300 nm, 3350 nm, 3400 nm, 3450 nm, 3500 nm, 3550 nm, 3600 nm, 3650 nm, 3700 nm, 3750 nm, 380 nm, 3850 nm, 3900 nm, 3950 nm, 4000 nm, 4100 nm, 4150 nm, 4200 nm, 4250 nm, 4300 nm, 4350 nm, 4400 nm, 4450 nm, 4500 nm, 4550 nm, 4600 nm, 4700 nm, 4750 nm, 4800 nm, 4850 nm, 4900 nm or 4950). The proper thickness of the Schottky metal buried layer can effectively avoid the improvement of phase leakage or the reduction of drain-source Breakdown Voltage (BV), and further improve the performance of the device.

In some embodiments, the electrode connection metal material includes one or more of Ti, mo, ni, W, cu and Al. Preferably, the electrode connection metal is one or two of Ti and W. Suitable electrode connection metal materials enable the buried metal layer to form a better connection with the outer electrode.

In some embodiments, the through holes have a length of 0.2 μm to 10 μm and a diameter of 0.05 μm to 5 μm. Alternatively, the length of the through hole may be, for example, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, 7.5 μm, 8 μm, 8.5 μm, 9 μm or 9.5 μm; alternatively, the diameter of the through hole may be, for example, 0.1 μm, 0.25 μm, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm or 4.5 μm. The proper diameter and length of the through hole can effectively avoid the promotion of phase leakage or the decrease of BV, and further promote the performance of the device.

The inventor of the present invention found in the course of research that if part of the gate electrode (including the oxide layer under the gate electrode) is replaced with a schottky contact on the basis of the pure MOSFET structure, the integration of the schottky diode can be achieved, so as to solve the problem of the parasitic diode in the MOSFET device, and this scheme can refer to fig. 2, and the rest of the construction is similar to that provided in fig. 1 except that the schottky contact metal region 6' is disposed on the surface of the device. However, in the solution presented in fig. 2, the schottky contact metal region 6' occupies a lot of chip area, and the reduction of the chip area cannot be effectively achieved. The inventors have found that if the schottky contact metal region 6' in fig. 2 is simply transferred to the inside of the device and is disposed at the bottom of the body region, without special design, the body region cannot reduce the longitudinal electric field by depletion with the JEFT region under high voltage, so as to realize the protection of the schottky contact, which may result in significant improvement of phase leakage or decrease of BV. Therefore, the thickness of the schottky metal buried layer, the length and the diameter of the through hole need to be controlled in particular, so that the basic performance of the device is maintained or even improved on the premise that the schottky contact metal region is integrated into the device and the area of the chip can be reduced effectively.

In some embodiments, the schottky metal buried layer has a thickness of 50 a nm a to 99 a nm a. The buried schottky metal layer may also have a thickness of, for example, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, or 95 nm. According to the scheme of fig. 2, when the schottky metal layer is disposed on the surface of the device, a part of schottky metal may react with the metal of the electrode layer due to the large-area contact between the upper surface of the schottky metal layer and the electrode layer (not shown in the figure), so that the schottky metal layer is often required to have a thickness of hundreds of nanometers, and the schottky metal layer with a certain thickness for reaction is reserved, so that the device performance is prevented from being reduced after the schottky metal layer reacts with the electrode metal layer. The schottky metal layer is arranged in the device, so that large-area contact with metal of the surface electrode layer is avoided, and the thickness which possibly reacts is not required to be reserved, so that the thickness of the schottky metal layer can be reduced under the condition that the performance of the device is not greatly and negatively influenced, the size of the device is further saved, and the production cost is reduced.

In an embodiment, referring to fig. 3, the drift region 1 may further include one or more sub-doped regions 8, where the material of the sub-doped regions 8 is silicon carbide doped with a semiconductor of the second conductivity type. By arranging the sub-doped regions 8 with opposite doping types in the drift region 1, the device performance can be further improved, and the improvement of phase leakage and the reduction of BV can be avoided.

In some embodiments, the gate oxide layer comprises one or more of silicon dioxide, hafnium oxide, titanium oxide, aluminum oxide, and tantalum oxide.

In some embodiments, the gate material includes one or more of polysilicon, tungsten silicide, titanium silicide, and nickel silicide.

In a second aspect of the present invention, there is provided a method of one or more of the foregoing embodiments of a silicon carbide MOSFET device, comprising the steps of:

a. providing a silicon carbide epitaxial wafer doped with a first conductive type semiconductor, and etching the silicon carbide epitaxial wafer doped with the first conductive type semiconductor to form a first groove structure to obtain a drift region 1;

b. depositing schottky metal on the inner bottom surface of the first groove structure to form a schottky metal buried layer 6;

c. preparing a body region 2 in a first groove structure formed with a schottky metal buried layer 6;

d. photoetching and ion implantation are carried out on the body region 2 to form a source region 3; preparing a gate oxide layer 5 on a plane formed by the drift region 1, the body region 2 and the source region 3, and enabling the gate oxide layer 5 to partially cover the drift region 1, the body region 2 and the source region 3; preparing a grid electrode 4 on the surface of one side of the grid oxide layer 5 away from the drift region 1;

e. etching the body region 2 to form a through hole connected with the Schottky metal buried layer 6, and depositing metal in the through hole to form electrode connection metal 7;

wherein, step d and step e are separated in no sequence.

In one embodiment, a method of a silicon carbide MOSFET device includes the steps of:

(1) Providing a silicon carbide epitaxial wafer doped with a first conductive type semiconductor, masking, gluing, exposing, developing and etching the silicon carbide epitaxial wafer doped with the first conductive type semiconductor to form a first groove structure, and enabling the groove angle to be arc-shaped through optimizing process parameters to obtain a drift region 1;

(2) Depositing schottky metal on the inner bottom surface of the first groove structure to form a schottky metal buried layer 6;

(3) Forming a body region 2 by epitaxy in a first groove structure formed with a Schottky metal buried layer 6, and flattening the surface by chemical mechanical polishing CMP;

(4) Masking, photoetching and ion implantation are carried out on the body region 2 to form a source region 3;

(5) Preparing a gate oxide layer 5 on a plane formed by the drift region 1, the body region 2 and the source region 3 through a dry oxygen oxidation and nitridation process, and enabling the gate oxide layer 5 to partially cover the drift region 1, the body region 2 and the source region 3;

(6) Depositing a gate electrode 4 on the surface of one side of the gate oxide layer 5 away from the drift region 1;

(7) Etching the body region 2 to form a through hole connected with the Schottky metal buried layer 6;

(8) Depositing metal in the through hole to form electrode connecting metal 7, and removing redundant metal by etching;

(9) Depositing an isolation dielectric layer on the surface, and forming a grid electrode and a source electrode metal electrode through photoetching, etching and deposition processes; and forming a drain electrode on the back surface through thinning and metallization.

Wherein, the schematic structural diagram of the device obtained in the step (1) can refer to fig. 4; the schematic structural diagram of the device obtained in the step (2) can be referred to fig. 5; the schematic structural diagram of the device obtained in the step (4) can be referred to fig. 6; the schematic structural diagram of the device obtained in step (6) can be referred to fig. 7; the schematic structure of the device obtained in step (8) can be referred to fig. 8.

In a third aspect of the present invention, a chip is provided comprising the silicon carbide MOSFET device of one or more of the embodiments described above.

Experimental example 1

(1) Providing a silicon carbide epitaxial wafer doped with an N-type semiconductor, masking, gluing, exposing, developing and etching the silicon carbide epitaxial wafer to form a first groove structure, and optimizing process parameters to enable the groove angle to be arc-shaped to obtain a drift region 1;

(2) Depositing schottky metal Ti on the inner bottom surface of the first groove structure to form a schottky metal buried layer 6 with the thickness of 500 nm;

(3) Forming a body region 2 of a doped P-type semiconductor by epitaxial formation in a first groove structure formed with a Schottky metal buried layer 6, and flattening the surface by Chemical Mechanical Polishing (CMP);

(4) Masking, photoetching and ion implantation are carried out on the body region 2 to form a source region 3 of the doped N-type semiconductor;

(5) Preparing a silicon dioxide gate oxide layer 5 on a plane formed by the drift region 1, the body region 2 and the source region 3 through dry oxygen oxidation and nitridation processes, and enabling the gate oxide layer 5 to partially cover the drift region 1, the body region 2 and the source region 3;

(6) Depositing a grid electrode 4 made of polycrystalline silicon on the surface of one side of the grid oxide layer 5, which is far away from the drift region 1;

(7) Etching the body region 2 to form a through hole connected with the Schottky metal buried layer 6, wherein the length of the through hole is 1.2 mu m, and the diameter of the through hole is 1 mu m;

(8) Depositing metal Ti in the through hole to form electrode connecting metal 7, and removing redundant metal by etching;

(9) Depositing an isolation dielectric layer on the surface, and forming a grid electrode and a source electrode metal electrode through photoetching, etching and deposition processes; and forming a drain electrode on the back surface through thinning and metallization.

Experimental example 2

Substantially the same as in experimental example 1, except that the buried schottky metal layer in step (2) had a thickness of 75 nm.

Comparative example 1

Substantially the same as in experimental example 1, except that steps (2), (7) and (8) were removed, the resulting device structure can be referred to in fig. 9, wherein reference numeral 9 is a parasitic body diode.

Characterization test:

the following characterization tests were performed on the devices prepared in each of the experimental examples and comparative examples, and the results are shown in table 1:

the on-resistance, the area, the dv/dt tolerance and the avalanche energy of the device are tested by referring to the content of a semiconductor device test standard IEC60747 chapter 8 field effect transistor of the International electrotechnical society;

the forward conduction voltage drop and reverse recovery loss of the diode were tested with reference to the content of chapter 3 of the international electrotechnical society semiconductor device test standard IEC 60747.

As can be seen from table 1, experimental example 1 has better performance in dv/dt tolerance, avalanche energy, forward conduction voltage drop and reverse recovery loss compared with the conventional pure MOSFET device in comparative example 1 because the schottky diode is integrated, and meanwhile, because the schottky diode is integrated in the device through design, the on-resistance and the area of the chip are not increased, the production cost can be effectively reduced, and the device performance is improved.

In experimental example 2, the schottky buried metal layer was thinned to 75 a nm a, and the performance was significantly better than that of comparative example 1, although the performance was slightly degraded compared to that of experimental example 1.

The technical features of the above-described experimental examples may be arbitrarily combined, and all possible combinations of the technical features in the above-described experimental examples are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above experimental examples only represent a few embodiments of the present invention, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. The scope of the invention is therefore intended to be covered by the appended claims, and the description and drawings may be interpreted in accordance with the contents of the claims.

Claims (10)

1. A silicon carbide MOSFET device, comprising: the semiconductor device comprises a drift region of a silicon carbide doped first conductivity type semiconductor material, a Schottky contact metal buried layer, a body region of a silicon carbide doped second conductivity type semiconductor material, an electrode connecting metal, a source region of the silicon carbide doped first conductivity type semiconductor material, a gate oxide layer and a gate electrode;

in each cell:

the drift region comprises at least two first groove structures, and the Schottky contact metal buried layer is arranged on the inner bottom surface of the first groove structures;

the body region is arranged on one side surface of the Schottky contact metal buried layer, which is far away from the drift region;

the body region comprises at least two second groove structures and at least one through hole, the second groove structures are not connected with the Schottky contact metal buried layer, one side of the through hole is connected with the Schottky contact metal buried layer, the source region is filled in the second groove structures, and the electrode connecting metal is filled in the through hole;

the surface of the interval region of two adjacent first groove structures in the drift region is sequentially provided with the gate oxide layer and the grid electrode, and the gate oxide layer partially covers the body region and the source region;

wherein the first conductive type semiconductor is a P-type semiconductor and the second conductive type semiconductor is an N-type semiconductor, or the first conductive type semiconductor is an N-type semiconductor and the second conductive type semiconductor is a P-type semiconductor; the Schottky contact metal buried layer and the drift region form Schottky contact, and the Schottky contact metal buried layer and the body region form ohmic contact.

2. The silicon carbide MOSFET device of claim 1, wherein the buried schottky metal layer comprises one or more of Ti, mo, ni, au and Pt.

3. The silicon carbide MOSFET device of claim 1, wherein the schottky metal buried layer has a thickness of 50 a nm a to 5000 a nm a.

4. The silicon carbide MOSFET device of claim 1, wherein the electrode-connecting metal comprises one or more of Ti, mo, ni, W, cu and Al.

5. The silicon carbide MOSFET device of claim 1, wherein the via has a length of 0.2 μm to 10 μm and a diameter of 0.05 μm to 5 μm.

6. The silicon carbide MOSFET device of any of claims 1-5, wherein the drift region further comprises one or more sub-doped regions, the sub-doped regions being of a silicon carbide doped semiconductor of the second conductivity type.

7. The silicon carbide MOSFET device of any of claims 1-5, wherein the gate oxide layer comprises one or more of silicon dioxide, hafnium oxide, titanium oxide, aluminum oxide, and tantalum oxide.

8. The silicon carbide MOSFET device according to any one of claims 1-5, wherein the gate is made of one or more of polysilicon, tungsten silicide, titanium silicide and nickel silicide.

9. The method for manufacturing a silicon carbide MOSFET device according to any one of claims 1 to 8, comprising the steps of:

a. providing a silicon carbide epitaxial wafer doped with a first conductive type semiconductor, and etching the silicon carbide epitaxial wafer doped with the first conductive type semiconductor to form a first groove structure to obtain a drift region;

b. depositing schottky metal on the inner bottom surface of the first groove structure to form a schottky metal buried layer;

c. preparing a body region in the first groove structure formed with the schottky metal buried layer;

d. photoetching and ion implantation are carried out on the body region to form a source region; preparing a gate oxide layer on a plane formed by the drift region, the body region and the source region, and enabling the gate oxide layer to partially cover the drift region, the body region and the source region; preparing a grid electrode on the surface of one side of the grid oxide layer far away from the drift region;

e. etching the body region to form a through hole connected with the Schottky metal buried layer, and depositing metal in the through hole to form electrode connection metal;

wherein, step d and step e are separated in no sequence.

10. A chip comprising a silicon carbide MOSFET device according to any one of claims 1 to 8.

Images