CN115801503A - LVDS parallel data automatic calibration circuit and method for cross-chip interconnection - Google Patents
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Abstract
The invention discloses an automatic calibration circuit and method for LVDS parallel data of cross-chip interconnection, which comprises an upstream bare chip sending end and a downstream bare chip receiving end; the upstream bare chip sending end comprises a first data isolator and a self-checking data generator; the downstream bare chip receiving end comprises a second data isolator, a self-checking data detector and a channel delay adjuster; the invention can generate detection data which can highlight the time sequence difference problem, can accurately judge the alignment condition of each channel according to the sampling result of the self-checking data, and can adjust the time delay of the clock and each data channel according to a proper algorithm. In addition, the invention can actively suspend the cross-chip transmission of normal data packets in the calibration process, thereby avoiding the loss of the data packets to be transmitted in the cross-chip in the upstream bare chip or the influence of the self-test data flowing into the network in the downstream bare chip on the normal operation of the upstream bare chip. The whole process does not need human intervention, detection and repair are completed by the hardware circuit, and manpower is saved.
Description
Technical Field
The invention relates to the field of multi-core system calibration, in particular to an automatic calibration circuit and method for cross-chip interconnection-oriented LVDS parallel data.
Background
In the context of high performance computing and big data applications, system architects are constantly required to integrate more cores, accelerators, and memory within a given power range. As the development of integrated circuit technology enters the aftermolarity, the limitations of electronics and physics make the continuous scaling and upgrading of advanced semiconductor processes more and more difficult. The solution of continuously realizing a large-scale system by a single chip inevitably faces the problems of greatly reduced yield, sharply increased design and mask costs, and the like. The scheme of changing the traditional single chip design scheme into a multi-chip design scheme and utilizing a high-speed interface for interconnection or utilizing an advanced packaging process for integration becomes a better choice. LVDS (Low Voltage Differential Signaling) is a Differential signal technology with Low swing, has the advantages of Low power consumption, low bit error rate, low crosstalk and Low radiation, and can meet the requirement of high-speed interconnection between the trans-die.
However, the multi-chip design may additionally introduce problems or failures caused by cross-chip interconnection while improving system performance and reducing complexity of large-scale system design. Because the PCB wiring and the inter-chip interface part may introduce a clock skew (time skew), the LVDS parallel data has problems of phase drift and incomplete high-low level duty cycle during the cross-chip transmission process, which may cause sampling errors of the inter-chip transmission data by a downstream chip, and further cause data packet errors and even loss.
Aiming at the problem that LVDS parallel data has time sequence difference to cause transmission error, the aim that each data channel can be aligned with a clock channel is achieved by adjusting channel delay. In the traditional method, each channel delay coefficient is manually adjusted, and after the sampling result of each channel is observed through a continuous test, each channel delay coefficient is repeatedly corrected until the parallel data sampling is completely correct, so that the time and the labor are consumed. Therefore, it is necessary to design a full-automatic calibration circuit, which can perform self-checking on the alignment status of the data channels and automatically adjust the delay coefficients of the channels according to the detection result, so as to liberate manpower and achieve convenient and efficient automatic calibration effects.
Disclosure of Invention
Aiming at the defects in the prior art, the cross-chip interconnection-oriented automatic calibration circuit and method for the LVDS parallel data solve the problems of time and labor consumption of the conventional LVDS parallel data calibration.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that:
the LVDS parallel data automatic calibration circuit for cross-chip interconnection comprises an upstream bare chip sending end and a downstream bare chip receiving end; the upstream bare chip sending end comprises a first data isolator and a self-checking data generator; the downstream bare chip receiving end comprises a second data isolator, a self-checking data detector and a channel delay adjuster;
the self-checking data generator is used for generating self-checking data with a determined format for each channel in a calibration state, namely self-checking parallel data;
the self-checking data detector is used for generating a calibration enabling signal when calibration is needed and sending the calibration enabling signal to the sending end of the upstream bare core; in a calibration state, comparing effective self-checking parallel data received within a period of time with known self-checking data to obtain alignment information of a channel and submitting the alignment information to a channel delay adjuster; generating a calibration completion signal after the calibration is completed and sending the signal to the sending end of the upstream bare chip;
the channel delay adjuster is used for correspondingly adjusting the delay of the clock channel and the data channel according to the alignment information of the channels;
a first data isolator to prevent data packets within an upstream die from flowing to an inter-chip link in a calibration state;
a second data isolator to prevent self-test data from flowing into a downstream die in a calibration state.
Further, after the adjusted delay of each channel is stable, the self-checking data of a period of time is received again through the self-checking data detector, the alignment information of the channels is obtained, and if the data channels are not aligned, the delay of the clock channel or the data channel is continuously adjusted through the channel delay adjuster.
Further, the internal signal of the transmitting end of the upstream bare chip comprises: the method comprises the steps of outputting a local clock, a clock for generating self-checking data, in-chip output data, an in-chip output data valid indication, a downstream bare chip input channel idle indication, self-checking data output, a self-checking data valid indication output, a calibration enable signal and a calibration end signal;
the LVDS interface at the upstream die transmit end is to: sending a clock, sending in-chip output data or self-checking data, sending in-chip output data valid indication signals or self-checking data, sending self-checking data valid indication signals, receiving downstream bare chip input channel idle indication signals, receiving calibration enabling signals, and receiving calibration completion signals;
the internal signal of the receiving end of the downstream bare core comprises: an external clock input and a clock sampling self-checking data, inter-chip input data, an inter-chip input data valid indication, a local input channel idle indication, a self-checking data input, a self-checking data valid indication input, a calibration enable signal, a calibration end signal, a calibration success signal, a calibration failure signal, and a channel alignment indication;
the LVDS interface at the receive end of the downstream die is to: receiving a clock, receiving inter-chip input data, receiving an inter-chip input data valid indication signal or self-check data, receiving a self-check data valid indication signal, sending a local input channel idle indication signal, sending a calibration enable signal, and sending a calibration completion signal.
The method for automatically calibrating the LVDS parallel data for cross-chip interconnection comprises an automatic calibration system for the LVDS parallel data for cross-chip interconnection, and further comprises the following steps:
s1, setting a calibration enabling signal of a downstream bare chip receiving end to be 1, and sending the calibration enabling signal to an upstream bare chip sending end;
s2, judging whether the calibration enabling signal received at the transmitting end of the upstream bare chip is high or not, and if so, entering the step S3; otherwise, repeating the current step;
s3, enabling the sending end of the upstream bare chip to enter a calibration state, preventing a data packet in the upstream bare chip from flowing to an inter-chip link, generating self-checking data with a determined format, and simultaneously pulling up an effective signal of the self-checking data;
s4, judging whether a self-checking data effective signal received at a downstream bare chip receiving end is high or not, and if so, entering the step S5; otherwise, no processing is carried out;
s5, enabling a downstream bare chip receiving end to enter a calibration state, receiving self-checking data and preventing the self-checking data from flowing into the downstream bare chip;
s6, comparing the effective self-checking parallel data received within a period of time with the known self-checking data, acquiring the alignment information of the channel and submitting the alignment information to the channel delay adjuster;
s7, correspondingly adjusting the time delay of the clock channel and the data channel according to the alignment information of the channels;
s8, generating a calibration completion signal and sending the calibration completion signal to an upstream bare chip sending end;
s9, stopping generating self-checking data through the sending end of the upstream bare chip, setting a self-checking data effective signal to be 0, and sending the self-checking data effective signal to the receiving end of the downstream bare chip to allow the data packet in the upstream bare chip to flow to the inter-chip link;
s10, judging whether a downstream bare chip receiving end detects that a self-checking data effective signal is low, if so, allowing inter-chip data in the downstream bare chip to flow into a chip, and completing automatic calibration; otherwise, inter-chip data in the downstream bare chip is continuously prevented from flowing into the chip.
Further, the specific method for generating the self-test data with the determined format in step S3 is as follows:
and assigning 0 and 1 to each bit of the self-checking data alternately, namely enabling the 1 st to the m-th LVDS channels to transmit signals 0 and 1 alternately.
Further, the specific method of step S6 includes the following sub-steps:
s6-1, continuously receiving effective self-checking parallel data, and enabling the effective self-checking data of each data channel to be sampled at least 256 times;
s6-2, acquiring the error sampling times of each data channel: for each data channel, performing bit identity or on the current sampling data and the last sampling data, and if the identity or result is 1, judging that the sampling is wrong for 1 time;
s6-3, judging whether the number of wrong sampling times of a data channel in at least 256 sampling times exceeds a set value, and if so, judging that the data channel is not aligned with a clock channel; otherwise, the data channel and the clock channel are judged to be in an aligned state.
Further, the specific method of step S7 includes the following substeps:
s7-1, judging whether all the channels are in an aligned state or not according to the alignment information of the channels, and if so, entering a step S8; otherwise, entering step S7-2;
s7-2, obtaining a delay coefficient of a clock channel which enables data channels larger than a set number to be sampled correctly by adjusting the delay coefficient of the clock channel;
s7-3, respectively adjusting the delay coefficients of all the data channels, judging whether all the data channels can be correctly sampled under the delay coefficient of the current clock channel, setting a calibration success signal calib _ good to 1 if the data channels can be correctly sampled, and entering a step S8; otherwise, entering step S7-4;
s7-34, judging whether all the channel delay combinations are traversed or not, if so, setting a calibration failure signal calib _ fail to 1, and entering the step S8; otherwise, adjusting the delay coefficient of the clock channel and returning to the step S7-3.
Further, the set value in step S6-3 is 2.
The invention has the beneficial effects that: the invention can automatically generate the detection data which can highlight the time sequence difference problem at proper time, can accurately judge the alignment condition of each channel according to the sampling result of the self-checking data, and then automatically adjusts the time delay of the clock and each data channel according to a proper algorithm. In addition, the invention can actively suspend the cross-chip transmission of normal data packets in the calibration process, thereby avoiding the loss of the data packets to be transmitted in the cross-chip in the upstream bare chip or the influence of the self-test data flowing into the network in the downstream bare chip on the normal operation of the upstream bare chip. The whole process does not need manual intervention, detection and repair are completed by a hardware circuit, and manpower is saved.
Drawings
FIG. 1 is a block diagram of the present auto-calibration circuit;
FIG. 2 is a schematic flow chart of the method.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
As shown in fig. 1, the LVDS parallel data auto-calibration circuit facing cross-chip interconnect includes an upstream die sending end and a downstream die receiving end; the upstream bare chip sending end comprises a first data isolator and a self-checking data generator; the downstream bare chip receiving end comprises a second data isolator, a self-checking data detector and a channel delay adjuster;
the self-checking data generator is used for generating self-checking data with a determined format for each channel in a calibration state, namely self-checking parallel data, and setting a self-checking data effective signal to be 1;
the self-checking data detector is used for generating a calibration enabling signal when calibration is needed and sending the calibration enabling signal to the sending end of the upstream bare chip; in a calibration state, comparing effective self-checking parallel data received within a period of time with known self-checking data, acquiring alignment information of a channel (namely whether a signal transmitted by a data channel can be correctly sampled by a clock transmitted by a clock channel) and submitting the alignment information to a channel delay adjuster; generating a calibration completion signal after the calibration is completed and sending the signal to the sending end of the upstream bare chip;
the channel delay adjuster is used for correspondingly adjusting the delay of the clock channel and the data channel according to the alignment information of the channels;
a first data isolator for preventing data packets within an upstream die from flowing to an inter-chip link in a calibration state;
a second data isolator to prevent self-test data from flowing into a downstream die in a calibration state.
In the specific implementation process, the states of the calibration enable signal and the calibration complete signal are both generated at the receiving end and transmitted to the transmitting end through the LVDS link, and the operation state of the whole calibration circuit is controlled by the two signals. When the calibration enable signal is high and the calibration complete signal is low, it represents that the inter-chip signal transmission path is in calibration.
In one embodiment of the present invention, it is assumed that the channels to be calibrated include 1 channel for transmitting a clock, 77 channels for transmitting data, and 1 channel for transmitting an inter-chip data valid indication signal, that is, channels 0 to 78. A brief description of the internal signal of the transmitting end of the upstream bare chip, the internal signal of the receiving end of the downstream bare chip, the LVDS interface signal of the transmitting end of the upstream bare chip, and the LVDS interface signal of the receiving end of the downstream bare chip is shown in tables 1 to 4.
Table 1: upstream bare core sending terminal internal signal
Table 2: downstream bare chip receiving end internal signal
Table 3: LVDS interface signal of upstream bare chip sending end
Table 4: LVDS interface signal of downstream bare chip receiving end
It should be noted that the OD _ LANEi interface and the ID _ LANEi interface are connected by the ith LVDS channel.
In this embodiment, the automatic calibration method may specifically be:
the calibration enable signal ENCALIB _ RX of the receiving end of the downstream die is first set to 1. The signal is transmitted from the OD _ LANE81 to the ID _ LANE81 through the 81 th LVDS channel, and then connected to the ENCALIB _ TX signal at the transmitter end of the upstream die.
When the transmitter of the upstream bare chip detects that the calibration enable signal ENCALB _ TX is high, the data isolator can prevent the data in the chip from flowing to the chip. The specific method is that the CPREADY is always assigned 0, and the input channel of the downstream bare chip is supposed to be always non-idle, so that the data packet to be transmitted across the chip in the upstream bare chip is temporarily stored in the local output channel. At the same time, OD _ LANE 1-78 will connect to the TEST _ DATA _ TX signal, ready to transmit self-TEST DATA.
The transmitting-end self-TEST DATA generator generates self-TEST DATA TEST _ DATA _ TX in a determined format, and simultaneously pulls up a self-TEST DATA VALID signal TEST _ VALID _ TX. The self-TEST generation mode is that 78'h0 and 78' h3FFFFFFFFFFFFFFFFFFF are alternately assigned to the self-TEST DATA TEST _ DATA _ TX, namely, the 1 st to 78 th LVDS channels alternately transmit the signal 0 and the signal 1. The self-test data valid signal will be connected to OD _ LANE79 and transmitted to the downstream die receiver using the 79 th LVDS channel.
When the receiving end of the downstream bare chip detects that the self-TEST data VALID signal TEST _ VALID _ RX is high, the data isolator prevents the inter-chip data from flowing into the downstream bare chip. The specific method is that the CPIVALID is always assigned with 0, and the input data between the chips is assumed to be invalid, so that the received self-checking data can not influence the on-chip network. Meanwhile, the ID _ LANE1 to 78 are connected to the TEST _ DATA _ RX, and the ID _ LANE79 is connected to the TEST _ VALID _ RX to prepare for receiving self-TEST DATA.
For the same channel, effective self-checking data are sampled at least 256 times in total, and the sampled data of the last time are subjected to bit matching each time. If the result of the same or of the nth channel is 1, the current sampling data of the channel is the same as the last sampling data. However, each channel alternately sends a signal 0 and a signal 1, so that it can be proved that the channel with the same or result of 1 is not correctly sampled by the clock transmitted by the clock channel. To prevent misjudging a channel from being misaligned, a data channel is considered misaligned with the clock channel only if it is sampled more than 2 times out of 256 samples. And recording the result of judging the alignment state of each data channel at the current time by using a 78-bit align _ status register at the receiving end of the downstream bare chip.
If align _ status is 78' h0, that is, all data channels can be correctly sampled, a calibration complete signal is directly generated and sent to the sending end of the upstream die, and a calibration successful signal calib _ good is set to 1. Otherwise, firstly adjusting the delay coefficient of the clock channel, finding a state which can enable most data channels to be correctly sampled, and then respectively adjusting the delay coefficient of each data channel; if all data channels cannot be correctly sampled in the clock channel delay state, the clock channel delay coefficient needs to be adjusted again; each time the time delay of the clock or the data channel is adjusted, whether the time delay combination can enable all the data channels to be correctly sampled needs to be judged again; and if all the channel delay combinations are traversed and all the data channels cannot be aligned with the clock channel at the same time, generating a calibration completion signal and sending the calibration completion signal to the sending end of the upstream bare chip, and setting a calibration failure signal calib _ fail to be 1.
The calibration complete signal calibiover _ RX at the receiving end of the downstream die is determined by the calibration successful signal caliib _ good and the calibration failed signal caliib _ fail, and when any one of them is pulled high, the calibiover _ RX is automatically set to 1. The CALIBUVER _ RX signal is transmitted from OD _ LANE82 to ID _ LANE82 via LVDS channel 82, and then connected to CALIBUVER _ TX signal at the transmitter side of the upstream die.
After the sender of the upstream die detects that the calibration completion signal CALIBOVER _ TX is high, the self-TEST DATA generator stops generating the self-TEST DATA TEST _ DATA _ TX and sets a self-TEST DATA VALID signal TEST _ VALID _ TX to 0. The data isolator will then allow the on-chip data to flow to the inter-chip, i.e. CPIREADY is no longer set to 0 directly, but rather it is connected to ID _ LANE80, so that the network within its upstream die normally senses the working condition of the local input channels of the downstream die. At the same time, OD _ LANE 1-77 are connected to the CPODATA signal, OD _ LANE78 is connected to the CPOVALID signal, and the output data in the upstream die is ready to be transmitted.
After the receiving end of the downstream die detects that the self-TEST data VALID signal TEST _ VALID _ RX is low, the data isolator will allow the inter-chip data to flow into the chip. Specifically, instead of directly setting CPIVALID to 0, the CPIVALID is connected to ID _ LANE78, so that the downstream die normally determines whether inter-chip input data is valid. While CPIDATA is connected to the ID _ LANE1 to 77, the inter-slice input data is ready to be received.
In conclusion, the invention realizes the detection and the automatic repair of the alignment condition of each channel through the hardware circuit, saves the manpower and the time resource, and simultaneously can realize better calibration effect.
Claims (8)
1. The automatic calibration circuit for the LVDS parallel data which are interconnected facing to the cross chip is characterized by comprising an upstream bare chip sending end and a downstream bare chip receiving end; the upstream bare chip sending end comprises a first data isolator and a self-checking data generator; the downstream bare chip receiving end comprises a second data isolator, a self-checking data detector and a channel delay adjuster;
the self-checking data generator is used for generating self-checking data with a determined format for each channel in a calibration state, namely self-checking parallel data;
the self-checking data detector is used for generating a calibration enabling signal when calibration is needed and sending the calibration enabling signal to the sending end of the upstream bare chip; in a calibration state, comparing effective self-checking parallel data received within a period of time with known self-checking data to obtain alignment information of a channel and submitting the alignment information to a channel delay adjuster; generating a calibration completion signal after the calibration is completed and sending the signal to the sending end of the upstream bare chip;
the channel delay adjuster is used for correspondingly adjusting the delay of the clock channel and the data channel according to the alignment information of the channels;
a first data isolator to prevent data packets within an upstream die from flowing to an inter-chip link in a calibration state;
a second data isolator to prevent self-test data from flowing into a downstream die in a calibration state.
2. The cross-chip interconnection-oriented LVDS parallel data automatic calibration circuit according to claim 1, wherein after the adjusted delay of each channel is stable, the self-checking data detector receives the self-checking data for a period of time again to obtain the alignment information of the channels, and if the data channels are still not aligned, the delay of the clock channel or the data channel is continuously adjusted by the channel delay adjuster.
3. The cross-chip interconnect oriented LVDS parallel data auto-calibration circuit according to claim 1, wherein an internal signal at a transmitter end of an upstream die comprises: the method comprises the steps of outputting a local clock, a clock for generating self-checking data, in-chip output data, an in-chip output data valid indication, a downstream bare chip input channel idle indication, self-checking data output, a self-checking data valid indication output, a calibration enable signal and a calibration end signal;
the LVDS interface at the upstream die transmit end is to: sending a clock, sending in-chip output data or self-checking data, sending in-chip output data valid indication signals or self-checking data, sending self-checking data valid indication signals, receiving downstream bare chip input channel idle indication signals, receiving calibration enabling signals, and receiving calibration completion signals;
the internal signal of the receiving end of the downstream bare core comprises: an external clock input and a clock sampling self-checking data, inter-chip input data, an inter-chip input data valid indication, a local input channel idle indication, a self-checking data input, a self-checking data valid indication input, a calibration enable signal, a calibration end signal, a calibration success signal, a calibration failure signal, and a channel alignment indication;
the LVDS interface at the receive end of the downstream die is to: receiving a clock, receiving inter-chip input data, receiving an inter-chip input data valid indication signal or self-check data, receiving a self-check data valid indication signal, sending a local input channel idle indication signal, sending a calibration enable signal, and sending a calibration completion signal.
4. An automatic calibration method for cross-chip interconnection-oriented LVDS parallel data, characterized by comprising the cross-chip interconnection-oriented LVDS parallel data automatic calibration system of any one of claims 1 to 3, and further comprising the following steps:
s1, setting a calibration enabling signal of a downstream bare chip receiving end to be 1, and sending the calibration enabling signal to an upstream bare chip sending end;
s2, judging whether the calibration enabling signal received at the transmitting end of the upstream bare chip is high or not, and if so, entering the step S3; otherwise, repeating the current step;
s3, enabling the sending end of the upstream bare chip to enter a calibration state, preventing a data packet in the upstream bare chip from flowing to an inter-chip link, generating self-checking data with a determined format, and simultaneously pulling up an effective signal of the self-checking data;
s4, judging whether a self-checking data effective signal received at a downstream bare chip receiving end is high or not, and if so, entering the step S5; otherwise, no processing is carried out;
s5, enabling a downstream bare chip receiving end to enter a calibration state, receiving self-checking data and preventing the self-checking data from flowing into the downstream bare chip;
s6, comparing the effective self-checking parallel data received within a period of time with the known self-checking data, acquiring the alignment information of the channel and submitting the alignment information to a channel delay adjuster;
s7, correspondingly adjusting the time delay of the clock channel and the data channel according to the alignment information of the channels;
s8, generating a calibration completion signal and sending the calibration completion signal to an upstream bare chip sending end;
s9, stopping generating the self-detection data through the upstream bare chip sending end, setting a self-detection data effective signal to be 0, sending the self-detection data effective signal to a downstream bare chip receiving end, and allowing an in-chip data packet in the upstream bare chip to flow to an inter-chip link;
s10, judging whether a downstream bare chip receiving end detects that a self-checking data effective signal is low, if so, allowing inter-chip data in the downstream bare chip to flow into a chip, and completing automatic calibration; otherwise, inter-chip data in the downstream bare chip is continuously prevented from flowing into the chip.
5. The method for automatically calibrating LVDS parallel data for cross-chip interconnection according to claim 4, wherein the specific method for generating the self-test data with the determined format in the step S3 is as follows:
and assigning 0 and 1 to each bit of the self-checking data alternately, namely enabling the 1 st to the m-th LVDS channels to transmit signals 0 and 1 alternately.
6. The method for automatically calibrating LVDS parallel data for cross-chip interconnection according to claim 5, wherein the specific method of step S6 comprises the following sub-steps:
s6-1, continuously receiving effective self-checking parallel data, and enabling the effective self-checking data of each data channel to be sampled at least 256 times;
s6-2, acquiring the error sampling times of each data channel: for each data channel, performing bit identity or on the current sampling data and the last sampling data, and if the identity or result is 1, judging that the sampling is wrong for 1 time;
s6-3, judging whether the number of wrong sampling times of a data channel in at least 256 sampling times exceeds a set value, and if so, judging that the data channel is not aligned with a clock channel; otherwise, the data channel and the clock channel are judged to be in an aligned state.
7. The method according to claim 6, wherein the specific method of step S7 comprises the following sub-steps:
s7-1, judging whether all the channels are in an aligned state or not according to the alignment information of the channels, and if so, entering a step S8; otherwise, entering step S7-2;
s7-2, obtaining a delay coefficient of a clock channel which enables data channels larger than a set number to be sampled correctly by adjusting the delay coefficient of the clock channel;
s7-3, respectively adjusting the delay coefficients of all the data channels, judging whether all the data channels can be correctly sampled under the delay coefficient of the current clock channel, setting a calibration success signal calib _ good to 1 if the data channels can be correctly sampled, and entering a step S8; otherwise, entering step S7-4;
s7-34, judging whether all the channel delay combinations are traversed or not, if so, setting a calibration failure signal caliib _ fail to 1, and entering the step S8; otherwise, adjusting the delay coefficient of the clock channel and returning to the step S7-3.
8. The method according to claim 6, wherein the set value in step S6-3 is 2.
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