TW201520775A - Differential signal testing system for interface and method thereof - Google Patents

Abstract

A differential signal testing system for interface and method thereof is disclosed. By electrically connecting a loop device and a testing end at interface, and producing a pseudo-random binary sequence (PRBS) from the testing end and using a boundary scan method for testing the interface, so as to obtain a bit error rate (BER) of the interface and to obtain a short-circuit state and open-circuit state of a differential signal circuit according to the feedback differential signal by the loop device. The mechanism is help to improve the testing coverage rate of the differential signal.

Description

Differential interface test system for connecting interface and method thereof

The invention relates to a signal testing system and a method thereof, in particular to a differential signal testing system and a method for testing a connection interface of a differential signal line of a connection interface according to a differential signal.

In recent years, with the popularization and vigorous development of hard disks, the traditional busbars have gradually become insufficient in bandwidth. Therefore, the bandwidth and compatibility of the expansion busbars have become a consensus. For example, the International Standards Organization proposed The interface specification of "SFF-8639" is to support interfaces such as "PCI Express", "SATA" and "SAS". However, while improving bandwidth and compatibility, how to quickly and effectively test the connection interface has become one of the problems that various manufacturers are eager to solve.

In general, the traditional connection interface test method is implemented by using a server and a large number of hard disks, and the connection interface is tested to meet the requirements by actually connecting the hard disk. However, this method requires a lot of time for testing and a large number of hard disks, so it has problems of low test efficiency and high cost.

In view of this, some manufacturers have proposed a test-end device to perform signal test on the connection interface by means of a probe, without actually connecting a large number of hard disks, thereby saving a large amount of test time and cost. However, this approach has the problem of poor test coverage of differential signals.

In summary, it can be known that the test coverage of differential signals has been poor in the prior art for a long time, so it is necessary to propose an improved technical means to solve this problem.

The invention discloses a differential interface test system for connecting interfaces and a method thereof.

First, the present invention discloses a differential interface test system for connecting interfaces for testing a connection interface having a differential signal line. The system includes a loop device and a test terminal, and the loop device is electrically connected to the connection interface for self-connection. The interface receives the differential signal and synchronously feeds the differential signal back to the connection interface. The test end is electrically connected to the connection interface, and the test end comprises: a first test module and a second test module. The first test module is configured to generate a set of pseudo random binary sequences (PRBS), and transmit the pseudo random binary sequence to the connection interface as a differential signal, and test the connection according to the feedback differential signal. The bit error rate (BER) of the serial channel transmission of the interface; the second test module is used to test a single signal in each pair of differential signal lines on the connection interface by using a Boundary Scan method. Short circuit and open circuit status of the line.

In addition, the present invention discloses a differential interface test method for testing a connection interface for testing a connection interface having a differential signal line, the method comprising: electrically connecting a loop device to a connection interface, and electrically connecting the test end to the connection interface; The test end generates a set of pseudo-random binary sequences, and transmits the set of pseudo-random binary sequences to the connection interface as differential signals; the loop device receives the differential signals from the connection interface, and synchronously feeds the differential signals back to the connection interface; the test end is based on the feedback The differential signal tests the bit error rate of the serial channel transmission of the connection interface; the test end uses the boundary scan method to test the short circuit and open state of a single signal line in each pair of differential signal lines on the connection interface.

The system and method disclosed in the present invention are as above, and the difference from the prior art is that the present invention electrically connects the loop device and the test end in the connection interface, and generates a pseudo-random binary sequence from the test end and tests the connection interface by using a boundary scan method. In order to obtain the bit error rate of the connection interface and the short circuit and open state of the differential signal line according to the differential signal fed back by the loop device.

Through the above technical means, the present invention can achieve the technical effect of improving the test coverage of differential signals.

110‧‧‧Connection interface

111‧‧‧Differential signal line

120‧‧‧Circuit device

130‧‧‧Test end

131‧‧‧First test module

132‧‧‧Second test module

133‧‧‧Signal multiplexer

300‧‧‧Signal adjustment retimer

Step 210 ‧ ‧ electrically connecting the primary circuit device to the connection interface, and electrically connecting a test terminal to the connection interface

Step 220‧‧‧ The test end generates a set of pseudo-random binary sequences, and transmits the set of pseudo-random binary sequences to the connection interface as a differential signal

Step 230‧‧ The circuit device receives the differential signal from the connection interface, and the difference is Signal synchronization feedback to the connection interface

Step 240‧‧‧ The test end tests the bit error rate of the serial channel transmission of the connection interface according to the feedback differential signal

Step 250‧‧‧ The test end uses the boundary scan method to test the short circuit and open state of a single signal line in each pair of differential signal lines on the connection interface

1 is a system block diagram of a differential signal test system for a connection interface of the present invention.

2 is a flow chart of a method for testing a differential signal of a connection interface of the present invention.

Figure 3 is a circuit diagram showing the differential signal test of the connection interface of the present invention.

The embodiments of the present invention will be described in detail below with reference to the drawings and embodiments, so that the application of the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented.

Before describing the differential signal testing system and method for the connection interface disclosed in the present invention, the terminology defined by the present invention will be described. The connection interface of the present invention may also be referred to as a connection backplane, a connection slot, and a connection port. And so on, it has a differential signal line. For example, a connection interface conforming to the "SFF-8639" interface specification can support a hard disk device using interfaces such as "PCI Express", "SATA", and "SAS".

The differential signal test system and method for the connection interface of the present invention are further described below with reference to the drawings. Please refer to FIG. 1 and FIG. 1 is a system block diagram of a differential signal test system for a connection interface of the present invention. A connection interface 110 having a differential signal line is tested. The system includes a loop device 120 and a test terminal 130. The loop device 120 is electrically connected to the connection interface 110 for receiving the differential signal from the connection interface 110 and synchronously feeding back the differential signal to the connection interface 110. In an actual implementation, one end of the connection interface 110 is electrically connected to the circuit device 120, and the other end of the connection interface 110 is electrically connected to the test end 130. The electrical connection manner conforms to the "SFF-8639" interface specification. In other words, the signal generated by the test terminal 130 is first transmitted to the loop device 120 via the connection interface 110, and the loop device 120 directly feeds back the signal back to the connection interface 110 and then from the connection interface 110 to the test terminal 130.

The test terminal 130 is configured to be electrically connected to the connection interface 110. The test terminal 130 includes: a first test module 131 and a second test module 132. The first test module 131 is configured to generate a Pseudo Random Binary Sequence (PRBS), and transmit the pseudo random binary sequence to the connection interface 110 as a differential signal, and the differential signal according to the feedback. The bit error rate (BER) of the serial channel transmission of the connection interface 110 is tested. In practical implementation, the differential signal lines of the connection interface can be used to verify the signal characteristics of each differential signal line in the high-speed differential mode at a rate of 2.5G, 5.0G, and 8.0 Gbps, respectively, and the difference is known according to the bit error rate. The quality of the signal line.

The second test module 132 is configured to test the short circuit and open state of a single signal line in each pair of differential signal lines on the connection interface 110 by using a Boundary Scan method. In practical implementation, the boundary scan is to test the AC-coupled circuit according to the rising speed of the differential signal. The test mode is implemented according to the 1149.6 standard formulated by the Joint Test Action Group (JTAG), which belongs to the differential signal. A test method that enables the characteristic test of an AC coupling circuit. Since the 1149.6 standard is a conventional technique, it will not be repeated here.

In particular, the test terminal 130 further includes a signal multiplexer 133 for controlling signal transmission of the first test module 131 and the second test module 132, that is, signal multiplexing. The device 133 can transmit the pseudo-random binary sequence generated by the first test module 131 and the signal generated when the second test module 132 uses the boundary scan mode to the connection interface 110 and receive the feedback signal in a multiplexed manner, and feedback The signal is transmitted to the corresponding first test module 131 or second test module 132.

Next, please refer to "Figure 2", "Figure 2" is the invention The differential signal testing method of the interface includes the steps of: electrically connecting the circuit device 120 to the connection interface 110, and electrically connecting the test terminal 130 to the connection interface 110 (step 210); the test terminal 130 generates a set of pseudo-random binary Sequence, and transmitting the set of pseudo-random binary sequences to the connection interface 110 as a differential signal (step 220); the loop device 120 receives the differential signal from the connection interface 110 and synchronously feeds the differential signal back to the connection interface 110 (step 230); The terminal 130 tests the bit error rate of the serial channel transmission of the connection interface 110 according to the feedback differential signal (step 240); the test terminal 130 tests the single signal in each pair of differential signal lines on the connection interface 110 using the boundary scan mode. The short circuit and open state of the line (step 250). Through the above steps, the connection interface 110 can be tested by connecting the circuit device 120 and the test terminal 130 to the connection interface 110, and the pseudo-random binary sequence is generated by the test terminal 130 and using the boundary scan mode, so as to be fed back according to the loop device 120. The differential signal obtains the bit error rate of the connection interface 110 and the short-circuit and open-circuit states of the differential signal line, thereby improving the test coverage of the differential signal.

The following is a description of the embodiment with reference to "FIG. 3". Please refer to FIG. 3, which is a circuit diagram of the differential signal test of the connection interface of the present invention. In actual implementation, the first test module 131 and the second test module 132 of the test terminal 130 can be generated by using a signal adjustment retimer 300 (eg, wafer "IDT 89HT0816P") as shown in FIG. a test model of the differential signal, that is, a pseudo-random binary sequence and a boundary-scanned signal, and the test model is transmitted via the signal multiplexer 133 to the differential signal line 111 of the connection interface 110 (which may also be referred to as a terminal to be tested), and then Feedback is then made via the loopback of loop device 120. The feedback differential signal first passes through the differential signal line 111 of the connection interface 110, passes through the signal multiplexer 133 of the test terminal 130, and is finally received by the receiving end of the signal conditioning retimer 300 of the test terminal 130 to determine the connection. The bit error rate of the serial channel transmission of the interface 110, and the short circuit and open state of the single signal line in each pair of differential signal lines 111 on the connection interface 110 are determined. In other words, by controlling the signal adjustment retimer 300 The pseudo-random binary sequence and boundary scan test in loop mode realize high coverage test of differential signals.

In summary, it can be seen that the difference between the present invention and the prior art is that the connection interface is tested by electrically connecting the loop device and the test end in the connection interface, and the pseudo-random binary sequence is generated by the test end and the boundary scan mode is used to test the connection interface. The differential signal fed back by the loop device obtains the bit error rate of the connection interface and the short-circuit and open-circuit state of the differential signal line, and the technical problem can be solved by the prior art, thereby achieving the technique of improving the test coverage of the differential signal. efficacy.

While the present invention has been described above in the foregoing embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of patent protection shall be subject to the definition of the scope of the patent application attached to this specification.

110‧‧‧Connection interface

120‧‧‧Circuit device

130‧‧‧Test end

131‧‧‧First test module

132‧‧‧Second test module

133‧‧‧Signal multiplexer

Claims (10)

A differential signal test system for connecting interfaces for testing a connection interface having a differential signal line, the system comprising: a loop device electrically connected to the connection interface for receiving a differential signal from the connection interface And synchronously feeding back the differential signal to the connection interface; and a test end for electrically connecting to the connection interface, the test end comprising: a first test module for generating a set of pseudo-random binary sequences ( Pseudo Random Binary. Sequence, PRBS), and transmitting the set of pseudo-random binary sequences to the connection interface as the differential signal, and testing the bit error rate of the serial channel transmission of the connection interface according to the feedback differential signal (Bit Error Rate, BER); and a second test module for testing the short circuit and open state of a single signal line in each pair of differential signal lines on the connection interface using a Boundary Scan method. According to the differential signal test system of the connection interface of claim 1, wherein the electrical connection manner of the circuit device and the connection interface, and the electrical connection manner between the connection interface and the test end are in accordance with the SFF-8639 interface specification. A differential signal test system for a connection interface according to claim 1 of the patent application, wherein the boundary scan is to test the AC coupling circuit according to the rising speed of the differential signal. A differential signal test system for a connection interface according to claim 1 of the patent application, wherein the rate of the differential signal includes at least 2.5G, 5.0G, and 8.0 Gbps. The differential signal test system of the connection interface according to the first aspect of the patent application, wherein the test end further comprises a signal multiplexer for controlling signal transmission of the first test module and the second test module. A method for testing a differential signal of a connection interface for testing a connection interface having a differential signal line, the method comprising: electrically connecting a primary circuit device to the connection interface, and electrically connecting a test terminal to the connection interface; The test end generates a Pseudo Random Binary Sequence (PRBS), and transmits the set of pseudo-random binary sequences to the connection interface as a differential signal; the loop device receives the differential signal from the connection interface, And synchronously feeding back the differential signal to the connection interface; the test end tests a bit error rate (BER) of the serial channel transmission of the connection interface according to the feedback differential signal; and the boundary scan is used by the test end (Boundary Scan) mode, testing the short circuit and open state of a single signal line in each pair of differential signal lines on the connection interface. a differential signal test method for a connection interface according to claim 6 of the patent application, wherein the circuit device is electrically connected to the connection interface, and The electrical connection between the connection interface and the test end conforms to the SFF-8639 interface specification. The differential signal test method of the connection interface according to claim 6 of the patent application, wherein the boundary scan tests the AC coupling circuit according to the rising speed of the differential signal. A differential signal test method for a connection interface according to claim 6 of the patent application, wherein the rate of the differential signal includes at least 2.5G, 5.0G, and 8.0 Gbps. According to the differential signal test method of the connection interface of claim 6, wherein the pseudo-random binary sequence and the boundary scan mode signal transmission are controlled by a signal multiplexer.