CN115799391A - Preparation method of P-type IBC battery - Google Patents
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- CN115799391A CN115799391A CN202211513555.7A CN202211513555A CN115799391A CN 115799391 A CN115799391 A CN 115799391A CN 202211513555 A CN202211513555 A CN 202211513555A CN 115799391 A CN115799391 A CN 115799391A
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Abstract
The invention relates to a preparation method of a P-type IBC battery, which comprises the following steps: (1) preprocessing a P-type silicon wafer; (2) Depositing a tunneling oxide layer on the back of a silicon wafer, and depositing a phosphorus-doped amorphous silicon layer; (3) Removing the winding coating on the front side of the silicon wafer, and depositing a front side mask layer on the front side of the silicon wafer; (4) Carrying out first laser grooving on the back of the silicon wafer, and then carrying out acid washing; (5) depositing a back mask layer on the back of the silicon wafer; (6) carrying out secondary laser grooving on the back of the silicon wafer; (7) cleaning the silicon wafer by adopting a cleaning solution; (8) And sequentially carrying out oxidation annealing, back passivation layer deposition on the back of the silicon wafer, electrode preparation and sintering treatment on the silicon wafer. According to the cell preparation method provided by the invention, the residual doped polycrystalline silicon layer is reduced as much as possible through secondary laser ablation, the corrosion amount of the side wall can be controlled by combining a milder wet chemical method, the widening of the P region is reduced, and the obtained patterns of the P region and the N region are more regular, so that the efficiency of the cell is improved.
Description
Technical Field
The invention belongs to the field of solar cell preparation, and particularly relates to a preparation method of a P-type IBC cell.
Background
At present, in the process of preparing a P-IBC battery, a laser ablation method is generally used to remove a tunneling SiOx layer and a doped Poly-Si layer in a P region, so as to form the P region, but the laser ablation method cannot completely remove the doped Poly-Si layer, and a chemical treatment needs to be performed at a later stage to remove the residual tunneling SiOx layer and the doped Poly-Si layer.
Disclosure of Invention
The invention aims to provide an improved preparation method of a P-type IBC battery.
In order to achieve the purpose, the invention adopts the technical scheme that:
a preparation method of a P-type IBC battery comprises the following steps:
(1) Preprocessing a P-type silicon wafer;
(2) Depositing a tunneling oxide layer on the back surface of the silicon wafer, and depositing a phosphorus-doped amorphous silicon layer on the tunneling oxide layer on the back surface of the silicon wafer;
(3) Removing the winding coating on the front side of the silicon wafer, and depositing a front side mask layer on the front side of the silicon wafer;
(4) Carrying out first laser grooving on the back of the silicon wafer, and then carrying out acid washing;
(5) Depositing a back mask layer on the back of the silicon wafer;
(6) Performing secondary laser grooving on the back of the silicon wafer;
(7) Cleaning the silicon wafer by adopting a cleaning solution;
(8) And sequentially carrying out oxidation annealing, back passivation layer deposition on the back of the silicon wafer, electrode preparation and sintering treatment on the silicon wafer.
Preferably, in the step (7), the cleaning solution is a mixed solution of hydrogen peroxide and an acid solution, and the acid solution is a hydrofluoric acid solution or a mixed solution of hydrofluoric acid and hydrochloric acid.
Preferably, in the cleaning solution, the volume ratio of the hydrogen peroxide to the water to the acid solution is (20-40): 100: (40-80).
Preferably, in the step (7), the cleaning solution contains an acid solution and ozone, and the acid solution is a hydrofluoric acid solution or a mixed solution of hydrofluoric acid and hydrochloric acid.
Preferably, the concentration of ozone is 0.2-0.6mg/L.
Preferably, in the step (7), the time for cleaning the silicon wafer by using the cleaning solution is 30 seconds to 300 seconds, and the reaction temperature is normal temperature.
Preferably, in the step (4), performing first laser grooving on the back surface of the silicon wafer to form a first groove; and (6) performing laser grooving at the first grooving position to form a second grooving.
Preferably, in the step (4), the line width of the slots is 100-150um, and the center distance between the slot lines is 0.8-1.2mm; in the step (6), the line width of the slots is 85-125um, and the center distance between the slot lines is 0.8-1.2mm.
Preferably, after step (7) and before step (8), further comprising: and (3) cleaning the cell piece in an acid solution, wherein the acid solution is a hydrofluoric acid solution or a mixed solution of hydrofluoric acid and hydrochloric acid, and the purpose of the step is to remove the SiNx mask layer residual on the back surface.
Preferably, in the step (8), in the oxidation annealing, the annealing temperature is 600-650 ℃; the annealing time is 20-25min; the oxygen flow is more than or equal to 5000slm.
Preferably, in the step (3), the step of removing the wraparound coating on the front surface of the silicon wafer comprises the following steps:
(31) Firstly, removing a BSG layer coated around the front surface of the silicon wafer by using an acid solution, wherein the reaction time is 60-120 seconds;
(32) Removing the doped Poly-Si winding coating on the front surface of the silicon wafer by using a first alkaline solution, removing the alkaline solution on the surface of the silicon wafer by using an acidic solution, and then washing with water;
(33) And (3) performing front surface texturing by using a second alkaline solution, removing the alkaline solution on the surface of the silicon wafer by using an acid solution, and then washing by using water.
Due to the application of the technical scheme, compared with the prior art, the invention has the following advantages: according to the preparation method of the P-type IBC battery, provided by the invention, the residual polycrystalline silicon layer is removed by secondary laser ablation and combining a milder wet chemical method, the secondary laser ablation aims to minimize the residual doped polycrystalline silicon layer, the milder wet chemical method can control the corrosion amount of the side wall, the P area broadening is reduced, and the obtained P area and N area patterns are relatively regular, so that the open-circuit voltage and the short-circuit current of the IBC battery are improved, and the efficiency of the IBC battery is finally improved.
Drawings
Fig. 1 is a schematic diagram of a battery structure after the step (1) of the P-type IBC battery preparation method in the embodiment of the present invention;
fig. 2 is a schematic structural diagram of the P-type IBC cell in the embodiment of the present invention after step (2) of the method for manufacturing the P-type IBC cell;
fig. 3 is a schematic diagram of the cell structure after step (3) of the P-type IBC cell preparation method in the embodiment of the present invention;
fig. 4 is a schematic structural diagram of the P-type IBC cell in the embodiment of the present invention after step (4) of the method for manufacturing the P-type IBC cell;
fig. 5 is a schematic structural diagram of the P-type IBC cell in the embodiment of the present invention after step (5) of the method for manufacturing the P-type IBC cell;
fig. 6 is a schematic diagram of the cell structure in step (6) of the P-type IBC cell manufacturing method according to the present invention;
fig. 7 is a schematic battery structure diagram of step (7) of the P-type IBC battery manufacturing method according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of the cell after a back passivation layer is deposited on the back surface of the silicon wafer in the step (8) of the preparation method of the P-type IBC cell in the embodiment of the present invention;
fig. 9 is a schematic structural diagram of a P-type IBC cell in an embodiment of the present invention;
fig. 10 is a schematic diagram of the cell structure (labeled P-type region and N-type region) after step (7) of the P-type IBC cell manufacturing method according to the embodiment of the present invention.
In the above drawings:
1-P type silicon chip; 2-tunneling oxide layer; a 3-phosphorus doped polysilicon layer; 4-BSG layer; 5-front mask layer; 6-first slotting; 7-a back mask layer; 8-second slotting; 9-back passivation layer.
Detailed Description
The invention will be further described with reference to examples of embodiments shown in the drawings.
A preparation method of a P-type IBC battery comprises the following steps:
(1) The method for preprocessing the P-type silicon wafer comprises the following steps: using an alkaline etching polishing solution to perform double-sided polishing on the silicon wafer, wherein the reflectivity of the surface of the silicon wafer is controlled to be 25-50%, and the etching polishing solution is a sodium hydroxide or potassium hydroxide solution with the mass concentration of 5-15%;
(2) Depositing a tunneling oxide layer on the back of the silicon wafer, and depositing a phosphorus-doped amorphous silicon layer on the tunneling oxide layer on the back of the silicon wafer;
depositing a tunneling oxide layer on the back of the silicon chip, wherein the oxide layer can be SiOx and has the thickness of 1-2nm. The tunnel oxide layer may be obtained by chemical oxidation, PECVD, LPCVD or thermal oxidation.
Depositing a layer of phosphorus-doped amorphous silicon layer on the back tunneling oxide layer, wherein the phosphorus-doped amorphous silicon layer can be directly obtained by a PECVD (plasma enhanced chemical vapor deposition) in-situ doping method, or can be directly obtained by an LPCVD (low pressure chemical vapor deposition) in-situ doping method, or an intrinsic amorphous silicon film can be obtained by LPCVD first, and then the phosphorus-doped amorphous silicon layer is obtained by a tube furnace thermal diffusion method, wherein the thickness of the amorphous silicon film is controlled to be 80-300 nm.
In this example, a tunneling oxide layer + phosphorus-doped polysilicon layer is prepared by LPCVD, which comprises a tunneling oxide layer (SiOx) of 1-2nm, a phosphorus-doped amorphous silicon layer (poly-Si (N +) of 80-300nm, and a BSG layer (borosilicate glass) of 40-80 nm from inside to outside, as shown in fig. 2.
(3) Removing the winding coating on the front surface of the silicon wafer, and depositing a front mask layer 5 on the front surface of the silicon wafer, wherein the winding coating on the front surface is treated by a wet chemical method, and the method comprises the following steps:
(31) Removing the BSG layer 4 plated around the front surface of the silicon wafer by using a chain method, wherein an HF solution is selected, the volume ratio concentration of the HF solution is 30-60%, and the reaction time is 60-120 seconds;
(32) Removing the doped Poly-Si winding coating on the front surface in a first groove-type alkaline solution, wherein the first alkaline solution is NaOH or KOH solution, and the mass ratio of the first alkaline solution is 4-6%; the reaction temperature is 60-75 ℃; the reaction time is 250-500 s; then removing residual alkaline solution on the surface of the silicon wafer by using an acidic solution (such as HCl), and then washing by using water.
(33) Firstly, performing front-side texturing by using a second alkaline solution, removing the alkaline solution on the surface of the silicon wafer by using an acid solution, and then washing by using water, wherein the second alkaline solution is a NaOH or KOH solution, the mass concentration of the second alkaline solution is 20-40%, the reaction temperature is 75-85 ℃, the reaction time is 550-650s, and the reflectivity is 8-15%; the pyramid base size is 1um-5um. The acidic solution is HCl solution. The resulting cell structure is shown in fig. 3.
The front mask layer deposited on the front side of the silicon wafer is SiNx, and the film can be used as a mask in the wet chemical treatment process of the back side and also used as a passivation and anti-reflection film on the front side, as shown in fig. 4.
(4) Carrying out first laser grooving on the back of the silicon wafer, and then carrying out acid washing;
grooving the P-shaped area by using a laser ablation method, wherein 6 is a first grooving area as shown in FIG. 5; the BSG and partial doped polycrystalline layer of the P-type region are removed, the laser ablation can only remove about 10-30nm of doped polycrystalline silicon generally, and the doped polycrystalline silicon layer can not be completely removed, so that the side wall of the slotted region is seriously corroded and the width of the slotted region is seriously widened by directly treating the slotted region with alkaline solution under the condition.
In the step, the laser parameters for the first laser grooving are as follows: wavelength 532nm, scanning speed 8000-20000mm/s, frequency 15-25KHz, line width of slot 100-150um, laser power: 2-10 watts; the center distance between the slotted lines is 0.8-1.2mm.
Next, the grooved area is treated with wet chemistry: and (3) cleaning the cell slice subjected to the laser ablation treatment in an acid solution with the volume fraction of 10% to remove impurities on the surface, wherein the acid solution is one or the combination of hydrofluoric acid and hydrochloric acid.
(5) And depositing a back mask layer 7 on the back surface of the silicon wafer, wherein the back mask layer 7 is SiNx, and the thickness of the layer is 70-80nm.
(6) Carrying out secondary laser grooving on the back of the silicon wafer: and (3) carrying out secondary grooving on the original P-type region by using a laser ablation method, as shown in fig. 7, wherein 8 is a secondary grooving region, and removing the back mask layer SiNx and part of doped polysilicon in the P-type region, wherein the thickness of the phosphorus doped polysilicon remained in the P region is less than 50nm. The second trench penetrates the phosphorus doped polysilicon layer.
In the step, the laser parameters for the second laser grooving are as follows: the laser parameters are 532nm in wavelength, 8000-20000mm/s in scanning speed, 15-25KHz in frequency, 85-125um in line width of the slot and 2-10 watts in laser power; the center distance between the slotted lines is 0.8-1.2mm. Compared with the step (4), the center distance of the second time of slotting is unchanged, and the line width of the second time of slotting is reduced by 15-25um compared with that of the first time of slotting.
(7) Cleaning the silicon wafer by adopting cleaning fluid
In one embodiment, the cleaning solution is a mixed solution of hydrogen peroxide and an acid solution, the battery piece after laser ablation treatment is placed in the cleaning solution in the chain type tank, the acid solution is a hydrofluoric acid solution or a mixed solution of hydrofluoric acid and hydrochloric acid, and the reason for using the cleaning solution is described by taking hydrofluoric acid as an example:
1、H 2 O 2 has strong oxidizability, can react with silicon in a groove-opening area, has moderate reaction speed and is convenient to control, firstly H 2 O 2 +Si→SiO 2 +H 2 0, then SiO produced by reaction 2 And reacted with HF to form SiF 4 Dissolved in a solution, thus continuously forming SiO 2 And is dissolved, so that the doped polysilicon remained in the P region is continuously etched by reaction;
2. in the reaction solution, HF reacts with the SiNx mask and BSG on the back surface due to the presence of HF, but BSG and SiNx are thick enough to react with each other in H 2 O 2 BSG and SiNx act to protect the polysilicon film in the N + layer region (i.e., the P-doped polysilicon layer) during reaction with the HF mixed solution, even if H reacts during the reaction due to over-reaction 2 O 2 The mixed solution with HF reacts with the polysilicon in the N region due to the P regionThe remaining polysilicon is limited, therefore, H 2 O 2 The reaction with the HF and the N-region polycrystalline silicon is limited, and the whole passivation effect cannot be influenced;
3. the reaction acts on the polycrystalline silicon, not only in the direction vertical to the surface of the silicon wafer, but also in the direction parallel to the silicon wafer, namely the side wall of the slotting region is etched, but the reaction speed of the cleaning liquid and the silicon wafer is slow, so that the corrosion of the side wall can be slowed down, the corrosion depth of the side wall in the cleaning liquid can be controlled, and the widening of the slotting region can be controlled; meanwhile, the reaction speed is low, and the patterns of the P area and the N area generated by laser ablation are relatively regular.
In the step, the volume ratio of hydrogen peroxide, water and acid liquor in the cleaning solution is (20-40): 100: (40-80), the reaction time is 30-300 seconds, and the reaction temperature is normal temperature.
In another embodiment, the cleaning solution comprises an acid solution and ozone, wherein the acid solution is a hydrofluoric acid solution or a mixed solution of hydrofluoric acid and hydrochloric acid. Wherein the concentration of the ozone is 0.2-0.6mg/L. When the acid solution is hydrofluoric acid, the volume ratio of the solution is as follows: HF: h 2 0＝(1：1)：(3：1)。
The specific implementation mode is as follows: taking hydrofluoric acid as an example, ozone O is introduced into the hydrofluoric acid solution 3 First of all, O 3 +Si→SiO 2 Then SiO produced by the reaction 2 And reacted with HF to form SiF 4 (SiO 2 +HF→SiF4+H 2 O), dissolved in the solution, thus continuously forming SiO 2 And is dissolved again, so that the doped polysilicon remained in the P region is continuously etched by reaction.
Next, after step (7), before step (8), further comprising: and (3) cleaning the cell in an acid solution, wherein the acid solution is one or a combination of more of hydrofluoric acid, nitric acid and hydrochloric acid, and the SiOx, siNx and BSG on the back surface of the silicon wafer can be completely removed after acid cleaning, as shown in FIG. 8.
(8) Sequentially carrying out oxidation annealing, back passivation layer deposition 9 on the back of the silicon wafer, electrode preparation and sintering treatment on the silicon wafer, specifically:
(81) Oxidation annealing
Placing the silicon wafer into a normal pressure oxidation furnace, and annealing at 600-650 ℃ under the normal pressure condition; the annealing time is 20-25min; the oxygen flow is more than or equal to 5000slm.
The function of the step is as follows: the problem of local lattice mismatch caused by two times of laser ablation can be repaired, and stress is released; the damage of laser to the surface of the silicon chip is reduced, and SiOx generated by oxidation can repair unsaturated bonds on the surface of the silicon chip.
(82) Passivating the back of the silicon wafer
Depositing a back passivation layer which is a composite layer of the AlOx layer and the SiNx layer (for example, depositing the AlOx layer first and then depositing the SiNx layer on the AlOx layer or depositing the SiNx layer first and then depositing the AlOx layer on the SiNx layer); performing anti-reflection passivation treatment on the front surface of the silicon wafer, and depositing a front passivation layer, wherein the front passivation layer is a composite layer of an AlOx layer and a SiNx layer (for example, depositing an AlOx layer first and then depositing a SiNx layer on the AlOx layer, or depositing a SiNx layer first and then depositing an AlOx layer on the SiNx layer), as shown in FIG. 9.
(83) Preparation of electrodes
LCO opening is performed in the cell p-type region 6 using laser, the contact hole region is laser opened without the back passivation layer 9, and then an electrode paste layer containing a conductive component is formed over the cell back n + region and p-type region using a screen printing method.
(84) Sintering in a sintering furnace to form good ohmic contact
Referring to fig. 10, 10 is a positive electrode, which is formed by firing aluminum paste or silver-aluminum paste; 11 is a negative electrode and is formed by firing silver paste.
In another embodiment of the invention, a P-type IBC cell prepared by a P-type IBC cell preparation method is provided, which includes a P-type silicon wafer 1, and a tunneling oxide layer 2 and a phosphorus-doped polysilicon layer 3 that are sequentially disposed inward and outward on the back surface of the silicon wafer 1, wherein the tunneling oxide layer 2 and the phosphorus-doped polysilicon layer 3 are provided with slots to form a P-type region (indicated by a in fig. 10) and an N-type region (indicated by b in fig. 10) that are disposed at intervals, and a back passivation layer 9 is disposed on one side of the phosphorus-doped polysilicon layer 3 away from the tunneling oxide layer 2; an anode is arranged in the groove, and a cathode is arranged on the N + area.
The sidewall corrosion broadening of the P-type IBC cell of this example was compared to a prior P-type IBC cell, see table 1:
TABLE 1 side wall erosion broadening data for P-type IBC cells of the present example versus conventional P-type IBC cells
In table 1, the groove width refers to the width of the first groove after the first laser groove (see the width c in fig. 4), and the groove region width after the chemical treatment of the P-type IBC battery prepared by the conventional method refers to the width of the groove after the laser ablation and after the treatment of the alkaline solution; the width of the slotting region after the chemical treatment of the P-type IBC battery prepared by the preparation method is the width of the slotting after the second laser ablation and the treatment of the cleaning solution; broadening refers to the difference between the width of the slot and the width of the slotted region after chemical treatment.
As can be seen from table 1, the width reduction amount of the grooved region of the P-type IBC cell of this example is small, and the broadening value is small, and thus the preparation method of this example can control the broadening.
Compared with the existing P-type IBC battery, the performance of the P-type IBC battery is tested, and the open-circuit voltage of the P-type IBC battery is increased by 2mv-5mv, the short-circuit current is increased by 20mA-50mA, and the overall efficiency is increased by 0.11% -0.26%.
The above embodiments are only for illustrating the technical idea and features of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the content of the present invention and implement the present invention, and not to limit the protection scope of the present invention by this means. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (10)
1. A preparation method of a P-type IBC battery is characterized by comprising the following steps:
(1) Preprocessing a P-type silicon wafer;
(2) Depositing a tunneling oxide layer on the back of the silicon wafer, and depositing a phosphorus-doped amorphous silicon layer on the tunneling oxide layer on the back of the silicon wafer;
(3) Removing the winding coating on the front side of the silicon wafer, and depositing a front side mask layer on the front side of the silicon wafer;
(4) Carrying out first laser grooving on the back of the silicon wafer, and then carrying out acid washing;
(5) Depositing a back mask layer on the back of the silicon wafer;
(6) Performing secondary laser grooving on the back of the silicon wafer;
(7) Cleaning the silicon wafer by adopting a cleaning solution;
(8) And sequentially carrying out oxidation annealing, back passivation layer deposition on the back of the silicon wafer, electrode preparation and sintering treatment on the silicon wafer.
2. The method for manufacturing a P-type IBC cell according to claim 1, wherein in the step (7), the cleaning solution is a mixture of hydrogen peroxide and an acid solution, and the acid solution is a hydrofluoric acid solution or a mixture of hydrofluoric acid and hydrochloric acid.
3. The preparation method of the P-type IBC battery as claimed in claim 2, wherein the volume ratio of the hydrogen peroxide to the water to the acid solution in the cleaning solution is (20-40): 100: (40-80).
4. The method for manufacturing a P-type IBC cell according to claim 1, wherein in the step (7), the cleaning solution contains an acid solution and ozone, and the acid solution is a hydrofluoric acid solution or a mixed solution of hydrofluoric acid and hydrochloric acid.
5. The method for preparing a P-type IBC battery according to claim 4, wherein the concentration of ozone is 0.2-0.6mg/L.
6. The method for preparing the P-type IBC battery according to claim 1, wherein in the step (7), the silicon wafer is cleaned by the cleaning solution for 30-300 seconds, and the reaction temperature is normal temperature.
7. The method for preparing the P-type IBC battery as claimed in claim 1, wherein in the step (4), the first laser grooving is carried out on the back surface of the silicon wafer to form a first grooving; and (6) performing laser grooving at the first grooving position to form a second grooving.
8. The method for preparing the P-type IBC battery according to claim 7, wherein in the step (4), the line width of the slots is 100-150um, and the center-to-center distance between the slot lines is 0.8-1.2mm; in the step (6), the line width of the grooves is 85-125um, and the center distance between the grooves is 0.8-1.2mm.
9. The method for preparing the P-type IBC battery according to claim 1, further comprising the following step (7) and before step (8): and (3) cleaning the cell piece in an acid solution, wherein the acid solution is a hydrofluoric acid solution or a mixed solution of hydrofluoric acid and hydrochloric acid, and the purpose of the step is to remove the SiNx mask layer residual on the back surface.
10. The method for preparing the P-type IBC battery according to claim 1, wherein in the step (8), in the oxidation annealing, the annealing temperature is 600-650 ℃; the annealing time is 20-25min; the oxygen flow is more than or equal to 5000slm.
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