CN115799290A - Light-emitting diode display panel, manufacturing method and display device - Google Patents
Light-emitting diode display panel, manufacturing method and display device Download PDFInfo
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- CN115799290A CN115799290A CN202111055433.3A CN202111055433A CN115799290A CN 115799290 A CN115799290 A CN 115799290A CN 202111055433 A CN202111055433 A CN 202111055433A CN 115799290 A CN115799290 A CN 115799290A
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Abstract
The invention provides a light-emitting diode display panel, a manufacturing method and a display device, wherein the light-emitting diode display panel comprises the following components: a substrate; the LED chips are arranged on the substrate in an m multiplied by n array; the driving circuit is arranged on the substrate, is electrically connected with the plurality of light emitting diode chips and comprises an anode driving sub-circuit and a cathode driving sub-circuit, the anodes of the plurality of light emitting diode chips are respectively connected with the anode driving sub-circuit, and the cathodes of the plurality of light emitting diode chips are respectively connected with the cathode driving sub-circuit. In the invention, the light-emitting diode chip and the driving circuit are directly integrated on the substrate, so that the process flows of bulk transfer, bonding welding and the like after independently manufacturing the light-emitting diode chip and the driving circuit backboard can be reduced, and the yield loss caused by the bulk transfer process is effectively avoided; the process flow is reduced, the loss of material equipment is correspondingly reduced, the production cost is saved, and the production efficiency is improved.
Description
Technical Field
The invention belongs to the field of semiconductor manufacturing, and particularly relates to a light emitting diode display panel, a manufacturing method and a display device.
Background
The current bottlenecks in the Micro-LED display technology industry mainly include chip fabrication, bulk transfer, full color display, etc., wherein the most important technology is bulk transfer, and usually the yield is lost in this link. In the mass transfer technology, the conventional technology for transferring millions of chips at a time is inefficient. At present, the mainstream in the industry is to transfer a large number of chips by utilizing the technologies of static/magnetic force/vacuum adsorption, van der Waals force printing, adhesive force of rubber materials, fluid assembly and the like. The printing technology of the watt-hour meter uses PDMS material as a medium to manufacture a bump, and selective transfer is performed due to the micro viscosity generated by PDMS, but the process smoothness requirement of the material is extremely high, the market selling price includes that the mold opening cost is high, the manufacturing size of a transfer head is limited by the process, the transfer efficiency is limited, and the transfer yield is risky.
Therefore, there is a need for a technical solution that integrates a chip and a circuit directly on a substrate for lighting display without a huge amount of transfer.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a light emitting diode display panel without a huge transfer process, which is used to solve the yield loss problem of Micro-LEDs during the huge transfer process.
To achieve the above and other related objects, the present invention provides the following embodiments.
A manufacturing method of a light emitting diode display panel comprises the following steps:
providing a substrate;
forming a plurality of light emitting diode chips arranged in an m x n array on the substrate, wherein m and n are integers more than or equal to 2;
forming a driving circuit on the substrate, wherein the driving circuit comprises a positive electrode driving sub-circuit and a negative electrode driving sub-circuit; and
and respectively electrically connecting the plurality of light-emitting diode chips with the drive circuit, respectively electrically connecting the anodes of the plurality of light-emitting diode chips with the anode drive sub-circuit, and respectively electrically connecting the cathodes of the plurality of light-emitting diode chips with the cathode drive sub-circuit.
In the manufacturing method of the light-emitting diode display panel, the light-emitting diode chip and the driving circuit are directly integrated and formed on the substrate, so that the process flows of bulk transfer, bonding welding and the like after the light-emitting diode chip and the driving circuit backboard are independently manufactured can be reduced, and the yield loss caused by the bulk transfer process is effectively avoided; the process flow is reduced, so that the loss of material equipment is correspondingly reduced, the production cost is saved, and the production efficiency is improved; the anodes of a plurality of LED chips with array design are respectively electrically connected with the anode drive sub-circuit, the cathodes of a plurality of LED chips with array design are respectively electrically connected with the cathode drive sub-circuit, namely, the LED chips with array design are arranged in parallel, and are driven and lightened simultaneously, and the drive circuit has a simple structure and high drive efficiency.
Optionally, the forming of light emitting diode chips arranged in an m × n array on the substrate includes:
forming an epitaxial layer on the substrate, wherein the epitaxial layer at least comprises an N-type layer and a P-type layer;
etching the epitaxial layer to form a plurality of epitaxial units which are arranged in an m multiplied by n array and are mutually independent;
forming an insulating layer covering the epitaxial cells;
and etching the insulating layer to form a first insulating part positioned at the top of the epitaxial unit, a second insulating part positioned at the first side of the epitaxial unit and a third insulating part positioned at the second side of the epitaxial unit, wherein the top of the second insulating part is flushed with the bottom of the N-type layer of the epitaxial unit, and the top of the third insulating part is flushed with the bottom of the P-type layer of the epitaxial unit.
Optionally, the forming an epitaxial layer on the substrate includes:
and sequentially laminating a sacrificial layer, the N-type layer, the multi-quantum well layer and the P-type layer on the substrate.
Optionally, the etching the insulating layer includes:
coating a first light resistor on the insulating layer, exposing the first light resistor, wherein the exposed first light resistor only covers the insulating layer at the top of the epitaxial unit and the insulating layer at the second side of the epitaxial unit;
etching by taking the exposed first photoresist as a mask, removing the exposed insulating layer, reserving part of the insulating layer only on the first side of the epitaxial unit, and enabling the top of the part of the insulating layer reserved on the first side of the epitaxial unit to be flush with the bottom of an N-type layer in the epitaxial unit to obtain a second insulating part;
removing the residual first photoresist, coating a second photoresist on the insulating layer, exposing the second photoresist, wherein the exposed second photoresist only covers the insulating layer at the top of the epitaxial unit and the second insulating part;
etching by taking the exposed second photoresist as a mask, removing the exposed insulating layer, reserving part of the insulating layer only on the second side of the epitaxial unit, and making the top of the part of the insulating layer reserved on the second side of the epitaxial unit flush with the bottom of a P-type layer in the epitaxial unit to obtain a third insulating part;
and removing the residual second photoresist, and reserving the insulating layer at the top of the epitaxial unit to obtain the first insulating part.
Optionally, the forming a driving circuit on the substrate includes:
forming a negative electrode driving sub-circuit on the substrate, wherein the negative electrode driving sub-circuit comprises a negative electrode power-on region and n negative electrode circuit regions, the n negative electrode circuit regions are respectively and electrically connected with the negative electrode power-on region, the n negative electrode circuit regions are arranged at intervals along a first direction, and the n negative electrode circuit regions are respectively in one-to-one correspondence with and adjacent to second insulating parts of the n rows of light-emitting diode chips;
forming a positive electrode drive sub-circuit on the substrate, wherein the positive electrode drive sub-circuit comprises a positive electrode power-on area and n positive electrode circuit areas, the n positive electrode circuit areas are respectively and electrically connected with the positive electrode power-on area, the n positive electrode circuit areas are arranged at intervals along a first direction, and the n positive electrode circuit areas are respectively in one-to-one correspondence with and adjacent to third insulation parts of the n columns of light-emitting diode chips;
the n negative electrode circuit areas and the n positive electrode circuit areas are mutually staggered in the first direction and are arranged in a cross tooth shape.
Optionally, the electrically connecting the plurality of light emitting diode chips with the driving circuit respectively includes:
forming a negative electrode on the second insulating part of the light-emitting diode chip and the negative circuit area, wherein the negative electrode electrically connects the N-type layer of the epitaxial unit with the negative circuit area, and the negative electrode of the light-emitting diode chip is electrically led out from the N-type layer of the epitaxial unit;
and forming a positive electrode on the third insulating part of the light-emitting diode chip and the positive circuit area, wherein the positive electrode electrically connects the P-type layer of the epitaxial unit with the positive circuit area, and the positive electrode of the light-emitting diode chip is electrically led out from the P-type layer of the epitaxial unit.
A light emitting diode display panel comprising:
a substrate;
the LED chips are arranged on the substrate in an m x n array, and m and n are integers more than or equal to 2; and
and the driving circuit is arranged on the substrate, is electrically connected with the plurality of light-emitting diode chips, and comprises an anode driving sub-circuit and a cathode driving sub-circuit, the anodes of the plurality of light-emitting diode chips are respectively and electrically connected with the anode driving sub-circuit, and the cathodes of the plurality of light-emitting diode chips are respectively and electrically connected with the cathode driving sub-circuit.
In the light-emitting diode display panel, the light-emitting diode chip and the driving circuit are directly integrated on the substrate, so that the process flows of bulk transfer, bonding welding and the like after independently manufacturing the light-emitting diode chip and the driving circuit backboard can be reduced, and the yield loss caused by the bulk transfer process is effectively avoided; the process flow is reduced, so that the loss of material equipment is correspondingly reduced, the production cost is saved, and the production efficiency is improved; the anodes of a plurality of LED chips with array design are respectively electrically connected with the anode drive sub-circuit, the cathodes of a plurality of LED chips with array design are respectively electrically connected with the cathode drive sub-circuit, namely, the LED chips with array design are arranged in parallel, and are driven and lightened simultaneously, and the drive circuit has a simple structure and high drive efficiency.
Optionally, the light emitting diode chip includes an epitaxial unit, a first insulating portion located at the top of the epitaxial unit, a second insulating portion located at the first side of the epitaxial unit, and a third insulating portion located at the second side of the epitaxial unit, where the epitaxial unit at least includes an N-type layer and a P-type layer, the top of the second insulating portion is flush with the bottom of the N-type layer of the epitaxial unit, the N-type layer of the epitaxial unit leads out a negative electrode of the light emitting diode chip, the top of the third insulating portion is flush with the bottom of the P-type layer of the epitaxial unit, and the P-type layer of the epitaxial unit leads out an positive electrode of the light emitting diode chip.
Optionally, the positive electrode driving sub-circuit includes a positive electrode power-on region and n positive electrode circuit regions, the n positive electrode circuit regions are arranged at intervals along a first direction, and the n positive electrode circuit regions are respectively electrically connected to the positive electrode power-on region, the positive electrode of the ith row of light emitting diode chips is electrically connected to the ith positive electrode circuit region, and i is an integer from 1 to n; the negative electrode driving sub-circuit comprises a negative electrode power-on area and n negative electrode circuit areas, wherein the n negative electrode circuit areas are arranged at intervals along the first direction, the n negative electrode circuit areas and the n positive electrode circuit areas are staggered in the first direction, the n negative electrode circuit areas are respectively and electrically connected with the negative electrode power-on area, the negative electrodes of the light emitting diode chips in the ith row are electrically connected with the ith negative electrode circuit areas, and i is an integer from 1 to n.
A display device comprising the light emitting diode display panel of any one of the above.
In the display device, the light-emitting diode chip and the driving circuit are directly integrated on the substrate, so that the process flows of huge transfer, bonding welding and the like after independently manufacturing the light-emitting diode chip and the driving circuit backboard can be reduced, and the yield loss caused by a huge transfer process is effectively avoided; the process flow is reduced, the production cost is saved, and the production efficiency is improved; a plurality of LED chips that are the array design set up in parallel, and the drive is lighted simultaneously, and drive circuit simple structure, drive efficiency is high.
Drawings
Fig. 1-2 are schematic structural diagrams of an led display panel according to an embodiment of the invention.
FIG. 3 is a schematic diagram of a manufacturing method of an LED display panel according to the present invention.
Fig. 4-19 are process flow diagrams of a method for manufacturing the led display panel of fig. 1.
Description of the reference numerals
1-substrate, 2-epitaxial layer, 21-sacrificial layer, 22-N type layer, 23-multiple quantum well layer, 24-P type layer, 2 '-epitaxial unit, 2' -light emitting diode chip, 3-insulating layer, 31-first insulating portion, 32-second insulating portion, 33-third insulating portion, 4-first photoresist, 5-second photoresist, 6-driving circuit, 61-negative driving sub-circuit, 62-positive driving sub-circuit, 611-negative electrode conducting region, 612-negative electrode circuit region, 621-positive electrode conducting region, 622-positive electrode circuit region, 71-negative electrode, 72-positive electrode.
Detailed Description
As described in the foregoing background, the inventors have studied to find that: in the existing Micro-LED process, the efficiency of mass transfer is low, the process conditions are strict, and yield loss inevitably exists, so that the production efficiency is greatly reduced, and the production cost is increased.
Based on this, the invention provides a manufacturing technical scheme of the light emitting diode display panel, which comprises the following steps: directly integrating and forming a light-emitting diode chip and a driving circuit on a substrate to reduce the process flows of huge transfer, bonding welding and the like after independently manufacturing the light-emitting diode chip and a driving circuit backboard; the driving circuit directly drives a plurality of light emitting diode chips which are designed in an array mode in parallel so as to drive and light simultaneously, and driving efficiency is improved.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 19. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated. The structures, the proportions, the sizes, and the like shown in the drawings attached to the present specification are only used for matching with the disclosure of the present specification, so as to be understood and read by those skilled in the art, and are not used for limiting the conditions under which the present invention can be implemented, so that the present invention has no technical essence, and any modifications of the structures, changes of the proportion relationships, or adjustments of the sizes, can still fall within the scope of the technical contents disclosed by the present invention without affecting the efficacy and the achievable purpose of the present invention.
As shown in fig. 1-2, an embodiment of the invention provides an led display panel, which includes:
a substrate 1;
the LED chip 2 'comprises a plurality of LED chips 2' arranged on the substrate 1 in an m × n array, wherein m and n are integers more than or equal to 2; and
the driving circuit 6 is disposed on the substrate 1, and electrically connected to the plurality of led chips 2", and includes an anode driving sub-circuit 62 and a cathode driving sub-circuit 61, wherein anodes of the plurality of led chips 2" are electrically connected to the anode driving sub-circuit 62, and cathodes of the plurality of led chips 2 "are electrically connected to the cathode driving sub-circuit 61.
The substrate 1 may be a non-conductive substrate such as sapphire or glass, or a semiconductor substrate such as gallium arsenide or gallium nitride, but is not limited thereto.
It should be understood that the led chip 2 ″ is not limited to the 3 × 5 array design shown in fig. 1, and in other alternative embodiments of the present invention, it may also be designed in other m × n array structures such as 2 × 2, 2 × 3, 3 × 4, etc., where m and n are integers greater than or equal to 2.
In detail, as shown in fig. 2, the light emitting diode chip 2 ″ includes an epitaxial cell 2', a first insulating portion 31 located at the top of the epitaxial cell 2', a second insulating portion 32 located at the first side of the epitaxial cell 2', and a third insulating portion 33 located at the second side of the epitaxial cell 2', the epitaxial cell 2' includes at least an N-type layer 22 and a P-type layer 24, the top of the second insulating portion 32 is flush with the bottom of the N-type layer 22 of the epitaxial cell 2', the N-type layer of the epitaxial cell 2' leads out the negative electrode of the light emitting diode chip 2 ″, the top of the third insulating portion 33 is flush with the bottom of the P-type layer 24 of the epitaxial cell 2', and the P-type layer 24 of the epitaxial cell 2' leads out the positive electrode of the light emitting diode chip 2 ″.
In detail, as shown in fig. 1-2, the positive electrode driving sub-circuit 62 includes a positive electrode conducting area 621 and n positive electrode circuit areas 622, the n positive electrode circuit areas 622 are disposed at intervals along a first direction (horizontal direction), the n positive electrode circuit areas 622 are electrically connected to the positive electrode conducting area 621 respectively, the positive electrode of the ith row of light emitting diode chips 2 "is electrically connected to the ith positive electrode circuit area 622 through the positive electrode 72, and i is an integer from 1 to n; the negative driving sub-circuit 61 comprises a negative electrode power-on region 611 and n negative electrode circuit regions 612, the n negative electrode circuit regions 612 are arranged at intervals along a first direction, the n negative electrode circuit regions 612 and the n positive electrode circuit regions 622 are staggered in the first direction, the n negative electrode circuit regions 612 are respectively electrically connected with the negative electrode power-on region 611, the negative electrodes of the ith row of light-emitting diode chips 2 "are electrically connected with the ith negative electrode circuit region 612 through the negative electrodes 71, and i is an integer from 1 to n.
Thus, as shown in fig. 1-2, the led chip 2 ″ and the driving circuit 6 are directly integrated on the substrate 1, which reduces the processes of bulk transfer, bonding and welding after independently manufacturing the led chip and the driving circuit backplane, and avoids yield loss caused by the bulk transfer process; the process flow is reduced, so that the loss of material equipment is correspondingly reduced, the production cost is saved, and the production efficiency is improved; the anodes of the light emitting diode chips 2' in array design are respectively electrically connected with the anode driving sub-circuit 62, and the cathodes of the light emitting diode chips 2' in array design are respectively electrically connected with the cathode driving sub-circuit 61, i.e. the light emitting diode chips 2' in m × n array design are arranged in parallel, and are driven and lightened simultaneously, the driving circuit has simple structure and high driving efficiency.
Meanwhile, the invention also provides a display device which comprises the LED display panel, and the LED display panel is based on the structural design that the LED chip 2 and the drive circuit 6 are directly integrated and formed on the substrate 1, so that the process flow is saved, the production efficiency is improved, the product yield is improved, and the drive circuit has a simple structure and high drive efficiency.
In addition, the present invention further provides a method for manufacturing a light emitting diode display panel, which is used for manufacturing the light emitting diode display panel, as shown in fig. 3, and includes the steps of:
s1, providing a substrate 1;
s2, forming a plurality of light emitting diode chips 2 arranged in an m x n array on the substrate 1, wherein m and n are integers more than or equal to 2;
s3, forming a driving circuit 6 on the substrate 1, wherein the driving circuit 6 comprises a positive electrode driving sub-circuit 62 and a negative electrode driving sub-circuit 61; and
and S4, electrically connecting the plurality of light-emitting diode chips 2' with the driving circuit 6 respectively, wherein the anodes of the plurality of light-emitting diode chips 2' are electrically connected with the anode driving sub-circuit 62 respectively, and the cathodes of the plurality of light-emitting diode chips 2' are electrically connected with the cathode driving sub-circuit 61 respectively.
In detail, in step S1, the substrate 1 may be a non-conductive substrate such as sapphire or glass, or a semiconductor substrate such as gallium arsenide or gallium nitride, which is not limited herein.
In detail, as shown in fig. 4 to 13, the step S2 of forming a plurality of light emitting diode chips 2 ″ arranged in an m × n array on the substrate 1 further includes:
s21, as shown in fig. 4, forming an epitaxial layer 2 on the substrate 1, where the epitaxial layer 2 at least includes an N-type layer 22 and a P-type layer 24;
s22, as shown in fig. 5 to fig. 6, etching the epitaxial layer 2 to form a plurality of epitaxial cells 2' arranged in an m × n array and independent from each other;
s23, as shown in fig. 7, forming an insulating layer 3 covering the epitaxial cells 2';
s24, as shown in fig. 8 to fig. 13, the insulating layer 3 is etched to form a first insulating portion 31 located at the top of the epitaxial cell 2', a second insulating portion 32 located at the first side of the epitaxial cell 2', and a third insulating portion 33 located at the second side of the epitaxial cell 2', wherein the top of the second insulating portion 32 is flush with the bottom of the N-type layer of the epitaxial cell 2', and the top of the third insulating portion 33 is flush with the bottom of the P-type layer of the epitaxial cell 2'.
In more detail, as shown in fig. 4, the step S21 of forming the epitaxial layer 2 on the substrate 1 further includes:
a sacrificial layer 21, an N-type layer 22, a multi-quantum well layer 23, and a P-type layer 24 are sequentially stacked on the substrate 1.
Optionally, in an optional embodiment of the present invention, the sacrificial layer 231 employs U-type gallium nitride, the N-type layer 22 employs N-type gallium nitride, and the P-type layer 24 employs P-type gallium nitride; the N-type layer 22 and the P-type layer 24 form a PN junction, electrons in the PN junction collide with holes after the PN junction is electrified, photons are excited, and therefore light is emitted, and the multi-quantum well layer 23 is mainly used for improving the recombination efficiency of the electrons and the holes.
In more detail, in step S22, as shown in fig. 5-6, platform etching (MESA) is performed by using a mask (mask), the epitaxial layer 2 is etched, a partial region of the epitaxial layer 2 is removed, the etching is stopped on the substrate 1, and a plurality of epitaxial cells 2' arranged in a 3x 5 array and independent of each other are formed on the substrate 1. It should be understood that the epitaxial cell 2' is not limited to the 3 × 5 array design shown in fig. 1, and in other alternative embodiments of the present invention, the epitaxial cell may have other m × n array structure designs such as 2 × 2, 2 × 3, 3 × 4, etc., where m and n are integers greater than or equal to 2.
In more detail, in step S23, as shown in fig. 7, an insulating layer 3 is formed by using a chemical vapor deposition process, and the insulating layer 3 at least covers the epitaxial cells 2', and the epitaxial cells 2' are isolated and protected by the insulating layer 3. The insulating layer 3 may be made of an insulating material such as silicon oxide.
In more detail, as shown in fig. 8 to 13, the step S24 of etching the insulating layer 3 further includes:
s241, as shown in fig. 8, coating the first photoresist 4 on the insulating layer 3, and exposing the first photoresist 4, wherein the exposed and developed first photoresist 4 only covers the insulating layer 3 on the top of the epitaxial cell 2 'and the insulating layer 3 on the second side of the epitaxial cell 2';
s242, as shown in fig. 9, using the exposed first photoresist 4 as a mask, performing etching to remove the exposed insulating layer 3, leaving only a portion of the insulating layer 2' on the first side of the epitaxial unit 2', and making the top of the portion of the insulating layer 2' left on the first side of the epitaxial unit 2' flush with the bottom of the N-type layer 22 in the epitaxial unit 2', so as to obtain a second insulating portion 32;
s243, as shown in fig. 10, removing the residual first photoresist 4, coating the second photoresist 5 on the insulating layer 3, and exposing the second photoresist 5, wherein the exposed second photoresist 5 only covers the insulating layer 3 and the second insulating portion 32 on the top of the epitaxial cell 2';
s244, as shown in fig. 11, using the exposed second photoresist 5 as a mask, performing etching to remove the exposed insulating layer 3, leaving only a portion of the insulating layer 3 on the second side of the epitaxial cell 2', and making the top of the portion of the insulating layer 3 on the second side of the epitaxial cell 2' flush with the bottom of the P-type layer 24 in the epitaxial cell 2', so as to obtain a third insulating portion 33;
s245, as shown in fig. 12-13, the residual second photoresist 5 is removed, and the insulating layer 3 on the top of the epitaxial cell 2' is remained, so as to obtain the first insulating portion 31.
As shown in fig. 12-13, the light emitting diode chip 2 ″ is obtained, which includes the epitaxial cell 2', the first insulating portion 31 located at the top of the epitaxial cell 2', the second insulating portion 32 located at the first side of the epitaxial cell 2', and the third insulating portion 33 located at the second side of the epitaxial cell 2', wherein the top of the second insulating portion 32 is flush with the bottom of the N-type layer 22 of the epitaxial cell 2', the second insulating portion 32 just covers the wrapped sacrificial layer 21, the N-type layer 22 leaks, the N-type layer 22 of the epitaxial cell 2' leads out the negative electrode of the light emitting diode chip 2 ″, the top of the third insulating portion 33 is flush with the bottom of the P-type layer 24 of the epitaxial cell 2', the third insulating portion 33 just covers the wrapped sacrificial layer 21, the N-type layer 22, and the multiple quantum layer 23, the P-type layer 24 leaks out, and the P-type layer 24 of the epitaxial cell 2' leads out the positive electrode of the light emitting diode chip 2 ″.
In detail, as shown in fig. 14 to 16, the step S3 of forming the driving circuit 6 on the substrate 1 further includes:
s31, as shown in fig. 14 to fig. 15, forming a negative electrode driving sub-circuit 61 on the substrate 1 by yellow light and vapor deposition processes, where the negative electrode driving sub-circuit 61 includes a negative electrode conducting area 611 and n negative electrode circuit areas 612, the n negative electrode circuit areas 612 are respectively electrically connected to the negative electrode conducting area 611, the n negative electrode circuit areas 612 are arranged at intervals along a first direction, and the n negative electrode circuit areas 612 are respectively arranged in one-to-one correspondence with and adjacent to the second insulating portions 32 of the n rows of light emitting diode chips 2 ″;
s32, as shown in fig. 14 or fig. 16, forming a positive electrode driving sub-circuit 62 on the substrate 1 by yellow light and vapor deposition processes, where the positive electrode driving sub-circuit 62 includes a positive electrode conducting area 621 and n positive electrode circuit areas 622, the n positive electrode circuit areas 622 are respectively electrically connected to the positive electrode conducting area 621, the n positive electrode circuit areas 622 are arranged at intervals along the first direction, and the n positive electrode circuit areas 622 are respectively arranged in one-to-one correspondence and adjacent to the third insulating portions 33 of the n columns of light emitting diode chips 2 ″.
The negative electrode driving sub-circuit 61 and the positive electrode driving sub-circuit 62 may be made of a conductive metal (such as titanium, molybdenum, tungsten) with a high melting point or a metal alloy material, and are mainly used for the subsequent power driving of the light emitting diode chip 2 ″.
In more detail, as shown in fig. 14 or fig. 16, the n negative electrode circuit regions 612 and the n positive electrode circuit regions 622 are staggered from each other in the first direction, and are arranged in a staggered tooth shape, that is, the negative electrode driving sub-circuit 61 and the positive electrode driving sub-circuit 62 are designed in a two-staggered comb-tooth structure; in an alternative embodiment of the present invention, the dimensions of the negative circuit area 612 and the positive circuit area 622 in the first direction are 3 ± 0.5 μm.
In detail, as shown in fig. 17 to 19, the step S4 of electrically connecting the plurality of light emitting diode chips 2 ″ with the driving circuit 6, respectively, further includes:
s41, forming a negative electrode 71 on the second insulating portion 32 and the negative line region 612 of the light emitting diode chip 2", the negative electrode 71 electrically connecting the N-type layer 22 of the epitaxial unit 2 'and the negative line region 612, and electrically drawing the negative electrode of the light emitting diode chip 2" from the N-type layer 22 of the epitaxial unit 2';
s42, the positive electrode 72 is formed on the third insulating portion 33 and the positive wiring region 622 of the light emitting diode chip 2", the positive electrode 72 electrically connects the P-type layer 24 of the epitaxial cell 2 'and the positive wiring region 622, and the positive electrode of the light emitting diode chip 2" is electrically led out from the P-type layer 24 of the epitaxial cell 2'.
The negative electrode 71 and the positive electrode 72 can be made of good conductive metal materials (such as gold) and used for electrode electrical leading-out connection; the cathode electrode 71 and the anode electrode 72 can be prepared by a process group of depositing and etching, one end of the prepared cathode electrode 71 is in ohmic contact with the N-type layer 22 of the epitaxial unit 2', the other end of the prepared cathode electrode 71 is in ohmic contact with the cathode circuit area 612, one end of the prepared anode electrode 72 is in ohmic contact with the P-type layer 24 of the epitaxial unit 2', and the other end of the prepared anode electrode 72 is in ohmic contact with the anode circuit area 622; the thickness of the cathode electrode 71 is slightly smaller than that of the N-type layer 22 in the epitaxial unit 2', and the thickness of the anode electrode 72 is slightly smaller than that of the P-type layer 24 in the epitaxial unit 2'.
It should be noted that, the above description of the process of the led display panel omits many detailed descriptions of photolithography, etching, evaporation, deposition, etc., which are well known to those skilled in the art and will not be described herein.
In summary, in the led display panel, the method for manufacturing the led display panel, and the display device provided by the present invention, the led chip and the driving circuit are directly integrated on the substrate, so that the process flows of bulk transfer, bonding and welding after independently manufacturing the led chip and the driving circuit backplane can be reduced, and the yield loss caused by the bulk transfer process is effectively avoided; the process flow is reduced, so that the loss of material equipment is correspondingly reduced, the production cost is saved, and the production efficiency is improved; the anodes of a plurality of LED chips with array design are respectively electrically connected with the anode drive sub-circuit, the cathodes of a plurality of LED chips with array design are respectively electrically connected with the cathode drive sub-circuit, namely, the LED chips with array design are arranged in parallel, and are driven and lightened simultaneously, and the drive circuit has a simple structure and high drive efficiency.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (10)
1. A method for manufacturing a light emitting diode display panel is characterized by comprising the following steps:
providing a substrate;
forming a plurality of light emitting diode chips arranged in an m x n array on the substrate, wherein m and n are integers more than or equal to 2;
forming a driving circuit on the substrate, wherein the driving circuit comprises a positive electrode driving sub-circuit and a negative electrode driving sub-circuit; and
and respectively electrically connecting the plurality of light-emitting diode chips with the drive circuit, respectively electrically connecting the anodes of the plurality of light-emitting diode chips with the anode drive sub-circuit, and respectively electrically connecting the cathodes of the plurality of light-emitting diode chips with the cathode drive sub-circuit.
2. The method of claim 1, wherein forming the led chips in an m x n array on the substrate comprises:
forming an epitaxial layer on the substrate, wherein the epitaxial layer at least comprises an N-type layer and a P-type layer;
etching the epitaxial layer to form a plurality of independent epitaxial units arranged in an m × n array;
forming an insulating layer covering the epitaxial cells;
and etching the insulating layer to form a first insulating part positioned at the top of the epitaxial unit, a second insulating part positioned at the first side of the epitaxial unit and a third insulating part positioned at the second side of the epitaxial unit, wherein the top of the second insulating part is flushed with the bottom of the N-type layer of the epitaxial unit, and the top of the third insulating part is flushed with the bottom of the P-type layer of the epitaxial unit.
3. The method according to claim 2, wherein the forming an epitaxial layer on the substrate comprises:
and sequentially laminating a sacrificial layer, the N-type layer, the multi-quantum well layer and the P-type layer on the substrate.
4. The method of claim 3, wherein the etching the insulating layer comprises:
coating a first light resistor on the insulating layer, exposing the first light resistor, wherein the exposed first light resistor only covers the insulating layer at the top of the epitaxial unit and the insulating layer at the second side of the epitaxial unit;
etching by taking the exposed first photoresist as a mask, removing the exposed insulating layer, reserving part of the insulating layer only on the first side of the epitaxial unit, and enabling the top of the part of the insulating layer reserved on the first side of the epitaxial unit to be flush with the bottom of an N-type layer in the epitaxial unit to obtain a second insulating part;
removing the residual first photoresist, coating a second photoresist on the insulating layer, exposing the second photoresist, and only covering the insulating layer at the top of the epitaxial unit and the second insulating part by the exposed second photoresist;
etching by taking the exposed second photoresist as a mask, removing the exposed insulating layer, and only reserving part of the insulating layer on the second side of the epitaxial unit, wherein the top of the part of the insulating layer reserved on the second side of the epitaxial unit is flush with the bottom of a P-type layer in the epitaxial unit, so as to obtain a third insulating part;
and removing the residual second photoresist, and reserving the insulating layer at the top of the epitaxial unit to obtain the first insulating part.
5. The method of claim 4, wherein forming a driving circuit on the substrate comprises:
forming a negative electrode driving sub-circuit on the substrate, wherein the negative electrode driving sub-circuit comprises a negative electrode power-on region and n negative electrode circuit regions, the n negative electrode circuit regions are respectively and electrically connected with the negative electrode power-on region, the n negative electrode circuit regions are arranged at intervals along a first direction, and the n negative electrode circuit regions are respectively in one-to-one correspondence with and adjacent to second insulating parts of the n rows of light-emitting diode chips;
forming an anode driving sub-circuit on the substrate, wherein the anode driving sub-circuit comprises an anode power-on area and n anode circuit areas, the n anode circuit areas are respectively electrically connected with the anode power-on area, the n anode circuit areas are arranged at intervals along a first direction, and the n anode circuit areas are respectively in one-to-one correspondence with and adjacent to third insulating parts of the n rows of light-emitting diode chips;
the n negative electrode circuit areas and the n positive electrode circuit areas are mutually staggered in the first direction and are arranged in a cross tooth shape.
6. The method of claim 5, wherein the electrically connecting the plurality of LED chips to the driving circuit respectively comprises:
forming a negative electrode on the second insulating part of the light emitting diode chip and the negative circuit area, wherein the negative electrode electrically connects the N-type layer of the epitaxial unit with the negative circuit area, and the negative electrode of the light emitting diode chip is electrically led out from the N-type layer of the epitaxial unit;
and forming a positive electrode on the third insulating part of the light-emitting diode chip and the positive circuit area, wherein the positive electrode electrically connects the P-type layer of the epitaxial cell with the positive circuit area, and the positive electrode of the light-emitting diode chip is electrically led out from the P-type layer of the epitaxial cell.
7. A light emitting diode display panel, comprising:
a substrate;
the LED chips are arranged on the substrate in an m x n array, and m and n are integers more than or equal to 2; and
the driving circuit is arranged on the substrate, is electrically connected with the plurality of light emitting diode chips and comprises an anode driving sub-circuit and a cathode driving sub-circuit, the anodes of the plurality of light emitting diode chips are respectively and electrically connected with the anode driving sub-circuit, and the cathodes of the plurality of light emitting diode chips are respectively and electrically connected with the cathode driving sub-circuit.
8. The LED display panel of claim 7, wherein the LED chip comprises an epitaxial cell, a first insulating portion at the top of the epitaxial cell, a second insulating portion at the first side of the epitaxial cell, and a third insulating portion at the second side of the epitaxial cell, the epitaxial cell at least comprises an N-type layer and a P-type layer, the top of the second insulating portion is flush with the bottom of the N-type layer of the epitaxial cell, the N-type layer of the epitaxial cell leads out the cathode of the LED chip, the top of the third insulating portion is flush with the bottom of the P-type layer of the epitaxial cell, and the P-type layer of the epitaxial cell leads out the anode of the LED chip.
9. The led display panel of claim 8, wherein the positive driving sub-circuit comprises a positive power-on region and n positive circuit regions, the n positive circuit regions are spaced apart from each other along a first direction, the n positive circuit regions are electrically connected to the positive power-on region, respectively, the positive electrodes of the led chips in the ith row are electrically connected to the ith positive circuit region, i is an integer from 1 to n; the negative electrode driving sub-circuit comprises a negative electrode power-on area and n negative electrode circuit areas, wherein the n negative electrode circuit areas are arranged at intervals along the first direction, the n negative electrode circuit areas and the n positive electrode circuit areas are staggered in the first direction, the n negative electrode circuit areas are respectively electrically connected with the negative electrode power-on area, the negative electrodes of the light emitting diode chips in the ith row are electrically connected with the negative electrode circuit areas, and i is an integer from 1 to n.
10. A display device comprising the light emitting diode display panel according to any one of claims 7 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202111055433.3A CN115799290A (en) | 2021-09-09 | 2021-09-09 | Light-emitting diode display panel, manufacturing method and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111055433.3A CN115799290A (en) | 2021-09-09 | 2021-09-09 | Light-emitting diode display panel, manufacturing method and display device |
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| CN202111055433.3A Pending CN115799290A (en) | 2021-09-09 | 2021-09-09 | Light-emitting diode display panel, manufacturing method and display device |
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