CN104538523A - Semiconductor device for improving current expanding - Google Patents
Semiconductor device for improving current expanding Download PDFInfo
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- CN104538523A CN104538523A CN201510012923.3A CN201510012923A CN104538523A CN 104538523 A CN104538523 A CN 104538523A CN 201510012923 A CN201510012923 A CN 201510012923A CN 104538523 A CN104538523 A CN 104538523A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
Abstract
The invention discloses a semiconductor device for improving current expanding. The semiconductor device comprises a substrate, a current expanding layer and an epitaxial layer, wherein the current expanding layer and the epitaxial layer are formed on the substrate. The current expanding layer is made of a conducting material which is different from the semiconductor material of which the epitaxial layer is made. The electrical conductivity of the conducting material is higher than that of the epitaxial layer material, and therefore the distance of current expanding is bigger. The semiconductor device of larger size and power can be obtained, it is not needed to adopt extra electrode lengthening or multi-electrode parallel connection used for current expanding. In this way, current expanding is improved, and uniformity, power and efficiency of devices are improved.
Description
Technical field
The invention belongs to technical field of semiconductor device, particularly relate to a kind of semiconductor device improving current expansion.
Background technology
Existing semiconductor device adopts heteroepitaxy more and more, especially adopts the substrate of insulation or high resistant, device architecture many employings formal dress that these backing materials grow or inverted structure.Because electrode is on one side same, the expansion of electric current particularly needs to be completed by the semi-conducting material by this polar layer near the current expansion of the polar layer of substrate.In some devices, by the impact of semi-conducting material doping characteristic, the distance that the current expansion of this layer can be expanded is limited, when the powerful device of manufacture large area, need special design current expansion electrode, as interdigited electrode, take chip real estate, and current expansion uniformity affects by design larger.Such as, growing GaN base LED component on a sapphire substrate, the formal dress generally adopted at present or inverted structure chip, its n-electrode contact need is etched away active layer, take larger area, and by the restriction that chip and extraneous second-level interconnect require, its electrode position is limited to, expansion effect can not reach optimum.
And for example, in growing GaN base LED component on sapphire or SiC substrate, adopt inverted structure time, affect by interconnection, its p pad width and p-n electrode spacing less.As in the DA chip (reference publication number is the United States Patent (USP) of US20130141920) of Cree, be confined to the requirement of current expansion, the n-electrode of chip adopts multiple discrete rounded contact region, being together in parallel, forming rectangular p pole and n pole welding disking area on surface by connecting up again.N-GaN one end current expansion requires that the circular ohmic contact in each discrete n district is evenly distributed on whole chip area as far as possible, connect up again, require that the n pad on surface can directly be connected with each discrete n-contact region is vertical, thus make n welding disking area area comparatively large, thus make the spacing between p welding disking area and p-n pad less.Less than normal and the p-n solder pad space length of P pad width is less than normal, by substantially increasing the requirements such as alignment precision that follow-up chip welds with substrate, will increase technology difficulty, reduction yield.And for example, the patents such as CN 201310443689.0 propose the scheme growing the first type current extending, the first type limiting layer, active layer, Second-Type limiting layer and Second-Type current extending on substrate layer successively, but unless the current extending thickness formed is very large, otherwise conductive capability is still very limited, but thickness is too large, can cause again occurring the problems such as device performance decline, high cost.For GaN base LED, even if n-GaN thickness reaches 4 μm, its surface resistance is also up to about 12 Ω/ (Solid-State Electronics, 2002,46 (8), 1235-1239), cause the chip for being greater than 14mil, if do not adopt interdigitated n-electrode or multiple n-electrode, due to current concentrated, voltage will increase and affect light efficiency.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor device improving current expansion, to overcome deficiency of the prior art.
For achieving the above object, the invention provides following technical scheme:
The embodiment of the invention discloses a kind of semiconductor device improving current expansion, the current extending comprising substrate and be formed on described substrate and epitaxial loayer, the material of described current extending is electric conducting material, and the conductivity of this electric conducting material is greater than the conductivity of described epitaxial film materials.
Preferably, in the semiconductor device of above-mentioned improvement current expansion, described electric conducting material comprises metal or nonmetallic materials, and described metal is the high-melting-point such as tungsten or tungsten alloy high-conductive metal, and described nonmetallic materials comprise the high temperature resistant high conductive material such as Graphene or carbon nano-tube.
Preferably, in the semiconductor device of above-mentioned improvement current expansion, described current extending is patterned conductive layer, and this graphics package draws together cellular grid.
Wherein, employing patterned conductive layer can while guarantee current expansion, and the extension mechanism on exposed substrate region can not change; Conductive layer overlay area is because growth selection simultaneously, and realize epitaxial crystal by horizontal extension and cover, its defect concentration can reduce.
In the semiconductor device of above-mentioned improvement current expansion, prepare current extending over the substrate, then prepare the epitaxial loayer on it by secondary epitaxy method.
Or, in the semiconductor device of above-mentioned improvement current expansion, between described substrate and current extending, be also formed with epitaxial buffer layer.More specifically, described Grown has epitaxial buffer layer, then on epitaxial buffer layer, prepares current extending, then on current extending, prepares epitaxial loayer by secondary epitaxy method.
Preferably, in the semiconductor device of above-mentioned improvement current expansion, described current extending is cellular grid, and its thickness is 10nm ~ 200nm, and live width is 5 ~ 10 μm, and the spacing between adjacent lines is 100 ~ 200 μm.
Preferably, in the semiconductor device of above-mentioned improvement current expansion, described epitaxial loayer comprises the first polar layer, active layer and the second polar layer that are formed successively, and described first polar layer and the second polar layer are electrically connected with the first electrode and the second electrode respectively.
Preferably, in the semiconductor device of above-mentioned improvement current expansion, the material of described first polar layer and the second polar layer is GaN, and described active layer is InGaN/GaN multiple quantum well layer.
Preferably, in the semiconductor device of above-mentioned improvement current expansion, described semiconductor device is inverted structure, its surface is provided with the second electrode lay in electrical contact with the second polar layer, described the second electrode lay regional area is formed with contact hole to the first polar layer direction, this contact hole leads to described first polar layer, the contact electrode of described first polar layer is connected with the first polar layer welding zone metal level on surface by contact hole, insulating barrier is provided with in the middle of the contact electrode of the first polar layer and connected welding zone metal and the second polar layer electrode under it and contact hole sidewall.
Preferred further, the contact hole of the first polar layer only has one and diameter is less than 30um, and the first electrode and the second electrode are symmetrically distributed in described device both sides.
Preferably, in the semiconductor device of above-mentioned improvement current expansion, described substrate is dielectric substrate, and described substrate runs through up and down and has through hole, and the electrode of substrate surface is connected with current extending by through hole.
Compared with prior art, the invention has the advantages that:
(1) improve the length of current expansion, the electric current of the polarity of semiconductor layer near substrate is expanded more equably;
(2) decrease the area that takies of electrode design that large size chip current expansion needs, make chip structure design simultaneously and distribution of electrodes more flexible;
(3) epitaxial growth of patterned conductive layer overlay area is due to horizontal extension, has the advantage that defect reduces.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, the accompanying drawing that the following describes is only some embodiments recorded in the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 a ~ Fig. 1 d is depicted as the Making programme figure of LED component in the embodiment of the present invention 1;
Fig. 2 is the schematic perspective view of tungsten cellular grid in the specific embodiment of the invention 1;
Fig. 3 a is the inversion schematic diagram of Fig. 1 d chips;
Fig. 3 b is the DA of Cree or the cross-sectional view of similar chip;
Fig. 4 a is depicted as the back electrode schematic diagram of embodiment 1 chips;
Fig. 4 b is the DA chip back electrode figure of Cree;
The structural representation of flip-chip in embodiment illustrated in fig. 51 on substrate or substrate;
Figure 6 shows that the structural representation of the LED component in the specific embodiment of the invention 3;
Fig. 7 a is depicted as the floor map of LED component in embodiment 3;
Fig. 7 b is the device plane schematic diagram not inserting current extending as a comparison;
Fig. 8 a and Fig. 8 b is the Making programme figure of LED component in the embodiment of the present invention 4.
Embodiment
The invention provides a kind of device and the manufacture method thereof of improving current expansion, make current expansion more even; Meanwhile, in formal dress or inverted structure device, the distribution of electrode is more flexible, to reduce substrate and the interconnected technological requirement of electrode.Further, be combined in etching through hole on substrate, vertical stratification or rear electrode device can be realized.
Particularly, the embodiment of the invention discloses a kind of semiconductor device improving current expansion, comprise substrate and the current extending be formed at successively on described substrate and epitaxial loayer, the material of described current extending is electric conducting material, and described electric conducting material is not identical with the semi-conducting material forming described epitaxial loayer, the conductivity of this electric conducting material is greater than the conductivity of described epitaxial film materials.
Preferably, in above-mentioned semiconductor device, between current extending and substrate, epitaxial buffer layer or other dielectric layers can be provided with respectively or simultaneously; Current extending is the high conductive materials such as metal, Graphene or oxide transparent electrode.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be described in detail the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not making creative work, all belongs to the scope of protection of the invention.
For GaN base LED component, technology of the present invention is introduced below, but it should be noted that the technology of this case is equally applicable to other semiconductor device.
embodiment 1:
Refer to Fig. 1 a, it is the epitaxial wafer cross-sectional view that the present invention improves the embodiment 1 of current expansion LED.
This device comprises a substrate 101, substrate 101 is provided with tungsten cellular grid 102, tungsten metal layer thickness preferred value is that about 10 nanometers are to 200 nanometers, the live width of tungsten metal about 5 ~ 10 microns, spacing about 100 ~ 300 microns, then growing GaN resilient coating under about 550 degree of temperature conditions, thickness is about 30nm, grow n-GaN layer 103, InGaN/GaN multiple quantum well layer 104 thereon more afterwards, the structures such as p-GaN layer 105.Wherein also AlGaN layer etc. may be inserted with between each layer.Fig. 2 is the schematic perspective view of the tungsten cellular grid 102 that this device is formed on the substrate 101 before epitaxial growth.
Shown in ginseng Fig. 1 b, by photoresist or SiO
2protection dry etching forms p-GaN table top, exposes n-GaN contact hole 206 and dicing lane 207, then prepares p-GaN ohmic contact 208 in p-GaN mesa region.
Shown in ginseng Fig. 1 c, deposit the passivation layer 309 of one deck insulation further at crystal column surface, and local 310 opening on n contact hole 206, dicing lane 207, p-electrode surface.
Shown in ginseng Fig. 1 d, form figure at crystal column surface deposit multilayer metal level 411 by microelectronic technique further, make it form good ohmic contact at n-GaN contact hole, and by region insulation outside passivation layer 310 and contact hole.Also graphical in p-GaN and n-GaN ohmic contact metal layer surface deposition pad metal layer further, form p-GaN pad layer 412 and n-GaN pad layer 413, pad metal layer 412,413 itself can be ubm layer, or comprises bump metal layer simultaneously.
Single flip-chip is formed, as shown in Figure 3 a, by the chip electrode placed face down of Fig. 1 d after the cutting of this wafer.Its back electrode as shown in fig. 4 a.As shown in Figure 5, this flip-chip is directly combined with substrate or substrate by solder metal upside-down mounting mode, in conjunction with time pad metal layer 412 be connected with the wiring 415 on substrate 414 with 413.
The present embodiment by adding current expansion conductive layer in n-GaN epitaxial loayer, and the n-GaN region of this conductive layer and growth on it forms better ohmic contact, substantially increase the current expansion ability of n-GaN one end, even if make the single n-GaN electrode compared with small size also directly by vertical direction, electric current can be imported to current extending, by electronics from current extending to surface p-GaN layer vertically injects, realize being uniformly distributed of electric current, and multiple discrete n contact electrode need not be needed as the DA chip of Cree (to ask comparison diagram 3a and Fig. 3 b.Fig. 3 b is the DA of Cree or the cross-sectional view of similar chip, wherein comprises multiple n contact electrode.Please contrast and consult Fig. 4 a and Fig. 4 b, Fig. 4 b is the DA chip back electrode figure of Cree, can see Cree DA chip electrode small one and large one (top thin be anode, what below was wide is negative electrode), spacing is very narrow, and comparatively speaking the present embodiment chip more easily uses), reduce taking of n-GaN electrode pair active area, n-GaN electrode riding position is also relatively more flexible, thus larger area can be arranged to be used for the surperficial welding zone of p-GaN, and arranges the spacing of p-GaN and n-GaN surface welding zone flexibly.According to calculating, the resistivity of tungsten is 5.5 × 10
-8Ω m, as adopted wide 5um thickness to be the tungsten cellular grid of 200nm, spacing is 250 μm, then its equivalent face resistance is 6.9 Ω/, is better than n-GaN itself, and the expansion effect of its electric current quite or be better than existing interdigited electrode or discrete point electrode.As adopted this kind of current extending, the structure similar compared to Cree DA chip, n-GaN perforate can reduce to original less than 1/16, can increase p-GaN mesa region area about 8%.
Current extending in the present embodiment also can be the transparent conductive materials such as single or multiple lift Graphene.Graphene can be flood or network structure.
embodiment 2:similar to Example 1, its difference is only, after the certain thickness epitaxial loayer of growth, to take out epitaxial wafer, insert this current extending, then carry out epitaxial growth again by deposition or transfer method.
embodiment 3:its epitaxial structure equally as shown in Figure 1a.
As shown in Figure 6, form p-GaN table top by photoetching, etching, expose n-GaN contact hole 507, then prepare p-GaN transparent resistive conductive layer 514 in p-GaN mesa region.
Further, also patterned metal layer 515 and pad metal layer 516 is deposited successively on n-GaN and p-GaN surface.Metal level 515 forms ohmic contact on n-GaN surface, in the assist current expansion of p-GaN surface.
The material of transparent resistive conductive layer is preferably ITO, NiAu etc.; The material of pad metal layer is preferably TiAlTiAu, CrAu etc.
Fig. 7 a is the floor map of this device, and Fig. 7 b is the device plane schematic diagram not inserting current extending as a comparison.Wherein 617 is p-GaN mesa region.Comparison diagram 7a and Fig. 7 b can find out, inserting current extending can improve outside the uniformity of the expansion of n-GaN layer electric current, also without the need to adopting interdigitated electrode structure, thus significantly can save the interdigital shared chip area of electrode for n-GaN current expansion, thus significantly improve light extraction efficiency.For the figure shown in the present embodiment, under same chip size, can increase by the p-GaN footprint of 8%.
embodiment 4:its epitaxial structure is as similar in Fig. 1 a.
As shown in Figure 8 a, its substrate is dielectric substrate, is preferably sapphire.Etching after substrate thinning is formed through hole 818, and through hole arrives or passes the current extending inserted.
In through hole, insert metal as shown in Figure 8 b form the first electrode 919, form the second electrode 920 at epitaxial surface, thus form the LED of the vertical stratification that usual dielectric substrate cannot be formed.
Wherein, through hole also can be only one, and shows after tested, and now the performance of device is also better than existing light emitting diode (LED) chip with vertical structure.
Epitaxial structure in the present embodiment is not limited to LED structure, also can be fieldtron structure.The electrode of epitaxial surface also can be source electrode and the drain electrode of fieldtron, and areal gate, and substrate surface through hole connecting conductive layer is as back grid, thus improves device performance.
It should be noted that, in this article, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
The above is only the specific embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. one kind is improved the semiconductor device of current expansion, the current extending that it is characterized in that comprising substrate and be formed on described substrate and epitaxial loayer, the material of described current extending is electric conducting material, and the conductivity of this electric conducting material is greater than the conductivity of described epitaxial film materials.
2. the semiconductor device improving current expansion according to claim 1, it is characterized in that: described electric conducting material comprises metal or nonmetallic materials, described metal material comprises the alloy of tungsten or tungsten, and described nonmetallic materials comprise Graphene or carbon nanotube film.
3. the semiconductor device improving current expansion according to claim 1, is characterized in that: described current extending is patterned conductive layer, and this graphics package draws together cellular grid.
4. the semiconductor device improving current expansion according to claim 1, it is characterized in that: described substrate is also formed with epitaxial buffer layer, described current extending is formed on described epitaxial buffer layer, and described current extending is distributed with the epitaxial loayer of secondary epitaxy growth formation.
5. the semiconductor device improving current expansion according to claim 1, is characterized in that: described current extending is cellular grid, and its thickness is 10nm ~ 200nm, and live width is 5 ~ 10 μm, and the spacing between adjacent lines is 100 ~ 200 μm.
6. the semiconductor device improving current expansion according to claim 1, it is characterized in that: described epitaxial loayer comprises the first polar layer, active layer and the second polar layer that are formed successively, and described first polar layer and the second polar layer are electrically connected with the first electrode and the second electrode respectively.
7. the semiconductor device improving current expansion according to claim 6, is characterized in that: the material of described first polar layer and the second polar layer is GaN, and described active layer is InGaN/GaN multiple quantum well layer.
8. the semiconductor device improving current expansion according to claim 6, it is characterized in that: described semiconductor device is inverted structure, its surface is provided with the second electrode lay in electrical contact with the second polar layer, described the second electrode lay regional area is formed with contact hole to the first polar layer direction, this contact hole leads to described first polar layer, the contact electrode of described first polar layer is connected with the first polar layer welding zone metal level on surface by contact hole, insulating barrier is provided with in the middle of the contact electrode of the first polar layer and connected welding zone metal and the second polar layer electrode under it and contact hole sidewall.
9. the semiconductor device improving current expansion according to claim 8, is characterized in that: the contact hole of the first polar layer only has one and diameter is less than 30um, and the first electrode and the second electrode are symmetrically distributed in described device both sides.
10. the semiconductor device improving current expansion according to claim 6, is characterized in that: described substrate is dielectric substrate, and described substrate runs through up and down and has through hole, and the electrode of substrate surface is connected with current extending by through hole.
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Cited By (4)
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| CN105702823A (en) * | 2016-04-11 | 2016-06-22 | 聚灿光电科技股份有限公司 | Small-sized light emitting diode (LED) chip and fabrication method thereof |
| CN107464864A (en) * | 2017-08-21 | 2017-12-12 | 厦门乾照光电股份有限公司 | Light emitting diode and preparation method thereof |
| CN109659413A (en) * | 2018-12-28 | 2019-04-19 | 华灿光电（浙江）有限公司 | A kind of light-emitting diode chip for backlight unit and preparation method thereof |
| CN112271241A (en) * | 2020-10-30 | 2021-01-26 | 华引芯（武汉）科技有限公司 | Manufacturing process of high-power LED chip and LED chip |
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Denomination of invention: Semiconductor device for improving current expanding Effective date of registration: 20200619 Granted publication date: 20180202 Pledgee: Bank of Jiangsu Limited by Share Ltd. Nanjing Hexi Branch Pledgor: NANJING JIASHIXIN ELECTRONIC Co.,Ltd. Registration number: Y2020980003265 |