JPH08330633A - Light-emitting semiconductor device - Google Patents

Light-emitting semiconductor device

Info

Publication number
JPH08330633A
JPH08330633A JP13056495A JP13056495A JPH08330633A JP H08330633 A JPH08330633 A JP H08330633A JP 13056495 A JP13056495 A JP 13056495A JP 13056495 A JP13056495 A JP 13056495A JP H08330633 A JPH08330633 A JP H08330633A
Authority
JP
Japan
Prior art keywords
light emitting
semiconductor
circuit board
emitting element
semiconductor light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13056495A
Other languages
Japanese (ja)
Inventor
Yoshifumi Bito
喜文 尾藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP13056495A priority Critical patent/JPH08330633A/en
Publication of JPH08330633A publication Critical patent/JPH08330633A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

PURPOSE: To obtain a light-emitting semiconductor device which eliminates high costs and a drop in productivity when a semiconductor light-emitting element is mounted on a circuit board and which can eliminate an irregularity in the contact resistance of the light-emitting semiconductor element with the circuit board. CONSTITUTION: In a light-emitting semiconductor device, an island-shaped semiconductor layer composed of at least two semiconductor layers which contain different impurities is formed on a semiconductor substrate, and a light-emitting semiconductor element 1 in which one pair of electrodes have been formed on the island-shaped semiconductor layer is mounted on a circuit board 2 to be mounted. The electrodes are formed on the same side as the island-shaped semiconductor layer on the semiconductor substrate, metal bumps 10 are installed so as to protrude on the electrodes 6, 7, flexible anisotropic conductive films 3 are interposed between the electrodes and the board 2 to be mounted, the semiconductor light-emitting element is mounted on the board to be mounted, and a light-transmitting resin 14 is interposed between the island-shaped semiconductor layer and the board to be mounted.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、例えばページプリンタ
ー用感光ドラムの露光用光源として用いられるLEDア
レイを備える半導体発光装置に関し、特に半導体発光素
子を被着回路基板に異方性導電膜を介して搭載すると共
に、半導体発光素子と被着回路基板間に透光性樹脂を介
在させて接続した半導体発光装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device provided with an LED array used as a light source for exposing a photosensitive drum for a page printer, and more particularly to a semiconductor light emitting element on an adhered circuit board via an anisotropic conductive film. The present invention relates to a semiconductor light emitting device in which the semiconductor light emitting element and the adherend circuit board are connected together with a translucent resin interposed therebetween.

【0002】[0002]

【従来の技術及びその問題点】半導体発光装置として
は、図5に示すように、半導体基板101の一方の主面
101aに複数の半導体層から成る発光素子102を形
成し、この発光素子102上から半導体基板101上に
かけて個別電極103を形成すると共に、半導体基板1
01の他方の主面101bに共通電極104を形成した
ものが従来から知られている。この半導体発光素子10
5を駆動回路が形成された被着回路基板に搭載する場
合、図6に示すように、その半導体発光素子105の共
通電極104を導電性ペースト107を介して被着回路
基板106上の共通配線108に接続し、発光素子10
2ごとに設けられた個別電極103をボンディングワイ
ヤー109によって、被着回路基板106上の個別配線
110に一つづつ接続することが行われている。
2. Description of the Related Art As a semiconductor light emitting device, as shown in FIG. 5, a light emitting element 102 composed of a plurality of semiconductor layers is formed on one main surface 101a of a semiconductor substrate 101, and on this light emitting element 102. The individual electrodes 103 are formed on the semiconductor substrate 101 from the semiconductor substrate 101 to the semiconductor substrate 101.
The one in which the common electrode 104 is formed on the other main surface 101b of 01 is conventionally known. This semiconductor light emitting device 10
5 is mounted on the adhered circuit board on which the drive circuit is formed, as shown in FIG. 6, the common electrode 104 of the semiconductor light emitting element 105 is connected via the conductive paste 107 to the common wiring on the adhered circuit board 106. The light emitting element 10 is connected to 108.
The individual electrodes 103 provided for every two are connected to the individual wirings 110 on the adhered circuit board 106 by the bonding wires 109 one by one.

【0003】なお、発光素子102は列状に多数設けら
れているが、図6における111は多数の発光素子10
2を選択的に発光させる駆動用ICである。
Although a large number of light emitting elements 102 are provided in a row, 111 in FIG. 6 is a large number of light emitting elements 10.
2 is a driving IC that selectively emits light.

【0004】ところが、上記半導体発光装置のように、
個別電極103を被着回路基板106上の配線110に
一つづつ接続する場合、発光素子102がせいぜい30
0〜400dpi程度の密度にしか対応できないという
問題があった。すなわち、それ以上の密度になると、発
光素子102の個別電極103と被着回路基板106の
個別配線110とはボンディングワイヤー109では接
続することができなくなる。
However, like the above semiconductor light emitting device,
When the individual electrodes 103 are connected to the wirings 110 on the adhered circuit board 106 one by one, the light emitting element 102 is 30 at most.
There is a problem in that it can only handle densities of about 0 to 400 dpi. That is, when the density is higher than that, the individual electrode 103 of the light emitting element 102 and the individual wiring 110 of the adhered circuit board 106 cannot be connected by the bonding wire 109.

【0005】また、発光素子102の個別電極103と
被着回路基板106の個別配線110をボンディングワ
イヤー109で個々に接続する場合、発光素子102が
高密度になると、生産性が低下するとともに、ワイヤー
ボンディングの作業性が煩雑で高コストになるという問
題があった。
When the individual electrodes 103 of the light emitting elements 102 and the individual wirings 110 of the adhered circuit board 106 are individually connected by the bonding wires 109, if the light emitting elements 102 have a high density, the productivity is lowered and the wires are There is a problem that the workability of bonding is complicated and the cost is high.

【0006】そこで、図7に示すように、各発光素子1
02の個別電極103と共通電極104’を半導体基板
101の一方の主面101aに設け、この個別電極10
3と共通電極104’に金バンプ112をそれぞれ形成
して、半導体発光素子105を構成し、この半導体発光
素子105をマイクロバンプボンディング法によって被
着回路基板106の共通配線108と個別配線110に
フェノール系樹脂113などの収縮力によって押し付け
て接続することが提案されている。
Therefore, as shown in FIG. 7, each light emitting element 1
No. 02 individual electrode 103 and common electrode 104 ′ are provided on one main surface 101 a of the semiconductor substrate 101.
3 and the common electrode 104 ′ to form gold bumps 112, respectively, to form the semiconductor light emitting element 105, and the semiconductor light emitting element 105 is phenol-bonded to the common wiring 108 and the individual wiring 110 of the adhered circuit board 106 by the micro bump bonding method. It has been proposed to press and connect with the contraction force of the resin 113 or the like.

【0007】ところが、この従来の半導体発光装置で
は、金バンプ112の高さが15〜20μm必要である
とともに、金バンプ112を被着回路基板106上の共
通配線108と個別配線110に接合させることなく、
当接させて接続することから、金バンプ112の高さの
違いによって接続状態が異なり、接続が不安定になって
接触抵抗のバラツキが生じ、発光素子102の発光特性
が不均一になると共に、金バンプ112の形成に長時間
を要するという問題があった。
However, in this conventional semiconductor light emitting device, the height of the gold bump 112 is required to be 15 to 20 μm, and the gold bump 112 is bonded to the common wiring 108 and the individual wiring 110 on the adhered circuit board 106. Without
Since they are brought into contact with each other to be connected, the connection state varies depending on the height of the gold bump 112, the connection becomes unstable and the contact resistance varies, and the light emitting characteristics of the light emitting element 102 become uneven. There is a problem that it takes a long time to form the gold bump 112.

【0008】[0008]

【発明の目的】本発明に係る半導体発光装置は、このよ
うな従来装置の問題点に鑑みて発明されたものであり、
半導体発光素子を被着回路基板に搭載する場合の生産性
の低下と高コスト化を解消すると共に、半導体発光素子
と被着回路基板の接触抵抗のバラツキを解消した半導体
発光装置を提供することを目的とする。
SUMMARY OF THE INVENTION The semiconductor light emitting device according to the present invention has been invented in view of the above problems of the conventional device.
It is possible to provide a semiconductor light emitting device that eliminates the reduction in productivity and the cost increase when mounting a semiconductor light emitting element on an adhered circuit board, and eliminates the variation in the contact resistance between the semiconductor light emitting element and the adhered circuit board. To aim.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
に、本発明に係る半導体発光装置では、半導体基板上
に、異なる半導体不純物を含有する少なくとも2層の半
導体層から成る島状半導体層を設け、この島状半導体層
に電流を流すための一対の電極を設けた半導体発光素子
を被着回路基板上に搭載した半導体発光装置において、
前記電極を前記半導体基板における前記半導体層と同じ
側に設けると共に、この電極上に金バンプを突出して設
け、この電極と前記被着基板との間に異方性導電膜を介
在させて前記半導体発光素子を前記被着基板上に搭載
し、前記島状半導体層と前記被着基板との間に透光性樹
脂を介在させた。
In order to achieve the above object, in a semiconductor light emitting device according to the present invention, an island-shaped semiconductor layer composed of at least two semiconductor layers containing different semiconductor impurities is provided on a semiconductor substrate. In a semiconductor light emitting device provided with a semiconductor light emitting element having a pair of electrodes for flowing a current through the island-shaped semiconductor layer, the semiconductor light emitting element is mounted on a target circuit board,
The electrode is provided on the same side of the semiconductor substrate as the semiconductor layer, and gold bumps are provided so as to project on the electrode, and an anisotropic conductive film is interposed between the electrode and the adherend substrate to form the semiconductor. A light emitting element was mounted on the adherend substrate, and a translucent resin was interposed between the island-shaped semiconductor layer and the adherend substrate.

【0010】[0010]

【作用】上記のように構成すると、半導体発光素子を被
着回路基板に搭載する場合、発光素子側の多数の電極と
被着回路基板上の多数の電極を一度に接続することがで
き、発光素子が高密度になっても、生産性を低下させる
ことがない。
With the above structure, when the semiconductor light emitting element is mounted on the adhered circuit board, a large number of electrodes on the light emitting element side and a large number of electrodes on the adhered circuit board can be connected at one time, and the Even if the element has a high density, the productivity is not reduced.

【0011】また、異方性導電膜は柔軟性を有すること
から、金バンプを低く形成でき、金バンプの高さに多少
のバラツキがあっても、全ての金バンプを異方性導電膜
に接続することができ、半導体発光素子と被着回路基板
の接触抵抗のバラツキを解消できる。
Further, since the anisotropic conductive film has flexibility, the gold bumps can be formed low, and even if there is some variation in the height of the gold bumps, all the gold bumps can be used as the anisotropic conductive film. Connection can be made, and variation in contact resistance between the semiconductor light emitting element and the adhered circuit board can be eliminated.

【0012】[0012]

【実施例】以下、本発明の実施例を添付図面に基づき詳
細に説明する。図1は、本発明に係る半導体発光装置の
一実施例を示す図であり、1は半導体発光素子、2は被
着回路基板、3は半導体発光素子1と被着回路基板2を
接続するための異方性導電膜である。
Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a diagram showing an embodiment of a semiconductor light emitting device according to the present invention, in which 1 is a semiconductor light emitting element, 2 is a circuit board to be adhered, and 3 is for connecting the semiconductor light emitting element 1 and the circuit board 2 to be adhered. Is an anisotropic conductive film.

【0013】図1に示す半導体発光素子1は、図2に示
すように、例えばシリコンなどから成る半導体基板4の
一方の主面4aにおいて一列に並列する複数の発光素子
(LED)5によって主として構成され、その半導体基
板4の一方の主面4aに各発光素子5毎に形成された個
別電極(アノード電極)6と、その基板4の一方の主面
4aの各発光素子5の両側に形成された共通電極(カソ
ード電極)7とを備えている。
As shown in FIG. 2, the semiconductor light emitting device 1 shown in FIG. 1 is mainly composed of a plurality of light emitting devices (LEDs) 5 arranged in a line on one main surface 4a of a semiconductor substrate 4 made of, for example, silicon. The individual electrode (anode electrode) 6 formed for each light emitting element 5 on the one main surface 4a of the semiconductor substrate 4 and both sides of each light emitting element 5 on the one main surface 4a of the substrate 4. And a common electrode (cathode electrode) 7.

【0014】発光素子5は、半導体基板4の一方の主面
4aに半導体結晶膜を有機金属気相エピタキシー(MO
CVD)や分子線エピタキシー(MBE)等により成長
させ、その成長層を発光素子5となる部分を残してエッ
チングすることで形成でき、例えば図3に示すように、
ガリウム砒素(GaAs)、ガリウム砒素リン(GaA
sP)、ガリウムリン(GaP)等の成長層であるバッ
ファ層5aと、アルミニウムガリウム砒素(Alx Ga
1-x As)の成長層であるn形半導体層5b、p形半導
体層5cおよびp+ 形半導体層5dとで構成され、さら
に窒化珪素(SiNx )や酸化珪素(SiO2 )などの
保護膜8をプラズマCVD等により形成することで構成
できる。
In the light emitting device 5, a semiconductor crystal film is formed on one main surface 4a of the semiconductor substrate 4 by metalorganic vapor phase epitaxy (MO).
CVD) or molecular beam epitaxy (MBE) and the like, and the growth layer can be formed by etching while leaving a portion to be the light emitting element 5, for example, as shown in FIG.
Gallium arsenide (GaAs), gallium arsenide phosphide (GaA)
buffer layer 5a, which is a growth layer of sP), gallium phosphide (GaP), or the like, and aluminum gallium arsenide (Al x Ga).
1-x As) growth layer, which is an n-type semiconductor layer 5b, a p-type semiconductor layer 5c, and ap + -type semiconductor layer 5d, and is further protected by silicon nitride (SiN x ) or silicon oxide (SiO 2 ). It can be formed by forming the film 8 by plasma CVD or the like.

【0015】各個別電極9は、各発光素子5を覆う保護
膜8の一部をエッチングで除去することで露出するp+
形半導体層5dに接続され、図2に示すように、各発光
素子5の並列方向(図2における左右方向)に直角な方
向(図2において上下方向)に引き出され、一方の側方
側に引き出されるものと他の側方側に引き出されるもの
とが交互に並列し、その引き出し端の上に金バンプ(導
電性部材)10が形成されている。
Each individual electrode 9 is exposed by removing a part of the protective film 8 covering each light emitting element 5 by etching p +.
2 is connected to the semiconductor layer 5d, and as shown in FIG. 2, the light-emitting elements 5 are drawn out in a direction (vertical direction in FIG. 2) perpendicular to the parallel direction (horizontal direction in FIG. 2) and to one side side. The drawn-out pieces and the drawn-out pieces on the other side are alternately arranged in parallel, and gold bumps (conductive members) 10 are formed on the drawn-out ends.

【0016】各共通電極7は、保護膜8の一部をエッチ
ングで除去することで露出する半導体基板4の一方の主
面4aに接続され、発光素子5の配列に沿う帯状とさ
れ、その上に間隔をおいて複数の金バンプ(導電性部
材)10が形成されている。
Each common electrode 7 is connected to one main surface 4a of the semiconductor substrate 4 which is exposed by removing a part of the protective film 8 by etching, and is formed into a strip shape along the arrangement of the light emitting elements 5, and above it. A plurality of gold bumps (conductive members) 10 are formed at intervals.

【0017】各金バンプ10は、例えば各電極6、7上
の直径数十μm程度のバンプ形成部分を除いてレジスト
によって被覆し、しかる後に電気メッキによって金を厚
さ3〜4μm程度に成膜することで形成できる。メッキ
液の組成としては、例えばシアン化金カリウムを4〜8
重量%、クエン酸カリウムを30〜40重量%、第一り
ん酸カリウムを30〜40重量%、クエン酸を20〜3
0重量%、エチレンジアミン二酢酸ニッケルを2〜3重
量%それぞれ混合した液を用いることができる。その電
気メッキは、複数の発光素子5をシリコンウェハー上に
作り込んだ状態で、各電極6、7を全て互いに接続する
短絡配線を設け、その短絡配線を介し各電極6、7をメ
ッキ電極に接続することで行い、そのウェハを分断して
発光素子5を互いに分離する際に短絡配線を各電極6、
7相互間で切断するようにしてもよい。
Each gold bump 10 is covered with a resist except for bump forming portions having a diameter of several tens of μm on the electrodes 6 and 7, and then gold is deposited by electroplating to a thickness of about 3 to 4 μm. Can be formed. As the composition of the plating solution, for example, potassium gold cyanide of 4 to 8 is used.
% By weight, 30-40% by weight potassium citrate, 30-40% by weight potassium monophosphate, 20-3% citric acid.
It is possible to use a liquid in which 0% by weight and nickel diamine diacetate of 2 to 3% by weight are mixed. In the electroplating, short-circuit wirings that connect all the electrodes 6 and 7 to each other are provided in a state where a plurality of light-emitting elements 5 are formed on a silicon wafer, and the electrodes 6 and 7 are used as plating electrodes through the short-circuit wirings. When the light emitting elements 5 are separated from each other by dividing the wafer by connecting the short-circuit wiring to each electrode 6,
You may make it cut | disconnect between 7 mutual.

【0018】また、図4に示すように、電極7をアルミ
ニウム薄膜により形成し、この電極7と金バンプ10と
の間に、クロム(Cr)11a、ニッケル(Ni)11
bおよび金(Au)11cを蒸着やスッパタリングによ
って順次成長させた三層金属膜11を介在させてもよ
い。
Further, as shown in FIG. 4, the electrode 7 is formed of an aluminum thin film, and chromium (Cr) 11a and nickel (Ni) 11 are provided between the electrode 7 and the gold bump 10.
It is also possible to interpose a three-layer metal film 11 in which b and gold (Au) 11c are sequentially grown by vapor deposition or sputtering.

【0019】上記半導体発光装置1は、図1に示すよう
に、金バンプ10と被着回路基板2の配線との間に異方
性導電膜3を介在させて半導体発光素子1と被着回路基
板2を接続する。
In the semiconductor light emitting device 1, as shown in FIG. 1, the anisotropic conductive film 3 is interposed between the gold bump 10 and the wiring of the adhered circuit board 2 to form the semiconductor light emitting element 1 and the adhered circuit. The board 2 is connected.

【0020】異方性導電膜3は、樹脂のフィルム中に、
ニッケルやカーボン等で金属コーティングした微細粒子
が分散しているもので、フィルムの片面にはテープが付
いている。このテープを剥がし半導体発光素子1の金バ
ンプ10が形成された電極6、7と被着回路基板2の配
線12、13がちょうど繋がるように位置合わせし、被
着回路基板2の配線6、7上に異方性導電膜3を置いて
圧着する。
The anisotropic conductive film 3 is formed of a resin film,
Fine particles coated with metal such as nickel or carbon are dispersed, and a tape is attached to one side of the film. The tape is peeled off, and the electrodes 6 and 7 of the semiconductor light emitting device 1 on which the gold bumps 10 are formed and the wirings 12 and 13 of the adhered circuit board 2 are aligned so that they are just connected, and the wirings 6 and 7 of the adhered circuit board 2 are aligned. Anisotropic conductive film 3 is placed on top and pressure-bonded.

【0021】圧着は、まず約60℃〜70℃の熱を加え
て仮圧着し、つぎに170℃の熱を加えて本圧着すると
いう二段方式にする。この際、半導体発光素子1の金バ
ンプ10と被着回路基板2の配線12、13が丁度繋が
る場所にある金属コーティングしたプラスチックのボー
ルが潰れ、異方性導電膜3は接着材の役割をすると同時
に、半導体発光素子1の金バンプ10と被着回路基板2
の配線12、13間に電気を通す役割をもつ。
The pressure bonding is a two-stage system in which heat of about 60 ° C. to 70 ° C. is first applied for temporary pressure bonding, and then heat of 170 ° C. is applied for main pressure bonding. At this time, the metal-coated plastic balls at the positions where the gold bumps 10 of the semiconductor light emitting element 1 and the wirings 12 and 13 of the adhered circuit board 2 are just connected are crushed, and the anisotropic conductive film 3 acts as an adhesive. At the same time, the gold bumps 10 of the semiconductor light emitting device 1 and the adhered circuit board 2
It also has a role of conducting electricity between the wirings 12 and 13.

【0022】なお、金バンプ10が設けられた領域以外
の領域では、異方性導電膜3中の金属コーティングした
プラスティックボールが潰れることはなく、絶縁性が保
たれる。
In the region other than the region where the gold bump 10 is provided, the metal ball coated with the metal in the anisotropic conductive film 3 is not crushed and the insulating property is maintained.

【0023】マイクロバンプボンディング法では、金層
の厚みを15〜20μm程度にしなければならないが、
異方性導電膜3を用いる方法では、3〜4μm程度です
む。
In the micro bump bonding method, the gold layer must have a thickness of about 15 to 20 μm.
The method using the anisotropic conductive film 3 requires about 3 to 4 μm.

【0024】発光素子1と被着回路基板2との間には隙
間ができるが、発光素子1の光を被着回路基板2に導い
て被着回路基板2の裏面側から効率よく放射するために
は、この隙間部分にシリコン樹脂等の透光性樹脂14を
充填するとよい。このように発光素子1と被着回路基板
2の隙間にシリコン樹脂14を充填すると、シリコン樹
脂14がないときのような空気層中での光の乱反射が防
止でき、発光素子1の光を効率よく被着回路基板2に放
射させることができる。
Although a gap is formed between the light emitting element 1 and the adhered circuit board 2, in order to guide the light of the light emitting element 1 to the adhered circuit board 2 and efficiently radiate it from the back side of the adhered circuit board 2. It is preferable that the transparent resin 14 such as silicon resin is filled in the gap. By thus filling the gap between the light emitting element 1 and the adhered circuit board 2 with the silicone resin 14, irregular reflection of light in the air layer, which would occur when the silicone resin 14 is not present, can be prevented, and the light of the light emitting element 1 can be efficiently emitted. It can be well radiated to the adhered circuit board 2.

【0025】この場合、発光素子5と被着回路基板5間
の隙間部分のみならず、半導体発光素子1を保護するた
めに、この半導体発光素子1の周辺部全体を透光性樹脂
で被覆してもよい。
In this case, in order to protect the semiconductor light emitting element 1 as well as the gap between the light emitting element 5 and the adhered circuit board 5, the entire peripheral portion of the semiconductor light emitting element 1 is covered with a transparent resin. May be.

【0026】[0026]

【発明の効果】以上のように、本発明に係る半導体発光
装置によれば、半導体発光素子と被着回路基板を異方性
導電膜を介して接続することから、発光素子が高密度に
なっても、多数の発光素子の電極と被着回路基板の配線
を一度に接続することができ、生産性を著しく向上させ
ることができるとともに、接続の信頼性が向上する。
As described above, according to the semiconductor light emitting device of the present invention, since the semiconductor light emitting element and the adhered circuit board are connected through the anisotropic conductive film, the light emitting element has a high density. However, the electrodes of a large number of light emitting elements and the wirings of the adhered circuit board can be connected at one time, the productivity can be remarkably improved, and the connection reliability is improved.

【0027】また、発光素子と被着回路基板の隙間部分
に透光性樹脂を充填することから、発光素子の光を効率
よく被着回路基板の裏面側から放射することができる。
Further, since the transparent resin is filled in the gap between the light emitting element and the adhered circuit board, the light of the light emitting element can be efficiently radiated from the rear surface side of the adhered circuit board.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る半導体発光装置の一実施例を示す
断面図である。
FIG. 1 is a sectional view showing an embodiment of a semiconductor light emitting device according to the present invention.

【図2】本発明に係る半導体発光装置に用いられる半導
体発光素子の平面図である。
FIG. 2 is a plan view of a semiconductor light emitting element used in the semiconductor light emitting device according to the present invention.

【図3】本発明に係る半導体発光装置に用いられる半導
体発光素子の断面図である。
FIG. 3 is a cross-sectional view of a semiconductor light emitting element used in a semiconductor light emitting device according to the present invention.

【図4】本発明に係る半導体発光装置における半導体発
光素子と被着回路基板の接続部を拡大して示す図であ
る。
FIG. 4 is an enlarged view showing a connection portion between a semiconductor light emitting element and an adhered circuit board in a semiconductor light emitting device according to the present invention.

【図5】従来の半導体発光素子を示す断面図である。FIG. 5 is a cross-sectional view showing a conventional semiconductor light emitting device.

【図6】従来の半導体発光装置を示す断面図である。FIG. 6 is a cross-sectional view showing a conventional semiconductor light emitting device.

【図7】従来の他の半導体発光装置を示す断面図であ
る。
FIG. 7 is a cross-sectional view showing another conventional semiconductor light emitting device.

【符号の説明】[Explanation of symbols]

1・・・半導体発光素子、2・・・被着回路基板、3・
・・異方性導電膜
DESCRIPTION OF SYMBOLS 1 ... Semiconductor light emitting element, 2 ... Adhered circuit board, 3 ...
..Anisotropic conductive film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に、異なる半導体不純物を
含有する少なくとも2層の半導体層から成る島状半導体
層を設け、この島状半導体層に電流を流すための一対の
電極を設けた半導体発光素子を被着回路基板上に搭載し
た半導体発光装置において、前記電極を前記半導体基板
における前記半導体層と同じ側に設けると共に、この電
極上に金バンプを突出して設け、この電極と前記被着基
板との間に異方性導電膜を介在させて前記半導体発光素
子を前記被着基板上に搭載し、前記島状半導体層と前記
被着基板との間に透光性樹脂を介在させたことを特徴と
する半導体発光装置。
1. A semiconductor light-emitting device comprising a semiconductor substrate, an island-shaped semiconductor layer including at least two semiconductor layers containing different semiconductor impurities, and a pair of electrodes for passing a current through the island-shaped semiconductor layer. In a semiconductor light emitting device in which an element is mounted on an adhered circuit board, the electrode is provided on the same side of the semiconductor substrate as the semiconductor layer, and a gold bump is provided on the electrode so as to project therefrom. The semiconductor light emitting element is mounted on the adherend substrate with an anisotropic conductive film interposed therebetween, and a translucent resin is interposed between the island-shaped semiconductor layer and the adherend substrate. And a semiconductor light emitting device.
JP13056495A 1995-05-29 1995-05-29 Light-emitting semiconductor device Pending JPH08330633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13056495A JPH08330633A (en) 1995-05-29 1995-05-29 Light-emitting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13056495A JPH08330633A (en) 1995-05-29 1995-05-29 Light-emitting semiconductor device

Publications (1)

Publication Number Publication Date
JPH08330633A true JPH08330633A (en) 1996-12-13

Family

ID=15037277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13056495A Pending JPH08330633A (en) 1995-05-29 1995-05-29 Light-emitting semiconductor device

Country Status (1)

Country Link
JP (1) JPH08330633A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7176623B2 (en) 2001-04-09 2007-02-13 Kabushiki Kaisha Toshiba Light emitting device
JP2012178400A (en) * 2011-02-25 2012-09-13 Toyoda Gosei Co Ltd Led lamp
JP2015065255A (en) * 2013-09-25 2015-04-09 沖電気工業株式会社 Photoelectric fusion module
JP2015076613A (en) * 2013-10-07 2015-04-20 廣▲ジャー▼光電股▲ふん▼有限公司 Light emitting diode module and method for manufacturing the same
JP2019096854A (en) * 2017-11-24 2019-06-20 ルーメンス カンパニー リミテッド Manufacturing method of high efficiency micro led module

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7176623B2 (en) 2001-04-09 2007-02-13 Kabushiki Kaisha Toshiba Light emitting device
US7569989B2 (en) 2001-04-09 2009-08-04 Kabushiki Kaisha Toshiba Light emitting device
JP2012178400A (en) * 2011-02-25 2012-09-13 Toyoda Gosei Co Ltd Led lamp
JP2015065255A (en) * 2013-09-25 2015-04-09 沖電気工業株式会社 Photoelectric fusion module
JP2015076613A (en) * 2013-10-07 2015-04-20 廣▲ジャー▼光電股▲ふん▼有限公司 Light emitting diode module and method for manufacturing the same
JP2019096854A (en) * 2017-11-24 2019-06-20 ルーメンス カンパニー リミテッド Manufacturing method of high efficiency micro led module

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