CN115799263A - Semiconductor device and electronic device - Google Patents

Abstract

The application provides a semiconductor device and an electronic device, the semiconductor device comprises an insulating substrate and a thin film transistor layer located on the insulating substrate, the thin film transistor layer comprises an active layer and a first metal layer located on the active layer, the active layer comprises an active section and a conductor layer which are arranged in a stacked mode, the conductor layer comprises a first conductor section and a second conductor section which are arranged on the active section at intervals, and the first metal layer comprises a first electrode connected with the first conductor section and a second electrode connected with the second conductor section; the semiconductor device further comprises a compensation part arranged in the groove, the compensation part comprises a conductive part, the conductive part is connected with one of the first electrode and the second electrode, and the conductive part is insulated from the other of the first electrode and the second electrode, so that the channel length is reduced, and the on-state current of the semiconductor device is improved.

Description

Semiconductor device and electronic device

Technical Field

The present application relates to the field of display technologies, and in particular, to a semiconductor device and an electronic device.

Background

At present, please refer to fig. 1, which is a schematic structural diagram of a conventional display panel; the conventional display panel 1 includes an insulating substrate 10, a light shielding layer 70, a buffer layer 80, a thin film transistor layer 20, a planarization layer 91, a common electrode 62A, a passivation layer 92, and a pixel electrode 61A, which are stacked, where the thin film transistor layer 20 includes an active layer 23, a gate insulating layer 22, a gate electrode 21, an interlayer insulating layer 25, a source electrode 24A1, and a drain electrode 24B1, which are sequentially stacked on the insulating substrate 10.

It is understood that, in the prior art, the Thin Film Transistor layer includes a plurality of Thin Film transistors 20A (TFTs) arranged in a matrix, and the Thin Film transistors 20A control a current between the source and drain electrodes 24A1 and 24B1 using a gate voltage, thereby functioning as switching elements of the display panel; as the performance of the display device is improved, the channel in the thin film transistor 20A is required to have a larger width-to-length ratio, and the width-to-length ratio of the channel determines the functional characteristics of the thin film transistor 20A, and under the condition that the channel width is constant, shortening the length of the channel can enable the thin film transistor to have a larger width-to-length ratio, so as to have a larger on-state current.

However, in the manufacturing process of the conventional thin film transistor, the length of the channel is directly limited by the photolithography process, so that it is difficult to realize a short channel; meanwhile, in the prior art, when the source electrode and the drain electrode are formed on the active layer by using an etching process, the metal material is affected by the etching solution, so that the channel length is increased, and the on-state current of the thin film transistor is reduced.

Disclosure of Invention

Embodiments of the present application provide a semiconductor device and an electronic device to alleviate the disadvantages of the related art.

In order to realize the above functions, the technical solutions provided in the embodiments of the present application are as follows:

1. an embodiment of the present application provides a semiconductor device, including:

an insulating substrate:

thin-film transistor layer, set up in on the insulating substrate, thin-film transistor layer includes:

the active layer is arranged on the insulating substrate and comprises an active section and a conductor layer which are arranged in a stacked mode, and the conductor layer comprises a first conductor section and a second conductor section which are arranged on the active section at intervals;

the first metal layer is arranged on one side, far away from the insulating substrate, of the active layer and comprises a first electrode connected with the first conductor section and a second electrode connected with the second conductor section;

wherein the active layer comprises a groove between the first electrode and the second electrode, the depth of the groove is smaller than the thickness of the active layer and larger than the thickness of the conductor layer;

the semiconductor device further comprises a compensation part arranged in the groove, wherein the compensation part at least comprises a conductive part, the conductive part is connected with one of the first electrode and the second electrode, and the conductive part is insulated from the other of the first electrode and the second electrode.

In the semiconductor device provided by the embodiment of the present application, the compensation portion includes a first compensation sub-portion and a second compensation sub-portion located between the conductive portion and the active segment, a sum of a thickness of the first compensation sub-portion and a thickness of the second compensation sub-portion is smaller than or equal to a depth of the groove, and the conductive portion extends from the second compensation sub-portion to a direction away from the groove.

In the semiconductor device provided by the embodiment of the application, an orthogonal projection of the conductive part on the insulating substrate overlaps an orthogonal projection of the second compensating sub-part on the insulating substrate, and an orthogonal projection of the second compensating sub-part on the insulating substrate overlaps an orthogonal projection of the first compensating sub-part on the insulating substrate.

In the semiconductor device provided in the embodiment of the present application, the material of the first compensation subsection is the same as that of the active segment, the material of the second compensation subsection is the same as that of the conductor layer, and the material of the conductive part is the same as that of the first metal layer.

In the semiconductor device provided by the embodiment of the application, the compensation part comprises a first compensation sub-part and a second compensation sub-part which are positioned between the conductive part and the active section, the sum of the thickness of the first compensation sub-part and the thickness of the second compensation sub-part is equal to the depth of the groove, and the second compensation sub-part is positioned between the first compensation sub-part and the conductive part;

the side of the first compensation sub-portion, which is far away from the insulation substrate, is flush with the side of the active section, which is far away from the insulation substrate, the side of the second compensation sub-portion, which is far away from the insulation substrate, is flush with the side of the conductor layer, which is far away from the insulation substrate, and the side of the conductive portion, which is far away from the insulation substrate, is flush with the side of the first metal layer, which is far away from the insulation substrate.

In the semiconductor device provided by the embodiment of the application, the semiconductor device further comprises a first insulating layer positioned on one side of the first metal layer far away from the active layer, and the first insulating layer extends from one side of the first metal layer far away from the active layer into the groove;

wherein at least a portion of the first insulating layer is located between the conductive portion and the first electrode, or at least a portion of the first insulating layer is located between the conductive portion and the second electrode.

In the semiconductor device provided in the embodiment of the present application, the conductive portion is connected to the first electrode;

the first insulating layer includes a first insulating sub-portion and a second insulating sub-portion connected to each other, an orthogonal projection of the first insulating sub-portion on the substrate covers an orthogonal projection of the second electrode on the substrate, the second insulating sub-portion is located in the groove, and the second insulating sub-portion is disposed between the compensation portion and the second electrode.

In the semiconductor device provided in the embodiment of the present application, the conductive portion is connected to the second electrode;

the first insulating layer includes a first insulating sub-portion and a second insulating sub-portion connected to each other, an orthographic projection of the first insulating sub-portion on the substrate covers an orthographic projection of the first electrode on the substrate, the second insulating sub-portion is located in the groove, and the second insulating sub-portion is disposed between the compensation portion and the first electrode.

In the semiconductor device provided by the embodiment of the application, the thin film transistor layer includes a gate electrode, a gate insulating layer, the active layer, the first electrode and the second electrode which are sequentially stacked;

wherein the first electrode covers the first conductor segment, the second electrode covers the second conductor segment, and an orthographic projection of the gate electrode on the insulating substrate covers an orthographic projection of the active layer on the insulating substrate.

An embodiment of the present application provides an electronic device including any one of the semiconductor devices described above.

The beneficial effects of the embodiment of the application are as follows: according to the semiconductor device, the active layer comprises the groove located between the first electrode and the second electrode, the depth of the groove is larger than the thickness of the conductor layer and smaller than the thickness of the active layer, the semiconductor device further comprises the compensation portion arranged in the groove, the compensation portion at least comprises the conductive portion, the conductive portion is connected with one of the first electrode and the second electrode, and the conductive portion is arranged in an insulating mode with the other of the first electrode and the second electrode, so that the channel length is reduced, the on-state current is improved, and the power consumption of the semiconductor device is reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a conventional display panel;

fig. 2 is a first top cross-sectional view of a semiconductor device provided in an embodiment of the present application;

FIG. 3 isbase:Sub>A schematic cross-sectional view taken along line A-A' of FIG. 2;

fig. 4 is a second top cross-sectional view of a semiconductor device provided in an embodiment of the present application;

FIG. 5 is a schematic cross-sectional view taken along line B-B' of FIG. 4;

fig. 6 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure;

fig. 7A to 7G are process flow diagrams of the structure of the semiconductor device in fig. 6.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.

The embodiment of the application provides a semiconductor device and an electronic device. The following are detailed descriptions. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.

Referring to fig. 2 to 7G, in an embodiment of the present invention, a semiconductor device and an electronic device are provided, where the semiconductor device 2 includes:

insulating substrate 10:

a thin-film transistor layer 20 disposed on the insulating substrate 10, the thin-film transistor layer 20 including:

an active layer 23 disposed on the insulating substrate 10, wherein the active layer 23 includes an active segment 23A and a conductor layer 231 stacked on each other, and the conductor layer 231 includes a first conductor segment 23B and a second conductor segment 23C spaced apart from each other on the active segment 23A;

a first metal layer 24 disposed on a side of the active layer 23 remote from the insulating substrate 10, the first metal layer 24 including a first electrode 24A connected to the first conductor segment 23B and a second electrode 24B connected to the second conductor segment 23C;

wherein the active layer 23 includes a groove 230 between the first electrode 24A and the second electrode 24B, and a depth of the groove 230 is smaller than a thickness of the active layer 23 and larger than a thickness of the conductor layer 231;

the semiconductor device 2 further includes a compensation portion 30 disposed in the groove 230, the compensation portion 30 at least includes a conductive portion 33, the conductive portion 33 is connected to one of the first electrode 24A and the second electrode 24B, and the conductive portion 33 is disposed in an insulating manner from the other of the first electrode 24A and the second electrode 24B.

It can be understood that, in the embodiment of the present application, by providing that the active layer 23 includes the groove 230 located between the first electrode 24A and the second electrode 24B, the depth of the groove 230 is smaller than the thickness of the active layer 23 and larger than the thickness of the conductor layer 231, the semiconductor device 2 further includes the compensation portion 30 located in the groove 230, the compensation portion 30 at least includes the conductive portion 33, the conductive portion 33 is connected to one of the first electrode 24A and the second electrode 24B, and the conductive portion 33 is insulated from the other of the first electrode 24A and the second electrode 24B, so as to reduce the channel length, promote the on-state current, and reduce the power consumption of the semiconductor device 2.

The technical solution of the present application will now be described with reference to specific embodiments.

In one embodiment, please combine fig. 2 and fig. 3; fig. 2 is a first top cross-sectional view of a semiconductor device provided in an embodiment of the present application; fig. 3 isbase:Sub>A schematic sectional view taken alongbase:Sub>A-base:Sub>A' direction in fig. 2.

In this embodiment, the semiconductor device 2 includes an insulating substrate 10 and a thin-film transistor layer 20 disposed on the insulating substrate 10, where the insulating substrate 10 may include a rigid substrate or a flexible substrate, and the material of the insulating substrate 10 is not particularly limited in this embodiment.

The thin-film transistor layer 20 includes a gate electrode 21, a gate insulating layer 22, an active layer 23, and a first metal layer 24 sequentially stacked on the insulating substrate 10, the active layer 23 includes an active segment 23A and a conductor layer 231 stacked on each other, the conductor layer 231 includes a first conductor segment 23B and a second conductor segment 23C spaced apart from each other on the active segment 23A, the first metal layer 24 includes a first electrode 24A connected to the first conductor segment 23B and a second electrode 24B connected to the second conductor segment 23C, the first electrode 24A includes, but is not limited to, a source electrode, the second electrode 24B includes, but is not limited to, a drain electrode, the first conductor segment 23B and the second conductor segment 23C have the same projection pattern, and the first electrode 24A and the second electrode 24B have different projection patterns.

The thin film transistor layer 20 comprises a plurality of thin film transistors 20A arranged in a matrix manner, one thin film transistor 20A is correspondingly located in one sub-pixel region, and the thin film transistor 20A comprises a gate 21, a gate insulating layer 22, an active layer 23, a first electrode 24A and a second electrode 24B which are arranged in a stacking manner.

The material of the active layer 23 includes, but is not limited to, amorphous silicon, polysilicon, or an oxide semiconductor material; preferably, the first conductor segment 23B and the second conductor segment 23C are each made of polysilicon doped with n-type impurities at high concentration, the shape of the first conductor segment 23B and the shape of the second conductor segment 23C are the same, an orthographic projection of the active segment 23A on the insulating substrate 10 covers an orthographic projection of the first conductor segment 23B on the insulating substrate 10, and an orthographic projection of the active segment 23A on the insulating substrate 10 covers an orthographic projection of the second conductor segment 23C on the insulating substrate 10.

The material of the gate electrode 21 is a metal material, and the metal material includes, but is not limited to, one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni); the orthographic projection of the gate electrode 21 on the insulating substrate 10 covers the orthographic projection of the active layer 23 on the insulating substrate 10; it can be understood that, with reference to fig. 1, in the prior art, a light shielding layer is usually disposed between the insulating substrate 10 and the active layer 23, and the light shielding layer can shield light that is incident on the active layer 23, so as to reduce an increase in leakage current caused by photo-generated carriers generated by irradiating the active layer 23 with light, and further maintain stability of the active layer 23 during operation.

The material of the first metal layer 24 includes, but is not limited to, one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni), the first electrode 24A covers the first conductor segment 23B, and the second electrode 24B covers the second conductor segment 23C, specifically, an orthographic projection of the first electrode 24A on the insulating substrate 10 covers an orthographic projection of the first conductor segment 23B on the insulating substrate 10, and an orthographic projection of the second electrode 24B on the insulating substrate 10 covers an orthographic projection of the second conductor segment 23C on the insulating substrate 10; it can be understood that, with reference to fig. 1, compared with the existing thin film transistor layer manufacturing process, in this embodiment, a contact via does not need to be formed through an etching process, so that the first electrode 24A and the second electrode 24B are connected to the active layer 23 through the contact via, and the manufacturing cost is further saved.

In this embodiment, the active layer 23 includes a groove 230 located between the first electrode 24A and the second electrode 24B, the depth of the groove 230 is smaller than the thickness of the active layer 23 and greater than the thickness of the conductor layer 231, and further, the width of the groove 230 is equal to the distance between the first electrode 24A and the second electrode 24B; wherein the semiconductor device 2 further comprises a compensation portion 30 disposed in the groove 230, the compensation portion 30 at least comprises a conductive portion 33, the conductive portion 33 is connected to one of the first electrode 24A and the second electrode 24B, and the conductive portion 33 is disposed in an insulating manner from the other of the first electrode 24A and the second electrode 24B.

Specifically, in the present embodiment, the conductive portion 33 is connected to the second electrode 24B, and the conductive portion 33 is insulated from the first electrode 24A; it can be understood that, in the present embodiment, by providing that the active segment 23A includes a groove 230 located between the first electrode 24A and the second electrode 24B, the depth of the groove 230 is less than the thickness of the active layer 23 and greater than the thickness of the conductor layer 231, the width of the groove 230 is equal to the distance between the first electrode 24A and the second electrode 24B, the semiconductor device 2 further includes a compensation portion 30 disposed in the groove 230, the compensation portion 30 at least includes a conductive portion 33, the conductive portion 33 is connected to the second electrode 24B, so as to increase the width of the second electrode 24B, thereby reducing the channel (channel) length of the thin film transistor 20A, increasing the on-state current, and reducing the power consumption of the semiconductor device 2; moreover, the conductive portion 33 is insulated from the first electrode 24A, so that the second electrode 24B is prevented from being conductive with the first electrode 24A, thereby affecting the electrical characteristics of the thin film transistor 20A.

In the present embodiment, the compensation portion 30 includes a first compensation sub-portion 31 and a second compensation sub-portion 32 located between the conductive portion 33 and the active section 23A, a sum of a thickness of the first compensation sub-portion 31 and a thickness of the second compensation sub-portion 32 is smaller than or equal to a depth of the groove 230, and the conductive portion 33 extends from the second compensation sub-portion 32 in a direction away from the groove 230.

Preferably, the sum of the thickness of the first compensation sub-portion 31 and the thickness of the second compensation sub-portion 32 is equal to the depth of the groove 230, the second compensation sub-portion 32 is located between the first compensation sub-portion 31 and the conductive portion 33, the side of the first compensation sub-portion 31 away from the insulating substrate 10 is flush with the side of the active segment 23A away from the insulating substrate 10, the side of the second compensation sub-portion 32 away from the insulating substrate 10 is flush with the side of the conductor layer 231 away from the insulating substrate 10, and the side of the conductive portion 33 away from the insulating substrate 10 is flush with the side of the first metal layer 24 away from the active layer 23.

Further, the orthographic projection of the conductive part 33 on the insulating substrate 10 overlaps with the orthographic projection of the second compensating sub-part 32 on the insulating substrate 10, and the orthographic projection of the second compensating sub-part 32 on the insulating substrate 10 overlaps with the orthographic projection of the first compensating sub-part 31 on the insulating substrate 10, so that the flatness of the thin film transistor 20A is maintained, and the flatness of the semiconductor device 2 is maintained; further, the material of the first compensation sub-section 31 is the same as that of the active segment 23A, the material of the second compensation sub-section 32 is the same as that of the conductor layer 231, and the material of the conductive section 33 is the same as that of the first metal layer 24, so as to maintain the electrical characteristics of the thin film transistor 20A.

Further, in this embodiment, the semiconductor device 2 further includes a first insulating layer 40 located on a side of the first metal layer 24 away from the active layer 23, wherein the first insulating layer 40 extends from the side of the first metal layer 24 away from the active layer 23 into the groove 230; wherein at least a portion of the first insulating layer 40 is located between the conductive portion 33 and the first electrode 24A.

Specifically, in the present embodiment, the first insulating layer 40 includes a first insulating portion 41 and a second insulating portion 42 connected to each other, and an orthographic projection of the first insulating portion 41 on the substrate covers an orthographic projection of the first electrode 24A on the substrate, thereby acting as a barrier to water and oxygen and insulation for the first electrode 24A; the second insulator portion 42 is disposed in the recess 230, and the second insulator portion 42 is disposed between the compensation portion 30 and the first electrode 24A, so that the conductive portion 33 is insulated from the first electrode 24A, and the second electrode 24B is prevented from being electrically connected to the first electrode 24A, thereby affecting the electrical characteristics of the thin film transistor 20A.

It is understood that, in the present embodiment, the channel (not labeled in the figure) of the thin film transistor 20A is located between the first conductor segment 23B and the second conductor segment 23C, that is, the active segment 23A, and the length of the channel is equal to the width of the second insulator portion 42, so that the length of the channel can be determined by the width of the second insulator portion 42, and therefore, under the condition that the width of the channel is constant, the present embodiment can shorten the length of the channel by reducing the width of the second insulator portion 42, thereby enabling the thin film transistor 20A to have a larger aspect ratio, thereby having a larger on-state current, and reducing the power consumption of the thin film transistor 20A.

Specifically, in the present embodiment, the semiconductor device 2 further includes a third electrode 61 located between the second electrode 24B and the gate insulating layer 22, a second insulating layer 50 located on a side of the first insulating layer 40 away from the first metal layer 24, and a fourth electrode 62 located on a side of the second insulating layer 50 away from the first insulating layer 40; wherein the third electrode 61 is connected to the second electrode 24B, an orthogonal projection of the third electrode 61 on the insulating substrate 10 at least coincides with an orthogonal projection of a part of the second electrode 24B on the insulating substrate 10, an orthogonal projection of the third electrode 61 on the insulating substrate 10 does not overlap with the first electrode 24A on the insulating substrate 10, and an orthogonal projection of the third electrode 61 on the insulating substrate 10 does not overlap with the gate electrode 21 on the insulating substrate 10; the third electrode 61 is one of a pixel electrode and a common electrode, and the fourth electrode 62 is the other of the pixel electrode and the common electrode.

It can be understood that, with reference to fig. 1, compared with the existing manufacturing process of the thin-film transistor layer 20, in this embodiment, a contact via does not need to be formed through an etching process, so that the second electrode 24B is connected to the third electrode 61 through the contact via, which further saves the manufacturing cost; further, the third electrode 61, the second electrode 24B, and the fourth electrode 62 are sequentially stacked on the insulating substrate, whereby the thickness of the semiconductor device 2 is reduced.

Please refer to fig. 4 and 5; fig. 4 is a second top cross-sectional view of a semiconductor device provided in an embodiment of the present application; fig. 5 is a schematic cross-sectional view taken along the direction B-B' in fig. 4.

In this embodiment, the structure of the display panel is similar to/the same as the first structure of the semiconductor device provided in the above embodiment, and please refer to the description of the semiconductor device in the above embodiment, which is not repeated herein, and the difference between the two structures is only:

in the present embodiment, the conductive portion 33 is connected to the first electrode 24A, and the conductive portion 33 is insulated from the second electrode 24B; it can be understood that, in the present embodiment, by providing that the active segment 23A includes a groove 230 located between the first electrode 24A and the second electrode 24B, the depth of the groove 230 is smaller than the thickness of the active layer 23 and larger than the thickness of the conductor layer 231, the width of the groove 230 is equal to the distance between the first electrode 24A and the second electrode 24B, the semiconductor device 2 further includes a compensation portion 30 disposed in the groove 230, the compensation portion 30 at least includes a conductive portion 33, and the conductive portion 33 is connected to the first electrode 24A, so that the width of the first electrode 24A is increased, the channel (channel) length of the thin film transistor 20A is reduced, the on-state current is increased, and the power consumption of the semiconductor device 2 is reduced; in addition, the conductive portion 33 is insulated from the second electrode 24B, so that the first electrode 24A is prevented from being electrically connected to the second electrode 24B, thereby preventing the electrical characteristics of the thin film transistor 20A from being affected.

Further, the first insulating layer 40 extends from a side of the first metal layer 24 away from the active layer 23 into the groove 230; wherein at least a portion of the first insulating layer 40 is located between the conductive portion 33 and the second electrode 24B.

Specifically, in the present embodiment, the first insulating layer 40 includes a first insulating portion 41 and a second insulating portion 42 connected to each other, and an orthographic projection of the first insulating portion 41 on the substrate covers an orthographic projection of the second electrode 24B on the substrate, thereby acting as a barrier to water and oxygen and insulation for the second electrode 24B; the second insulator portion 42 is located in the groove 230, and the second insulator portion 42 is disposed between the compensation portion 30 and the second electrode 24B, so that the conductive portion 33 is insulated from the second electrode 24B, and the first electrode 24A is prevented from being electrically connected to the second electrode 24B, thereby affecting the electrical characteristics of the thin film transistor 20A.

The present embodiment further provides a method for manufacturing a semiconductor device, please refer to fig. 2, fig. 3, and fig. 6, fig. 7A to fig. 7G; fig. 6 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure; fig. 7A to 7G are process flow diagrams of the structure of the semiconductor device in fig. 6.

In this embodiment, the method for manufacturing a semiconductor device includes the following steps:

step S100: an insulating substrate 10 is provided.

Wherein, when the insulating base 10 is a rigid substrate, the material may be metal or glass, and when the insulating base 10 is a flexible substrate, the material may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane-based resin, cellulose resin, silicone resin, polyimide-based resin, and polyamide-based resin.

Step S200: forming a thin-film transistor layer 20 on the insulating substrate 10, wherein the thin-film transistor layer 20 includes an active layer 23, and a first metal layer 24 on the active layer 23, the active layer 23 includes an active segment 23A and a conductor layer 231 that are stacked, the conductor layer 231 includes a first conductor segment 23B and a second conductor segment 23C that are spaced apart from each other on the active segment 23A, and the first metal layer 24 includes a first electrode 24A connected to the first conductor segment 23B and a second electrode 24B connected to the second conductor segment 23C; the active layer 23 includes a groove 230 between the first electrode 24A and the second electrode 24B, and the depth of the groove 230 is smaller than the thickness of the active layer 23 and larger than the thickness of the conductor layer 231.

The manufacturing method of the semiconductor device further comprises the following steps of:

step S300: a compensation portion 30 is formed on a side of the thin-film transistor layer 20 away from the insulating substrate 10, the compensation portion 30 is disposed in the groove 230, the compensation portion 30 at least includes a conductive portion 33, the conductive portion 33 is connected to one of the first electrode 24A and the second electrode 24B, and the conductive portion 33 is disposed in an insulating manner with the other of the first electrode 24A and the second electrode 24B.

Specifically, in this embodiment, in the step S200, the method for manufacturing a semiconductor device further includes the steps of:

step S201: forming a gate electrode 21 on the insulating substrate 10, as shown in fig. 7A; the material of the gate electrode 21 includes, but is not limited to, one or more alloys of molybdenum (Mo), titanium (Ti), and nickel (Ni).

Step S202: forming a gate insulating layer 22 on a side of the gate electrode 21 away from the insulating substrate 10, wherein the gate insulating layer 22 covers the gate electrode 21, thereby serving as a barrier to water and oxygen and an insulating function for the gate electrode 21, as shown in fig. 7B; wherein the material of the gate insulating layer 22 includes, but is not limited to, a single layer of silicon nitride (Si) ₃ N ₄ ) Single layer silicon dioxide (SiO) ₂ ) Single layer of silicon oxynitride (SiON) _x ) Or a double-layer structure of the above layers.

Step S203: an active layer 23 is formed on the side of the gate insulating layer 22 away from the gate electrode 21, and an orthographic projection of the gate electrode 21 on the insulating substrate 10 covers an orthographic projection of the active layer 23 on the insulating substrate 10.

Specifically, the step S203 includes the steps of:

step S2031: a first amorphous silicon (a-Si) layer is deposited on the gate insulating layer 22 and is subjected to a crystallization process to form a first polycrystalline silicon thin film.

Step S2032: the active segment 23A is formed by patterning the first polysilicon film.

Step S2033: a second amorphous silicon (a-Si) layer is deposited on the active segment 23A and is crystallized to form a second polycrystalline silicon thin film.

Step S2034: patterning the second polysilicon film to form a second polysilicon pattern, and performing ion implantation on the second polysilicon pattern to form a conductor layer 231, where the active layer 23 includes the active segment 23A and the conductor layer 231, which are stacked, as shown in fig. 7C; preferably, the conductor layer 231 is made of silicide polysilicon doped with n-type impurities at a high concentration.

Step S204: a third electrode 61 is formed on a side of the gate insulating layer 22 away from the gate electrode 21, an orthographic projection of the third electrode 61 on the insulating substrate 10 and the orthographic projection of the active layer 23 on the insulating substrate 10 do not overlap each other, and an orthographic projection of the third electrode 61 on the insulating substrate 10 and the orthographic projection of the gate electrode 21 on the insulating substrate 10 do not overlap each other, as shown in fig. 7D.

Step S205: forming a first metal layer 24 on a side of the active layer 23 away from the gate insulating layer 22, patterning the first metal layer 24 and the active layer 23 to form a trench 2300 passing through the first metal layer 24, the conductor layer 231 and a portion of the active segment 23A, wherein the trench 2300 includes a first opening (not labeled) passing through the first metal layer 24 and the recess 230 passing through the conductor layer 231 and a portion of the active segment 23A, and the first opening and the recess 230 are communicated with each other; wherein the first metal layer 24 forms the first electrode 24A and the second electrode 24B which are arranged at an interval, the conductor layer 231 forms the first conductor segment 23B and the second conductor segment 23C which are arranged at an interval, the first electrode 24A is connected with the first conductor segment 23B, the second electrode 24B is connected with the second conductor segment 23C, and the groove 230 is located between the first electrode 24A and the second electrode 24B, as shown in fig. 7E.

Specifically, an orthographic projection of the first electrode 24A on the insulating substrate 10 covers an orthographic projection of the first conductor segment 23B on the insulating substrate 10, and an orthographic projection of the second electrode 24B on the insulating substrate 10 covers an orthographic projection of the second conductor segment 23C on the insulating substrate 10.

Further, the second electrode 24B is connected to the third electrode 61, and an orthogonal projection of the third electrode 61 on the insulating substrate 10 at least coincides with an orthogonal projection of a portion of the second electrode 24B on the insulating substrate 10.

Step S206: away from the active layer at the first electrode 24A23, a first insulating layer 40 is formed on one side of the first electrode 24A, and the first insulating layer 40 extends from the side of the first electrode 24A far away from the active layer 23 into the groove 230, as shown in fig. 7F; wherein the material of the first insulating layer 40 includes, but is not limited to, a single layer of silicon nitride (Si) ₃ N ₄ ) Single layer of silicon dioxide (SiO) ₂ ) Single layer of silicon oxynitride (SiON) _x ) Or a double-layer structure of the above layers.

Further, in this embodiment, in the step S300, the method for manufacturing the semiconductor device further includes the steps of:

step S301: a compensation portion 30 is formed on a side of the thin-film transistor layer 20 away from the insulating substrate 10, the compensation portion 30 is disposed in the groove 230, the compensation portion 30 includes a first compensation sub-portion 31, a second compensation sub-portion 32 and the conductive portion 33, which are stacked on the active section 23A, wherein the conductive portion 33 is connected to the second electrode 24B, and the conductive portion 33 is insulated from the first electrode 24A, as shown in fig. 7G.

Specifically, the thickness of the compensation portion 30 is equal to the depth of the trench 2300, the side of the first compensation sub-portion 31 away from the insulating substrate 10 is flush with the side of the active segment 23A away from the insulating substrate 10, the side of the second compensation sub-portion 32 away from the insulating substrate 10 is flush with the side of the conductor layer 231 away from the insulating substrate 10, the side of the conductive portion 33 away from the insulating substrate 10 is flush with the side of the first metal layer 24 away from the insulating substrate 10, the orthographic projection of the conductive portion 33 on the insulating substrate 10 overlaps the orthographic projection of the second compensation sub-portion 32 on the insulating substrate 10, and the orthographic projection of the second compensation sub-portion 32 on the insulating substrate 10 overlaps the orthographic projection of the first compensation sub-portion 31 on the insulating substrate 10, so as to maintain the flatness of the thin film transistor 20A.

Further, the material of the first compensation sub-section 31 is the same as that of the active segment 23A, the material of the second compensation sub-section 32 is the same as that of the conductor layer 231, and the material of the conductive section 33 is the same as that of the first metal layer 24, so as to maintain the electrical characteristics of the thin film transistor 20A.

The second insulator portion 42 is disposed between the compensation portion 30 and the first electrode 24A, so that the conductive portion 33 is insulated from the first electrode 24A, and the second electrode 24B is prevented from being electrically connected to the first electrode 24A, thereby affecting the electrical characteristics of the thin film transistor 20A.

Specifically, in this embodiment, the method for manufacturing a semiconductor device further includes the following steps:

step S400: a second insulating layer 50 and a fourth electrode 62 are sequentially formed on a side of the first insulating layer 40 away from the first electrode 24A, wherein the second insulating layer 50 covers the interlayer insulating layer, the first insulating layer 40, the compensation portion 30, the second electrode 24B, and the third electrode 61, thereby functioning to block water and oxygen and insulate the layers, and the fourth electrode 62 is disposed corresponding to the third electrode 61, as shown in fig. 3.

It is understood that, in the present embodiment, the thin film transistor layer 20 includes a plurality of thin film transistors 20A arranged in a matrix, one thin film transistor 20A is located in one sub-pixel region, the thin film transistor 20A includes the gate electrode 21, the gate insulating layer 22, the active layer 23, the first electrode 24A and the second electrode 24B, which are stacked, and the channel of the thin film transistor 20A is located between the first conductor segment 23B and the second conductor segment 23C, that is, the length of the channel is equal to the width of the second insulator segment 42, so that the length of the channel can be determined by the width of the second insulator segment 42, and therefore, under the condition that the width of the channel is constant, the present embodiment can shorten the length of the channel by reducing the width of the second insulator segment 42, thereby enabling the thin film transistor 20A to have a larger aspect ratio, thereby having a larger on-state current, and reducing the power consumption of the thin film transistor 20A.

This embodiment provides an electronic device including the semiconductor device described in any of the above embodiments.

It is to be understood that the semiconductor device has been described in detail in the above embodiments, and the description is not repeated here.

When specifically applying, the electronic device can be a display screen of a smart phone, a tablet computer, a notebook computer, an intelligent bracelet, an intelligent watch, intelligent glasses, an intelligent helmet, a desktop computer, an intelligent television or a digital camera, and even can be applied to an electronic device with a flexible display screen.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.

The foregoing detailed description is directed to a semiconductor device and an electronic device provided in the embodiments of the present application, and specific examples are applied herein to explain the principles and implementations of the present application, and the description of the foregoing embodiments is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. A semiconductor device, comprising:

an insulating substrate:

thin-film transistor layer, set up in on the insulating substrate, thin-film transistor layer includes:

the active layer is arranged on the insulating substrate and comprises an active section and a conductor layer which are arranged in a stacked mode, and the conductor layer comprises a first conductor section and a second conductor section which are arranged on the active section at intervals;

the first metal layer is arranged on one side, away from the insulating substrate, of the active layer and comprises a first electrode connected with the first conductor section and a second electrode connected with the second conductor section;

wherein the active layer comprises a groove between the first electrode and the second electrode, the depth of the groove is smaller than the thickness of the active layer and larger than the thickness of the conductor layer;

the semiconductor device further comprises a compensation part arranged in the groove, the compensation part at least comprises a conductive part, the conductive part is connected with one of the first electrode and the second electrode, and the conductive part is insulated from the other one of the first electrode and the second electrode.

2. The semiconductor device of claim 1, wherein the compensation portion comprises a first compensation subsection and a second compensation subsection located between the conductive portion and the active segment, a sum of a thickness of the first compensation subsection and a thickness of the second compensation subsection being less than or equal to a depth of the recess, the conductive portion extending from the second compensation subsection in a direction away from the recess.

3. The semiconductor device according to claim 2, wherein an orthogonal projection of the conductive portion on the insulating substrate overlaps an orthogonal projection of the second compensating sub-portion on the insulating substrate, and an orthogonal projection of the second compensating sub-portion on the insulating substrate overlaps an orthogonal projection of the first compensating sub-portion on the insulating substrate.

4. The semiconductor device as claimed in claim 2, wherein the material of the first compensation sub-section is the same as the material of the active segment, the material of the second compensation sub-section is the same as the material of the conductor layer, and the material of the conductive portion is the same as the material of the first metal layer.

5. The semiconductor device of claim 1, wherein the compensation portion includes a first compensation subsection and a second compensation subsection located between the conductive portion and the active segment, a sum of a thickness of the first compensation subsection and a thickness of the second compensation subsection being equal to a depth of the recess, the second compensation subsection being located between the first compensation subsection and the conductive portion;

the side of the first compensation sub-portion, which is far away from the insulation substrate, is flush with the side of the active section, which is far away from the insulation substrate, the side of the second compensation sub-portion, which is far away from the insulation substrate, is flush with the side of the conductor layer, which is far away from the insulation substrate, and the side of the conductive portion, which is far away from the insulation substrate, is flush with the side of the first metal layer, which is far away from the insulation substrate.

6. The semiconductor device according to claim 1, further comprising a first insulating layer on a side of the first metal layer remote from the active layer, the first insulating layer extending from the side of the first metal layer remote from the active layer into the groove;

wherein at least a portion of the first insulating layer is located between the conductive portion and the first electrode, or at least a portion of the first insulating layer is located between the conductive portion and the second electrode.

7. The semiconductor device according to claim 6, wherein the conductive portion is connected to the first electrode;

the first insulating layer includes a first insulating sub-portion and a second insulating sub-portion connected to each other, an orthogonal projection of the first insulating sub-portion on the substrate covers an orthogonal projection of the second electrode on the substrate, the second insulating sub-portion is located in the groove, and the second insulating sub-portion is disposed between the compensation portion and the second electrode.

8. The semiconductor device according to claim 6, wherein the conductive portion is connected to the second electrode;

the first insulating layer includes a first insulating sub-portion and a second insulating sub-portion connected to each other, an orthographic projection of the first insulating sub-portion on the substrate covers an orthographic projection of the first electrode on the substrate, the second insulating sub-portion is located in the groove, and the second insulating sub-portion is disposed between the compensation portion and the first electrode.

9. The semiconductor device according to claim 1, wherein the thin film transistor layer comprises a gate electrode, a gate insulating layer, the active layer, the first electrode, and the second electrode, which are sequentially stacked;

wherein the first electrode covers the first conductor segment, the second electrode covers the second conductor segment, and an orthographic projection of the gate electrode on the insulating substrate covers an orthographic projection of the active layer on the insulating substrate.

10. An electronic device characterized in that it comprises a semiconductor device according to any one of claims 1 to 9.

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