CN115799053A - High-energy ion implantation method and semiconductor device - Google Patents
High-energy ion implantation method and semiconductor device Download PDFInfo
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 21
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- 229920005591 polysilicon Polymers 0.000 claims description 6
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 4
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- BMYNFMYTOJXKLE-UHFFFAOYSA-N 3-azaniumyl-2-hydroxypropanoate Chemical compound NCC(O)C(O)=O BMYNFMYTOJXKLE-UHFFFAOYSA-N 0.000 claims description 3
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
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Abstract
The application provides a high-energy ion implantation method and a semiconductor device, and relates to the technical field of semiconductors. Firstly, providing an epitaxial layer, and sequentially manufacturing a protective layer, a first mask layer and a second mask layer based on the epitaxial layer; the manufacturing materials of the first mask layer, the protection layer and the second mask layer are different, the thicknesses of the first mask layer and the second mask layer are larger than that of the protection layer, and then the second mask layer and the first mask layer are sequentially etched to form an injection groove; and finally, performing high-energy ion implantation on the epitaxial layer based on the implantation groove. The high-energy ion implantation method and the semiconductor device have the advantage of improving the uniformity of the trench oxide layer.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a high-energy ion implantation method and a semiconductor device.
Background
At present, with the rapid development and application of the third generation semiconductor industry, silicon carbide power semiconductor devices are rapidly widely applied to industry and vehicles. For the doping concentration and depth of different regions formed by the high-energy ion implantation process of the semiconductor device, the accuracy and reliability of the high-energy ion implantation are particularly critical.
In the prior art, when ion implantation is performed, a hard mask film is used and photoetching dry etching is used to form a hard mask groove region capable of high-energy ion implantation, the region can be used for high-energy ion implantation to the epitaxy of a substrate, and the rest regions are blocked by the hard mask film.
The depth control of the hard mask groove area made by photoetching and utilizing the upper hard mask film is not good, so that the high-energy ion implantation in the device is not uniform, and the electrical property uniformity in the chip is influenced.
In summary, the prior art has the problem of non-uniform high-energy ion implantation.
Disclosure of Invention
The present application provides a high-energy ion implantation method and a semiconductor device, so as to solve the problem of non-uniform high-energy ion implantation in the prior art.
In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:
in a first aspect, an embodiment of the present application provides a method for high-energy ion implantation, where the method includes:
providing an epitaxial layer;
sequentially manufacturing a protective layer, a first mask layer and a second mask layer on the basis of the epitaxial layer; the first mask layer, the protection layer and the second mask layer are made of different materials, and the thickness of the first mask layer and the thickness of the second mask layer are larger than that of the protection layer;
etching the second mask layer and the first mask layer in sequence to form an injection groove; wherein the injection groove exposes the surface of the protective layer;
and performing high-energy ion implantation on the epitaxial layer based on the implantation groove.
Optionally, the step of sequentially manufacturing the protection layer, the first mask layer and the second mask layer based on the epitaxial layer includes:
manufacturing a protective layer of 700-1500A along the epitaxial layer;
manufacturing a first mask layer from 12000 to 17000A along one side, far away from the epitaxial layer, of the protective layer;
and manufacturing a 4000 to 6000A second mask layer along one side, far away from the protective layer, of the first mask layer.
Optionally, the step of sequentially manufacturing the protection layer, the first mask layer and the second mask layer based on the epitaxial layer includes:
and sequentially manufacturing a first TEOS layer, an undoped polysilicon layer and a second TEOS layer based on the epitaxial layer.
Optionally, the step of sequentially manufacturing the protection layer, the first mask layer, and the second mask layer based on the epitaxial layer includes:
and sequentially manufacturing a first TEOS layer, an undoped polysilicon layer and a silicon nitride layer based on the epitaxial layer.
Optionally, the step of sequentially etching the second mask layer and the first mask layer includes:
coating photoresist along the surface of the second mask layer;
carrying out patterning treatment on the photoresist and forming a groove;
etching the second mask layer based on the photoresist, and forming a groove exposing the first mask layer on the second mask layer;
and etching the first mask layer by using the second mask layer as a hard mask to form an injection groove.
Optionally, the step of etching the second mask layer based on the photoresist includes:
and etching the second mask layer by using a dry process or a wet process.
Optionally, after the step of etching the second mask layer based on the photoresist, the method further includes:
and removing the photoresist.
Optionally, the step of etching the first mask layer by using the second mask layer as a hard mask includes:
and etching the first mask layer in a chlorine and hydrobromic acid environment.
Optionally, before the step of performing high-energy ion implantation on the epitaxial layer based on the implantation trench, the method further includes:
and cleaning the epitaxial layer by using sulfuric acid and hydrogen peroxide solution.
On the other hand, an embodiment of the present application further provides a semiconductor device, which is manufactured by the above-mentioned high-energy ion implantation method, and the semiconductor device includes:
an epitaxial layer;
the protective layer, the first mask layer and the second mask layer are positioned on one side of the epitaxial layer and are arranged layer by layer; the first mask layer, the protection layer and the second mask layer are made of different materials, and the thickness of the first mask layer and the thickness of the second mask layer are larger than that of the protection layer;
the injection grooves are positioned in the first mask layer and the second mask layer, and the injection grooves expose the surface of the protection layer;
and an ion implantation area is arranged at the position of the epitaxial layer opposite to the implantation groove.
Compared with the prior art, the method has the following beneficial effects:
the application provides a high-energy ion implantation method and a semiconductor device, wherein an epitaxial layer is provided, and then a protective layer, a first mask layer and a second mask layer are sequentially manufactured on the basis of the epitaxial layer; the manufacturing materials of the first mask layer, the protection layer and the second mask layer are different, the thicknesses of the first mask layer and the second mask layer are larger than that of the protection layer, and then the second mask layer and the first mask layer are sequentially etched to form an injection groove; and finally, performing high-energy ion implantation on the epitaxial layer based on the implantation groove. On one hand, the high-energy ion implantation is realized by arranging the three-layer structure, so that the implantation can be more accurate; on the other hand, in the high-energy ion implantation, the ion implantation is not directly performed from the surface of the epitaxial layer, but performed through the protective action of a protective layer, so that the implantation uniformity is higher.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic cross-sectional view of a hard mask for ion implantation in the prior art.
Fig. 2 is a schematic cross-sectional view illustrating a prior art after ion implantation.
Fig. 3 is an exemplary flowchart of a method for high-energy ion implantation according to an embodiment of the present disclosure.
Fig. 4 is a schematic cross-sectional view of a three-layer structure deposited on the surface of an epitaxial layer according to an embodiment of the present disclosure.
Fig. 5 is a schematic cross-sectional view of a photoresist patterned according to an embodiment of the present disclosure.
Fig. 6 is a schematic cross-sectional view of the second mask layer after etching according to the embodiment of the present disclosure.
Fig. 7 is a schematic cross-sectional view of the first mask layer after etching according to the embodiment of the present disclosure.
Fig. 8 is a schematic cross-sectional view illustrating a high-energy ion implantation process according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, as generally described and illustrated in the figures herein, could be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
Ion implantation is a phenomenon that ion beams are resisted by a solid material and then slowly reduced to finally stay in the solid material after being injected into the solid material, and is widely applied to the field of semiconductors at present.
As described in the background, currently, when high-energy ion implantation is performed, ion implantation is generally performed by using a hard mask. For example, referring to fig. 1 and 2, in the prior art, a hard mask of a material such as silicon dioxide is first deposited on an epitaxial layer. And finally, etching the hard mask to form a groove on the hard mask. Next, as shown in fig. 1, ion implantation is performed from top to bottom, and due to the blocking effect of the hard mask, ion implantation cannot be performed on the epitaxial layer in the region where the hard mask exists, and ion implantation can be performed only in the trench region, so that an ion implantation region is formed in the epitaxial layer in the region corresponding to the trench, as shown in fig. 2.
However, in a high-energy ion implantation scenario, since energy during ion implantation is high, on one hand, the thickness of the hard mask is required to be thick, etching of the hard mask is conventionally achieved by using photoresist, and for a thick hard mask, complete etching effect cannot be achieved by using the photoresist, so that the thickness of the hard mask is limited, and during ion implantation, ions may pass through the hard mask and reach the epitaxial layer, which results in unreliable ion implantation of the epitaxial layer. On the other hand, since the energy at the time of ion implantation is high, the implanted ions may be distributed not only in the ion implantation region but also in the remaining region in the epitaxial layer, resulting in uneven ion implantation.
In view of the above, in order to solve the above problem, embodiments of the present application provide a high energy ion implantation method, which is exemplarily described as follows:
as an implementation, please refer to fig. 3, the method includes:
s102, providing an epitaxial layer.
S104, sequentially manufacturing a protective layer, a first mask layer and a second mask layer based on the epitaxial layer; the first mask layer, the protection layer and the second mask layer are made of different materials, and the thickness of the first mask layer and the thickness of the second mask layer are larger than that of the protection layer.
S106, etching the second mask layer and the first mask layer in sequence to form an injection groove; wherein the implantation trench exposes a surface of the protection layer.
And S108, performing high-energy ion implantation on the epitaxial layer based on the implantation groove.
High-energy ion injection is realized by arranging the three-layer structure, so that the injection is more accurate. In addition, during high-energy ion implantation, the ion implantation is not directly performed from the surface of the epitaxial layer, but performed through the protection effect of the protective layer, so that the implantation uniformity is higher.
The epitaxial layer may be a silicon carbide epitaxial layer, and certainly, a substrate is further disposed on a bottom surface of the epitaxial layer, which is not described herein again.
In the present application, the methods of manufacturing the protection layer, the first mask layer, and the second mask layer may all adopt a deposition method, and as shown in fig. 4, the protection layer may be deposited on the surface of the epitaxial layer first, then the first mask layer may be deposited along one side of the principle epitaxial layer of the protection layer, and the second mask layer may be deposited along the surface of the first mask layer, which is far away from the epitaxial layer.
In a specific implementation, the deposition of the protection layer is implemented by a CVD process (Chemical vapor deposition process), the fabrication of the first mask layer is implemented by a DIFF process (diffusion), and the deposition of the second mask layer is implemented by a CVD process.
In one implementation, the protective layer and the second mask layer may be made of the same material, for example, the protective layer may be a first TEOS layer, the first mask layer may be an undoped polysilicon layer, and the second mask layer may be a second TEOS layer. In another implementation, the material of the protection layer and the second mask layer may also be different, for example, the protection layer may be a first TEOS layer, and the second mask layer may be a silicon nitride layer.
The material of the first TEOS layer and the second TEOS layer may be orthosilicate, or silicon dioxide, which is not limited herein.
In addition, in the manufacturing process, the thickness of the protection layer to be protected is relatively thin, the thicknesses of the first mask layer and the second mask layer are relatively thick, and the thickness of the first mask layer is the thickest, optionally, the thickness of the protection layer may be 700 to 1500a, the thickness of the first mask layer may be 12000 to 17000a, and the thickness of the second mask layer may be 4000 to 6000a. Illustratively, the protective layer has a thickness of 1000A, the first mask layer has a thickness of 15000A, and the second mask layer has a thickness of 5000A.
Through the arrangement mode, the protective effect during ion implantation can be realized by utilizing the thin first TEOS layer, and meanwhile, the undoped polysilicon layer and the second TEOS layer are used as masks, so that the thickness is large, and high-energy ion implantation is effectively realized.
Specifically, when the protective layer is manufactured, a TEOS liquid source is used, stress is-200 MPa, the refractive index is 1.46 (+ -0.02), the particle Adder is less than or equal to 150ea, and the particle size is more than or equal to 0.3um.
The basic process conditions were 25% SiH4 (diluted by He or Ar) 40 cm 3 /min， N 2 O:270 cm 3 / min，He :250 cm 3 The power is 160W, the temperature is 270 ℃, and the pressure is 106 Pa;
or, the basic process conditions are that TEOS (heated at 40 deg.C by HOTBOX transport system) is 170sccm and O is carried into the cavity by He or Ar gas 2 460sccm, 375W power, 430 ℃ temperature, 930 Pa pressure. Or the power is 375W, the temperature is 380-420 ℃, the pressure is 930 Pa (7T-8.5T), TEOS (the temperature for gasifying the TEOS liquid is 80-120 ℃, the liquid flow is 500mgm-1500 mgm, N2 or He:1000 sccm), O 2 2000sccm to 4500sccm. Or power 375W, temperature 380-420 deg.C, pressure 930 Pa (7T-8.5T), TEOS (the temperature of the bubbler for vaporizing TEOS liquid is always 65 deg.C, N2 or He:1000 sccm), 20-110sccm, O 2 :160sccm。
After the protective layer is made, the whole epitaxial layer can be cleaned, and then a first mask layer is made, wherein the first mask layer can be made at the temperature of 630-645 ℃ and the pressure of 0.25-0.3 torr, siH4 (He) of 3000-5000 sccm (pure SiH 4: 280-360 sccm, N is 2 2000 sccm).
When the second mask layer is manufactured, the process conditions same as those of the protective layer can be adopted, and the thickness is far larger than that of the protective layer.
After the manufacturing is completed, the first mask layer and the second mask layer need to be etched, and the method comprises the following steps:
and S1061, coating photoresist along the surface of the second mask layer.
And S1062, performing patterning treatment on the photoresist, and forming a groove.
S1063, etching the second mask layer based on the photoresist, and forming a trench exposing the first mask layer on the second mask layer.
And S1064, etching the first mask layer by using the second mask layer as a hard mask to form an injection groove.
The photoresist is spin-coated on the mask layer, and is subjected to patterning treatment in a mask plate and ultraviolet light mode to form the structure shown in fig. 5, wherein a groove is formed in the photoresist layer, and the groove exposes the surface of the second mask layer.
And etching the mask layer based on the photoresist, for example, completing etching of the second mask layer by using a wet etching process, further etching a trench at a corresponding position of the second mask layer based on the pattern of the photoresist, and removing the photoresist, as shown in fig. 6.
Wherein, when dry etching is adopted, CF may be adopted 4 Etching the second mask layer with chlorine; for example, the second mask layer is etched under the environment of Pressure 40mT/Source power 800W/Bias power 200W/CF4 100sccm/CHF3 50sccm/Ar 20sccm/Temp 25 ℃/Time 2.5min, and when wet etching is adopted, the second mask layer can be etched in a memorial manner by using sulfuric acid + hydrogen peroxide solution.
It should be noted that, since the thickness of the second mask layer is relatively thin, the second mask layer can be etched by directly using the photoresist. In removing the photoresist, O may be utilized 2 Removing the photoresist, e.g., pressure1000 mT/power 900W/O 2 And removing the photoresist in the environment of 300sccm/Temp 85 ℃/Time 5min.
After removing the photoresist, the whole epitaxial layer needs to be cleaned and the CD (width) of the trench in the second mask layer is measured, for example, the CD of the trench of the second mask layer may be 1.2 ± 0.12um.
And then, etching the first mask layer by using the second mask layer, wherein the second mask layer is made of a TEOS material or a silicon nitride material, so that when the second mask layer is used as a mask, the first mask layer with a larger depth can be etched, an injection groove is formed in the first mask layer, the injection groove exposes the surface of the protection layer, and the etched structure is as shown in fig. 7.
The etching of the first mask layer can be performed in a chlorine and hydrobromic acid environment, for example, the etching condition can be Pressure 20mT/Source power 600W/Bias power 200W/Cl2 100sccm/HBr 40sccm/Temp 20 ℃/Time 7.5min.
As an implementation manner, after the second mask layer is completely etched, the entire epitaxial layer may be cleaned, for example, the epitaxial layer is cleaned by using a solution of sulfuric acid and hydrogen peroxide, or of course, the epitaxial layer may be cleaned in other manners, for example, by using NH 4 And cleaning the epitaxial layer by using OH + hydrogen peroxide and aqueous solution. Then, a high-energy ion implantation process is performed, and an ion implantation region is formed in the position of the epitaxial layer opposite to the implantation trench, as shown in fig. 8.
It should be noted that, when ion implantation is performed, ions need to pass through the protective layer to enter the epitaxial layer, and therefore, the protective layer can play a certain buffering role, and on the basis, the uniformity of ion implantation is improved. And, because the position in non-ion implantation district is provided with first mask layer, and first mask layer adopts undoped polycrystalline silicon, and simultaneously, the thickness of first mask layer is great, consequently, the difficult condition that appears the ion and pass first mask layer during ion implantation, and then avoided the ion to pour into in other regions of epitaxial layer, promoted ion implantation's accuracy. In addition, the first mask layer, the second mask layer and the protective layer can play a role in blocking ion implantation, so that the implantation accuracy is further improved.
After the ion implantation is completed, all the level structures on the epitaxial layer may be removed, that is, the protection layer, the first mask layer, and the second mask layer are removed, which is not described herein again.
The working principle of the high-energy ion implantation method provided by the application is as follows:
and forming a hard mask groove area capable of injecting high-energy ions by utilizing three layers of different hard mask films and matching with different thicknesses and utilizing photoetching dry etching, wherein the area can inject the high-energy ions into the extension of the substrate, and the rest areas are blocked by the hard mask films. And then improve accuracy and reliability to the doping depth that semiconductor device high energy ion implantation technology formed different regions, utilize first TEOS as the epitaxial protective layer when high energy ion is implanted simultaneously, it is more even to pour into, and avoids among the implantation process, the epitaxial layer appears damaging.
Based on the foregoing implementation, an embodiment of the present application further provides a semiconductor device fabricated by the foregoing high-energy ion implantation method, and referring to fig. 8, the semiconductor device includes:
an epitaxial layer; the protective layer, the first mask layer and the second mask layer are positioned on one side of the epitaxial layer and arranged layer by layer; the first mask layer, the protection layer and the second mask layer are made of different materials, and the thickness of the first mask layer and the thickness of the second mask layer are larger than that of the protection layer; the injection grooves are positioned in the first mask layer and the second mask layer, and the injection grooves expose the surface of the protection layer; and an ion implantation area is arranged at the position of the epitaxial layer opposite to the implantation groove.
In summary, the present application provides a high-energy ion implantation method and a semiconductor device, first providing an epitaxial layer, and then sequentially fabricating a protection layer, a first mask layer and a second mask layer based on the epitaxial layer; the manufacturing materials of the first mask layer, the protection layer and the second mask layer are different, the thicknesses of the first mask layer and the second mask layer are larger than that of the protection layer, and then the second mask layer and the first mask layer are sequentially etched to form an injection groove; and finally, performing high-energy ion implantation on the epitaxial layer based on the implantation groove. On one hand, the high-energy ion implantation is realized by arranging the three-layer structure, so that the implantation can be more accurate; on the other hand, during high-energy ion implantation, the ion implantation is not directly performed from the surface of the epitaxial layer, but performed through the protection effect of the protective layer, so that the implantation uniformity is higher.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (10)
1. A method of high energy ion implantation, the method comprising:
providing an epitaxial layer;
sequentially manufacturing a protection layer, a first mask layer and a second mask layer on the basis of the epitaxial layer; the first mask layer, the protection layer and the second mask layer are made of different materials, and the thickness of the first mask layer and the thickness of the second mask layer are larger than that of the protection layer;
etching the second mask layer and the first mask layer in sequence to form an injection groove; wherein the implantation trench exposes a surface of the protection layer;
and performing high-energy ion implantation on the epitaxial layer based on the implantation groove.
2. The method of claim 1, wherein the step of sequentially forming a protective layer, a first mask layer, and a second mask layer on the epitaxial layer comprises:
manufacturing a protective layer of 700-1500A along the epitaxial layer;
manufacturing a first mask layer of 12000 to 17000A along one side of the protective layer, which is far away from the epitaxial layer;
and manufacturing a 4000 to 6000A second mask layer along one side of the first mask layer, which is far away from the protective layer.
3. The method of claim 1, wherein the step of sequentially forming a protective layer, a first mask layer, and a second mask layer on the epitaxial layer comprises:
and sequentially manufacturing a first TEOS layer, an undoped polysilicon layer and a second TEOS layer based on the epitaxial layer.
4. The method of claim 1, wherein the step of sequentially forming a protective layer, a first mask layer, and a second mask layer on the epitaxial layer comprises:
and sequentially manufacturing a first TEOS layer, an undoped polysilicon layer and a silicon nitride layer based on the epitaxial layer.
5. The method of claim 1, wherein the step of sequentially etching the second mask layer and the first mask layer comprises:
coating photoresist along the surface of the second mask layer;
carrying out patterning treatment on the photoresist, and forming a groove;
etching the second mask layer based on the photoresist, and forming a groove exposing the first mask layer on the second mask layer;
and etching the first mask layer by using the second mask layer as a hard mask to form an injection groove.
6. The method of claim 5, wherein etching the second mask layer based on the photoresist comprises:
and etching the second mask layer by using a dry process or a wet process.
7. The method of high energy ion implantation according to claim 5, wherein after the step of etching the second mask layer based on the photoresist, the method further comprises:
and removing the photoresist.
8. The method of claim 5, wherein the step of etching the first mask layer using the second mask layer as a hard mask comprises:
and etching the first mask layer in a chlorine and hydrobromic acid environment.
9. The method of high energy ion implantation according to claim 1, wherein prior to the step of high energy ion implanting the epitaxial layer based on the implantation trench, the method further comprises:
and cleaning the epitaxial layer by using sulfuric acid and hydrogen peroxide solution.
10. A semiconductor device fabricated by the high-energy ion implantation method as claimed in any one of claims 1 to 9, the semiconductor device comprising:
an epitaxial layer;
the protective layer, the first mask layer and the second mask layer are positioned on one side of the epitaxial layer and are arranged layer by layer; the first mask layer, the protection layer and the second mask layer are made of different materials, and the thickness of the first mask layer and the thickness of the second mask layer are larger than that of the protection layer;
the injection grooves are positioned in the first mask layer and the second mask layer, and the injection grooves expose the surface of the protection layer;
and an ion implantation area is arranged at the position of the epitaxial layer opposite to the implantation groove.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56138920A (en) * | 1980-03-31 | 1981-10-29 | Fujitsu Ltd | Method of selection and diffusion for impurities |
| CN102496559A (en) * | 2011-11-25 | 2012-06-13 | 中国科学院微电子研究所 | Three-layer composite ion implantation barrier layer and preparation and removal method thereof |
| CN103606551A (en) * | 2013-10-18 | 2014-02-26 | 泰科天润半导体科技（北京）有限公司 | Silicon carbide channel-type semiconductor device and manufacturing method thereof |
| CN104882369A (en) * | 2014-02-28 | 2015-09-02 | 株洲南车时代电气股份有限公司 | Silicon carbide ion implantation doped mask structure and preparation method thereof |
| CN113270482A (en) * | 2021-05-20 | 2021-08-17 | 厦门市三安集成电路有限公司 | Preparation method of MOSFET device |
| CN113394085A (en) * | 2021-06-11 | 2021-09-14 | 武汉新芯集成电路制造有限公司 | Ion implantation method |
| CN113488492A (en) * | 2021-06-09 | 2021-10-08 | 华虹半导体(无锡)有限公司 | Ion implantation method for small-sized CIS device |
| WO2021227731A1 (en) * | 2020-05-12 | 2021-11-18 | 长鑫存储技术有限公司 | Manufacturing method for buried word line structure, and semiconductor memory comprising buried word line structure |
-
2023
- 2023-02-08 CN CN202310079397.7A patent/CN115799053A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56138920A (en) * | 1980-03-31 | 1981-10-29 | Fujitsu Ltd | Method of selection and diffusion for impurities |
| CN102496559A (en) * | 2011-11-25 | 2012-06-13 | 中国科学院微电子研究所 | Three-layer composite ion implantation barrier layer and preparation and removal method thereof |
| CN103606551A (en) * | 2013-10-18 | 2014-02-26 | 泰科天润半导体科技（北京）有限公司 | Silicon carbide channel-type semiconductor device and manufacturing method thereof |
| CN104882369A (en) * | 2014-02-28 | 2015-09-02 | 株洲南车时代电气股份有限公司 | Silicon carbide ion implantation doped mask structure and preparation method thereof |
| WO2021227731A1 (en) * | 2020-05-12 | 2021-11-18 | 长鑫存储技术有限公司 | Manufacturing method for buried word line structure, and semiconductor memory comprising buried word line structure |
| CN113270482A (en) * | 2021-05-20 | 2021-08-17 | 厦门市三安集成电路有限公司 | Preparation method of MOSFET device |
| CN113488492A (en) * | 2021-06-09 | 2021-10-08 | 华虹半导体(无锡)有限公司 | Ion implantation method for small-sized CIS device |
| CN113394085A (en) * | 2021-06-11 | 2021-09-14 | 武汉新芯集成电路制造有限公司 | Ion implantation method |
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