CN115799051A - Semiconductor structure, method for forming same, and electronic component - Google Patents
Semiconductor structure, method for forming same, and electronic component Download PDFInfo
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- CN115799051A CN115799051A CN202211554659.2A CN202211554659A CN115799051A CN 115799051 A CN115799051 A CN 115799051A CN 202211554659 A CN202211554659 A CN 202211554659A CN 115799051 A CN115799051 A CN 115799051A
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Abstract
The invention discloses a semiconductor structure, a forming method thereof and an electronic component, wherein the forming method of the semiconductor structure comprises the following steps: providing a semiconductor substrate, and forming a mask layer comprising an SOG material layer, an SiON material layer and an SOC material layer on the surface of the semiconductor substrate; a photoresist layer is formed on a surface of the mask layer. According to the invention, the mask layer comprising the SOG material layer, the SiON material layer and the SOC material layer is added between the photoresist and the silicon wafer, the mask layer is etched by taking a layer of photoresist as the mask, the target pattern on the photoresist is transferred to the mask layer, and then the silicon wafer is etched by utilizing the etching resistance of the mask layer.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor structure, a method of forming the same, and an electronic component.
Background
Photolithography refers to a technique of transferring a pattern on a reticle onto a substrate by means of a photoresist (also called a photoresist) under the influence of light. The main process is as follows: firstly, irradiating ultraviolet light on the surface of a substrate attached with a layer of photoresist film through a mask plate to cause the photoresist in an exposure area to generate chemical reaction; dissolving and removing the photoresist in the exposed area or the unexposed area (the former is called positive photoresist and the latter is called negative photoresist) by a developing technology, so that the pattern on the mask is copied to the photoresist film; and finally, transferring the pattern to the substrate by using an etching technology.
Therefore, the photoresist is required to have high resolution and high corrosion resistance in the etching process, and when a 3 μm silicon wafer is etched, if the thickness of the photoresist is too small, the photoresist layer is easily excessively consumed in the subsequent silicon wafer etching process, so that the photoresist layer cannot have a blocking effect in the etching process, and the structural performance of a semiconductor is affected. In order to make the photoresist resist etching, the film thickness of the photoresist can be increased or the C content of the photoresist can be increased, but the above method can reduce the pattern resolution and cannot resolve smaller patterns, i.e. the etching resistance and the high resolution of the photoresist cannot meet the requirements at the same time.
Disclosure of Invention
The invention provides a semiconductor structure, a forming method thereof and an electronic component, aiming at the technical problem that the etching resistance and high resolution of the existing layer of photoresist cannot meet the requirement at the same time.
In a first aspect, an embodiment of the present application provides a method for forming a semiconductor structure, including:
s1: providing a semiconductor substrate;
s2: forming a mask layer comprising an SOG material layer, an SiON material layer and an SOC material layer on the surface of the semiconductor substrate;
s3: forming a photoresist layer on the surface of the mask layer;
s4: forming a target pattern on the photoresist layer through a photoetching process;
s5: etching the mask layer by taking the photoresist layer as a mask so as to transfer the target pattern to the mask layer;
s6: removing the photoresist layer;
s7: etching the semiconductor substrate by taking the mask layer as a mask, and etching the target pattern on the semiconductor substrate;
s8: and removing the mask layer after the target pattern is etched on the semiconductor substrate.
In the method for forming the semiconductor structure, the thickness of the photoresist layer is 1.2 μm to 5 μm.
In a second aspect, an embodiment of the present application provides a method for forming a semiconductor structure, including:
s1: a semiconductor substrate is provided, and a semiconductor substrate,
s2: forming a mask layer comprising an APF material layer and an SOC material layer on the surface of the semiconductor substrate;
s3: forming a photoresist layer on the surface of the mask layer;
s4: forming a target pattern on the photoresist layer through a photoetching process;
s5: etching the mask layer by taking the photoresist layer as a mask so as to transfer the target pattern to the mask layer;
s6: removing the photoresist layer;
s7: etching the semiconductor substrate by taking the mask layer as a mask, and etching the target pattern on the semiconductor substrate;
s8: and removing the mask layer after the target pattern is etched on the semiconductor substrate.
In the above method for forming a semiconductor structure, S2 includes:
s21: forming an APF material layer on the surface of the semiconductor substrate;
s22: and forming an SOC material layer on the surface of the APF material layer.
In the method for forming the semiconductor structure, the thickness of the photoresist layer is 1.2 μm to 5 μm.
In a third aspect, an embodiment of the present application provides a method for forming a semiconductor structure, including:
s1: a semiconductor substrate is provided, and a semiconductor substrate,
s2: forming a mask layer comprising an SOG material layer and an SOC material layer on the surface of the semiconductor substrate;
s3: forming a photoresist layer on the surface of the mask layer;
s4: forming a target pattern on the photoresist layer through a photoetching process;
s5: etching the mask layer by taking the photoresist layer as a mask so as to transfer the target pattern to the mask layer;
s6: removing the photoresist layer;
s7: etching the semiconductor substrate by taking the mask layer as a mask, and etching the target pattern on the semiconductor substrate;
s8: and removing the mask layer after the target pattern is etched on the semiconductor substrate.
In the above method for forming a semiconductor structure, the S2 includes:
s21: forming an SOG material layer on the surface of the semiconductor substrate;
s22: and forming an SOC material layer on the surface of the SOG material layer.
In the method for forming the semiconductor structure, the thickness of the photoresist layer is 1.2 μm to 5 μm.
In a fourth aspect, embodiments of the present application provide a semiconductor structure formed by the method for forming a semiconductor structure according to any one of the above aspects.
In a fifth aspect, an embodiment of the present application provides an electronic component, where the electronic component includes the semiconductor structure described in the fourth aspect.
Compared with the prior art, the invention has the advantages and positive effects that:
according to the method, the mask layer with etching resistance is additionally arranged between the photoresist and the silicon wafer, the photoresist with the thickness of 1.2-5 microns is used as the mask to etch the mask layer, the target graph on the photoresist is transferred to the mask layer, the etching resistance of the mask layer is utilized to etch the silicon wafer, the high resolution of the graph is kept in the process, and therefore the etching resistance is improved while the film thickness of the photoresist is not required to be increased.
Drawings
FIG. 1 is a cross-sectional view of a prior art semiconductor structure;
FIG. 2 is a schematic diagram of a step of a method for forming a semiconductor structure according to the present invention;
FIG. 3 is a schematic flow chart based on step S2 in FIG. 2 according to the present invention;
FIG. 4 is a cross-sectional view of a first semiconductor structure formed in response to the step of forming the semiconductor structure of FIG. 3 in accordance with the present invention;
FIG. 5 is a schematic diagram illustrating another step of a method for forming a semiconductor structure according to the present invention;
FIG. 6 is a cross-sectional view of a second semiconductor structure provided in accordance with the present invention;
FIG. 7 is a schematic diagram illustrating another step of a method for forming a semiconductor structure according to the present invention;
FIG. 8 is a schematic flow chart based on the step S2 in FIG. 6 according to the present invention;
FIG. 9 is a cross-sectional view of a third semiconductor structure formed in response to the step of forming the semiconductor structure of FIG. 7 in accordance with the present invention;
FIG. 10 is a schematic diagram illustrating another step of a method for forming a semiconductor structure according to the present invention;
FIG. 11 is a schematic flow chart based on step S2 in FIG. 9 according to the present invention;
FIG. 12 is a cross-sectional view of a fourth semiconductor structure formed corresponding to the step of forming the semiconductor structure of FIG. 10 in accordance with the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided in the present application without any inventive step are within the scope of protection of the present application.
It is obvious that the drawings in the following description are only examples or embodiments of the present application, and that it is also possible for a person skilled in the art to apply the present application to other similar contexts on the basis of these drawings without inventive effort. Moreover, it should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the specification. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of ordinary skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments without conflict.
Unless defined otherwise, technical or scientific terms referred to herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which this application belongs. The use of the terms "a" and "an" and "the" and similar referents in the context of describing the invention (including a single reference) are to be construed in a non-limiting sense as indicating either the singular or the plural. The present application is directed to the use of the terms "including," "comprising," "having," and any variations thereof, which are intended to cover non-exclusive inclusions; for example, a process, method, system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to only those steps or elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. Reference to "connected," "coupled," and the like in this application is not intended to be limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as referred to herein means two or more. "and/or" describes an association relationship of associated objects, meaning that three relationships may exist, for example, "A and/or B" may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. Reference herein to the terms "first," "second," "third," and the like, are merely to distinguish similar objects and do not denote a particular ordering for the objects.
The present invention is described in detail with reference to the embodiments shown in the drawings, but it should be understood that these embodiments are not intended to limit the present invention, and those skilled in the art should understand that functional, methodological, or structural equivalents or substitutions made by these embodiments are within the scope of the present invention.
As shown in fig. 1, when a silicon wafer with a thickness of 3 μm is etched by using a layer of iline photoresist, the thickness of the photoresist is 1.2 μm-5 μm, so in order to prevent the etching of the silicon wafer with a thickness of 3 μm, the etching resistance of the photoresist needs to be improved, but the etching resistance can be improved by increasing the thickness of the photoresist or increasing the C content of the photoresist, but the resolution is reduced by increasing the film thickness or increasing the C content, which results in insufficient pattern resolution and inability to resolve smaller patterns. In order to enable the etching resistance and the resolution of the photoresist to meet the requirements at the same time, the embodiment of the application provides a semiconductor structure, a forming method thereof and an electronic component.
Fig. 2 is a schematic diagram of a step of a method for forming a semiconductor structure according to the present invention, and as shown in fig. 2, this embodiment discloses a specific implementation of a method for forming a semiconductor structure (hereinafter referred to as "method").
Specifically, the method disclosed in the present embodiment mainly includes:
step S1: providing a semiconductor substrate;
step S2: forming a mask layer comprising an SOG material layer, an SiON material layer and an SOC material layer on the surface of the semiconductor substrate;
and step S3: forming a photoresist layer on the surface of the mask layer;
in a specific implementation, the semiconductor substrate has a thickness of 3 μm; the photoresist layer has a thickness of 1.2 to 5 μm. In this embodiment, the semiconductor substrate is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other semiconductor materials.
Further, as shown in fig. 3, step S2 includes:
step S21: forming an SOG material layer on the surface of the semiconductor substrate;
the SOG material layer is Spin On Glass (SOG), which has corrosion resistance and flatness and is a main local planarization technique in semiconductor manufacturing, and particularly, the SOG is formed by uniformly Coating a liquid solvent containing a dielectric material on the surface of a wafer in a spin Coating (spin Coating) manner to fill the holes in the recesses of the deposited dielectric layer. Thereafter, the solvent is removed by heat treatment, leaving a cured (Curing) dielectric material on the wafer surface that approximates silicon dioxide (SiO 2).
Step S22: forming a SiON material layer on the surface of the SOG material layer; among them, siON has very good corrosion resistance.
Step S23: and forming an SOC material layer on the surface of the SiON material layer. Among them, the SOC material layer refers to Spin-on carbon (SOC), which is one of SiARC materials, and has very good etching resistance and planarization function.
A cross-sectional view of a first semiconductor structure formed by the above steps is shown in fig. 4, wherein a photoresist layer may be formed on the SOC material layer by a process such as spin coating. In this embodiment, the SOC material layer provides a flat surface for the formation of the photoresist layer.
Furthermore, the forming sequence of the SOG material layer, the SiON material layer and the SOC material layer can be adjusted according to the actual situation;
optionally, step S2 may further include:
step S211: forming an SOC material layer on the surface of the semiconductor substrate;
step S212: forming a SiON material layer on the surface of the SOC material layer;
step S213: and forming an SOG material layer on the surface of the SiON material layer.
Optionally, step S2 may further include:
step S221: forming a SiON material layer on the surface of the semiconductor substrate;
step S222: forming an SOC material layer on the surface of the SiON material layer;
step S223: and forming an SOG material layer on the surface of the SOC material layer.
Optionally, step S2 may further include:
step S231: forming an SOG material layer on the surface of the semiconductor substrate;
step S232: forming an SOC material layer on the surface of the SOG material layer;
step S233: forming a SiON material layer on the surface of the SOC material layer.
Optionally, step S2 may further include:
step S241: forming a SiON material layer on the surface of the semiconductor substrate;
step S242: forming an SOG material layer on the surface of the SiON material layer;
step S243: and forming an SOC material layer on the surface of the SOG material layer.
Optionally, step S2 may further include:
step S251: forming an SOC material layer on the surface of the semiconductor substrate;
step S252: forming an SOG material layer on the surface of the SOC material layer;
step S253: and forming a SiON material layer on the surface of the SOG material layer.
In the embodiment, the three layers of anti-corrosion materials are added between the silicon substrate and the photoresist by utilizing the anti-corrosion properties of three materials of SOG, silicon oxynitride (SiON) and SOC and the planarization function of SOG and SOC, so that the thickness of the photoresist layer in the subsequent etching process is reduced, the thickness of the photoresist layer is kept between 1.2 mu m and 5 mu m, the pattern resolution is increased while the anti-corrosion property is enhanced, and the subsequent analysis of smaller patterns is facilitated.
And step S4: forming a target pattern on the photoresist layer through a photoetching process;
specifically, the photoresist layer may comprise, for example, a photosensitive material that undergoes a change in chemical properties when the photoresist layer is exposed to light, and a target pattern may be formed on the photoresist by exposure development.
Step S5: etching the mask layer by taking the photoresist layer as a mask so as to transfer the target pattern to the mask layer;
step S6: and removing the photoresist layer.
Specifically, a target pattern is etched in a mask layer which is not covered by a patterned photoresist layer by taking the patterned photoresist layer as the mask; during etching, a dry etching process and/or a wet etching process can be utilized, an anisotropic dry etching process is preferably used for etching, the longitudinal etching rate of the dry etching process is far greater than the transverse etching rate, quite accurate pattern conversion can be obtained in the process of patterning the mask layer, and the shape and the appearance of the mask layer can be accurately controlled; etching gases such as SF6, NF3, COS, cl2, HBr, fluorocarbon (CF 4, CHF 3) with small fluorocarbon ratio and the like, wherein the etching rate of the etching process is greater than the polymer deposition rate, and the verticality of the etched line is better. And then, after the mask layer is etched, removing the photoresist layer by using a method such as plasma ashing and the like.
Step S7: etching the semiconductor substrate by taking the mask layer as a mask, and etching the target pattern on the semiconductor substrate;
step S8: and removing the mask layer after the target pattern is etched on the semiconductor substrate.
Specifically, a patterned mask layer is used as a mask, and a groove of a target pattern is etched in a semiconductor substrate which is not covered by the mask layer. When etching the semiconductor substrate, the etching process may use the dry etching process and/or the wet etching process as described in step S4.
In an embodiment of the invention, referring to fig. 5, fig. 5 is a schematic view illustrating another step of the method for forming a semiconductor structure according to the invention; the method mainly comprises the following steps:
s1: a semiconductor substrate is provided, and a semiconductor substrate,
s2: forming a mask layer comprising an SOG material layer on the surface of the semiconductor substrate;
s3: forming a photoresist layer on the surface of the mask layer;
s4: forming a target pattern on the photoresist layer through a photoetching process;
s5: etching the mask layer by taking the photoresist layer as a mask so as to transfer the target pattern to the mask layer;
s6: removing the photoresist layer;
s7: etching the semiconductor substrate by taking the mask layer as a mask, and etching the target pattern on the semiconductor substrate;
s8: and removing the mask layer after the target pattern is etched on the semiconductor substrate.
The second semiconductor structure formed by the above steps is shown in fig. 6; in the present embodiment, the mask layer formed on the semiconductor substrate is an SOG material layer having corrosion resistance and planarization function, and the photoresist layer may be formed on the SOG material layer by a process such as spin coating. The SOC material layer provides a flat surface for the formation of the photoresist layer.
In an embodiment of the invention, referring to fig. 7, fig. 7 is a schematic view illustrating another step of the method for forming a semiconductor structure according to the invention; the method mainly comprises the following steps:
s1: a semiconductor substrate is provided, and a semiconductor substrate,
s2: forming a mask layer comprising an SOG material layer and an SOC material layer on the surface of the semiconductor substrate;
s3: forming a photoresist layer on the surface of the mask layer;
s4: forming a target pattern on the photoresist layer through a photoetching process;
s5: etching the mask layer by taking the photoresist layer as a mask so as to transfer the target pattern to the mask layer;
s6: removing the photoresist layer;
s7: etching the semiconductor substrate by taking the mask layer as a mask, and etching the target pattern on the semiconductor substrate;
s8: and removing the mask layer after the target pattern is etched on the semiconductor substrate.
Further, referring to fig. 8, a flow chart based on step S2 in fig. 7 provided for the embodiment of the present invention includes:
step S21: forming an SOG material layer on the surface of the semiconductor substrate;
step S22: and forming an SOC material layer on the surface of the SOG material layer.
The third semiconductor structure formed through the above steps is as shown in fig. 9, and optionally, the forming sequence of the SOG material layer and the SOC material layer may be adjusted according to actual conditions; the mask layer is composed of a SOG material layer with corrosion resistance and planarization function and an SOC material layer, and a photoresist layer can be formed on the SOC material layer through a process such as spin coating, and the SOC material layer provides a flat surface for the formation of the photoresist layer.
In an embodiment of the invention, referring to fig. 10, fig. 10 is a schematic view illustrating another step of the method for forming a semiconductor structure according to the invention; the method comprises the following steps:
s1: a semiconductor substrate is provided and a semiconductor layer is formed on the semiconductor substrate,
s2: forming a mask layer comprising an APF material layer and an SOC material layer on the surface of the semiconductor substrate;
s3: forming a photoresist layer on the surface of the mask layer;
s4: forming a target pattern on the photoresist layer through a photoetching process;
s5: etching the mask layer by taking the photoresist layer as a mask so as to transfer the target pattern to the mask layer;
s6: removing the photoresist layer;
s7: etching the semiconductor substrate by taking the mask layer as a mask, and etching the target pattern on the semiconductor substrate;
s8: and removing the mask layer after the target pattern is etched on the semiconductor substrate.
Further, with reference to fig. 11, a flowchart of another method for forming a semiconductor structure based on step S2 according to an embodiment of the present invention is shown, where the method includes:
s21: forming an APF material layer on the surface of the semiconductor substrate; the APF material layer includes an Advanced Patterning Film (APF) having a planarization function and high corrosion resistance.
S22: and forming an SOC material layer on the surface of the APF material layer.
As shown in fig. 12, the mask layer in this embodiment is composed of an APF material layer having corrosion resistance and planarization function and an SOC material layer on which a photoresist layer is formed by a process such as spin coating, and the SOC material layer provides a flat surface for forming the photoresist layer. Furthermore, the forming sequence of the APF material layer and the SOC material layer can be adjusted according to actual conditions;
optionally, step S2 may further include:
s211: forming an SOC material layer on the surface of the semiconductor substrate;
s212: and forming an APF material layer on the surface of the SOC material layer.
Embodiments of the present application further provide a semiconductor structure formed by using the method for forming a semiconductor structure according to any one of the above embodiments.
Correspondingly, the embodiment of the invention also provides an electronic component which comprises the semiconductor structure provided by any one of the embodiments.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method of forming a semiconductor structure, comprising:
s1: providing a semiconductor substrate;
s2: forming a mask layer comprising an SOG material layer, an SiON material layer and an SOC material layer on the surface of the semiconductor substrate;
s3: forming a photoresist layer on the surface of the mask layer;
s4: forming a target pattern on the photoresist layer through a photoetching process;
s5: etching the mask layer by taking the photoresist layer as a mask so as to transfer the target pattern to the mask layer;
s6: removing the photoresist layer;
s7: etching the semiconductor substrate by taking the mask layer as a mask, and etching the target pattern on the semiconductor substrate;
s8: and removing the mask layer after the target pattern is etched on the semiconductor substrate.
2. The method of claim 1, wherein the photoresist layer has a thickness of 1.2 μm to 5 μm.
3. A method of forming a semiconductor structure, comprising:
s1: a semiconductor substrate is provided and a semiconductor layer is formed on the semiconductor substrate,
s2: forming a mask layer comprising an APF material layer and an SOC material layer on the surface of the semiconductor substrate;
s3: forming a photoresist layer on the surface of the mask layer;
s4: forming a target pattern on the photoresist layer through a photoetching process;
s5: etching the mask layer by taking the photoresist layer as a mask so as to transfer the target pattern to the mask layer;
s6: removing the photoresist layer;
s7: etching the semiconductor substrate by taking the mask layer as a mask, and etching the target pattern on the semiconductor substrate;
s8: and removing the mask layer after the target pattern is etched on the semiconductor substrate.
4. The method for forming the semiconductor structure according to claim 3, wherein the S2 comprises:
s21: forming an APF material layer on the surface of the semiconductor substrate;
s22: and forming an SOC material layer on the surface of the APF material layer.
5. The method of claim 3, wherein the photoresist layer has a thickness of 1.2 μm to 5 μm.
6. A method of forming a semiconductor structure, comprising:
s1: a semiconductor substrate is provided, and a semiconductor substrate,
s2: forming a mask layer comprising an SOG material layer and an SOC material layer on the surface of the semiconductor substrate;
s3: forming a photoresist layer on the surface of the mask layer;
s4: forming a target pattern on the photoresist layer through a photoetching process;
s5: etching the mask layer by taking the photoresist layer as a mask so as to transfer the target pattern to the mask layer;
s6: removing the photoresist layer;
s7: etching the semiconductor substrate by taking the mask layer as a mask, and etching the target pattern on the semiconductor substrate;
s8: and removing the mask layer after the target pattern is etched on the semiconductor substrate.
7. The method for forming the semiconductor structure according to claim 6, wherein the S2 comprises:
s21: forming an SOG material layer on the surface of the semiconductor substrate;
s22: and forming an SOC material layer on the surface of the SOG material layer.
8. The method as claimed in claim 6, wherein the photoresist layer has a thickness of 1.2 μm to 5 μm.
9. A semiconductor structure formed by the method of forming a semiconductor structure of any of claims 1-8.
10. An electronic component, characterized in that the electronic component comprises the semiconductor structure of claim 9.
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