CN115796103A

CN115796103A - SRAM memory cell layout, design method, circuit, semiconductor structure and memory

Info

Publication number: CN115796103A
Application number: CN202111061849.6A
Authority: CN
Inventors: 李宗翰; 刘志拯
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-09-10
Filing date: 2021-09-10
Publication date: 2023-03-14
Also published as: WO2023035470A1

Abstract

The application provides a layout of an SRAM memory cell, a design method, a circuit, a semiconductor structure and a memory, wherein the layout comprises the following steps: a substrate; at least one active region extending in a first direction; at least one gate structure extending along a second direction; the second direction is perpendicular to the first direction; at least one contact structure; wherein the at least one contact structure connects two adjacent active regions of the at least one active region and the target gate structure; the target gate structure belongs to at least one gate structure; the projection of the target gate structure in the substrate intersects the projections of the other active regions in the at least one active region except for two adjacent active regions in the substrate. The method and the device can reduce the use of connecting wires, save the processing area and improve the integration level of the integrated circuit; meanwhile, the processing technology is simplified, and the risk of low yield is reduced.

Description

SRAM memory cell layout, design method, circuit, semiconductor structure and memory

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular, to a layout of an SRAM memory cell, a design method of the SRAM memory cell, a circuit of the SRAM memory cell, a semiconductor structure of the SRAM memory cell, and a memory of the SRAM memory cell.

Background

With the development of electronic technology, the performance requirements for integrated circuits are increasing. More electronic components need to be integrated in the same processing area to increase the integration level of the integrated circuit. Meanwhile, with the complicated structure of the integrated circuit, the processing technology is more complicated, and the risk of low yield is brought.

In an integrated circuit, connecting lines are used to conduct between semiconductor devices. In the process of arranging the connecting wires, a part of metal materials are required to be arranged more, and allowance space is reserved to avoid poor conduction. Thus, the processing area is additionally occupied, and the improvement of the integration level of the integrated circuit is not facilitated. Meanwhile, the process of arranging the connecting wires is complex, and the risk of low yield exists.

Disclosure of Invention

The embodiment of the application is expected to provide a layout and a design method of an SRAM (static random access memory) storage unit, a circuit, a semiconductor structure and a memory, which can reduce the use of connecting wires, save the processing area and improve the integration level of an integrated circuit; meanwhile, the processing technology is simplified, and the risk of low yield is reduced.

The technical scheme of the application is realized as follows:

the embodiment of the application provides a layout of an SRAM memory cell, wherein the layout comprises:

a substrate;

at least one active region extending in a first direction;

at least one gate structure extending along a second direction; the second direction is perpendicular to the first direction;

at least one contact structure; wherein the content of the first and second substances,

the at least one contact structure connects two adjacent active regions of the at least one active region and a target gate structure; the target gate structure belongs to the at least one gate structure;

the projection of the target gate structure in the substrate intersects the projections of the other active areas except the two adjacent active areas in the at least one active area in the substrate.

The embodiment of the present application further provides a method for designing an SRAM memory cell, where the method includes:

providing a substrate;

providing at least one active region extending in a first direction; the at least one active region includes: a first active region and a second active region;

providing at least one gate structure extending along a second direction; the second direction is perpendicular to the first direction; a first gate structure;

providing at least one contact structure; wherein, the first and the second end of the pipe are connected with each other,

the projection of the target gate structure in the substrate intersects the projections of the other active regions in the at least one active region except the two adjacent active regions in the substrate.

An embodiment of the present application further provides an SRAM memory cell circuit, which includes: the device comprises a switch unit, a first latch unit and a second latch unit;

the switch unit, the first latch unit and the second latch unit are connected through at least one contact structure;

the first latch unit is connected with a power supply end; the second latch unit is connected with a grounding end;

the switch unit is connected with a bit line; the switch unit also receives a word line signal; wherein the content of the first and second substances,

the switch unit is used for conducting the first latch unit and the second latch unit on the bit line under the condition of being triggered by the word line signal in a reading state and a writing state so as to read and write a storage signal;

the first latch unit and the second latch unit form a latch circuit for locking and saving the storage signal.

The embodiment of the present application further provides a semiconductor structure, which is characterized by being shown by a layout in the foregoing scheme.

The embodiment of the application also provides a semiconductor memory which is characterized by comprising the semiconductor structure in the scheme.

Therefore, the embodiment of the application provides a layout and a design method of an SRAM memory cell, a circuit, a semiconductor structure and a memory, wherein the layout of the SRAM memory cell comprises: a substrate; at least one active region extending in a first direction; at least one gate structure extending along a second direction, wherein the second direction is perpendicular to the first direction; and, at least one contact structure. Wherein the at least one contact structure connects two adjacent active regions of the at least one active region and the target gate structure; the target gate structure belongs to at least one gate structure; the projection of the target gate structure in the substrate intersects the projections of the other active regions except two adjacent active regions in the at least one active region in the substrate. Therefore, the semiconductor device is directly connected through the contact structure, and the use of connecting wires is reduced, so that the processing area can be saved, and the integration level of an integrated circuit is improved; meanwhile, the process of metal wiring is reduced, so that the processing technology is simplified, and the product yield can be improved.

Drawings

Fig. 1 is a first schematic diagram of a layout of an SRAM memory cell according to an embodiment of the present application;

fig. 2 is a second schematic diagram of a layout of an SRAM memory cell according to an embodiment of the present application;

fig. 3 is a third schematic diagram of a layout of an SRAM memory cell according to an embodiment of the present application;

fig. 4 is a fourth schematic diagram of a layout of an SRAM memory cell according to an embodiment of the present application;

fig. 5 is a first flowchart of a layout design method for an SRAM memory cell according to an embodiment of the present application;

fig. 6 is a second flowchart of a layout design method for an SRAM memory cell according to an embodiment of the present application;

fig. 7 is a third flowchart of a layout design method for an SRAM memory cell according to an embodiment of the present application;

FIG. 8 is a first schematic diagram of an SRAM memory cell circuit according to an embodiment of the present disclosure;

FIG. 9 is a second schematic diagram of an SRAM memory cell circuit provided in an embodiment of the present application;

fig. 10 is a schematic structural diagram of a semiconductor memory according to an embodiment of the present disclosure.

Detailed Description

In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application are further described in detail with reference to the drawings and the embodiments, the described embodiments should not be considered as limiting the present application, and all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

The following description will be added if a similar recitation of "first/second" appears in the specification, and reference is made in the following description to the term "first/second/third" merely to distinguish between similar objects and not to imply a particular ordering with respect to the objects, it being understood that "first/second/third" may, where permissible, be interchanged in a particular order or sequence to enable the embodiments of the application described herein to be practiced in other than the order illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the application.

In an integrated circuit, semiconductor devices are formed on a semiconductor substrate, and connection lines are used to conduct the semiconductor devices. However, in the process of disposing the connecting lines, a part of metal material needs to be disposed at the contact position between the connecting lines and the semiconductor device, and an allowance space is left to avoid poor conduction and influence on the performance of the integrated circuit. Therefore, a larger space is reserved for arranging the connecting wires, the processing area is additionally occupied, and the integration level of the integrated circuit is not improved; meanwhile, the process of arranging the connecting wires is complex, and high risk causes low yield.

Fig. 1 is a layout of an SRAM memory cell provided in an embodiment of the present application, and as shown in fig. 1, a layout 01 of the SRAM memory cell includes: a substrate 11 (the hollow filled region in fig. 1); at least one active region (dotted fill region in fig. 1) extending along a first direction, comprising: a first active region 1201, a second active region 1202, a third active region 1203, and a fourth active region 1204; at least one gate structure (diagonal filled region in fig. 1) extending along a second direction, comprising: a first gate structure 1301 and a second gate structure 1302, wherein the second direction is perpendicular to the first direction; at least one contact structure (the area enclosed by the bold black box in fig. 1) comprising: a first contact structure 1401 and a second contact structure 1402.

Wherein the at least one contact structure connects two adjacent active regions of the at least one active region and a target gate structure, wherein the target gate structure belongs to the at least one gate structure. Referring to fig. 1, the target gate structure may be a first gate structure 1301, and a first contact structure 1401 connects the first active region 1201, the second active region 1202 and the first gate structure 1301; the target gate structure may also be a second gate structure 1302, the second contact structure 1402 connecting the third active region 1203, the fourth active region 1204 and the second gate structure 1302.

The projection of the target gate structure in the substrate intersects the projections of the other active regions except two adjacent active regions in the at least one active region in the substrate. Referring to fig. 1, the target gate structure may be a first gate structure 1301, and a projection of the third active region 1203 in the substrate 11 and a projection of the fourth active region 1204 in the substrate 11 respectively intersect with a projection of the first gate structure 1301 in the substrate 11; the target gate structure may also be the second gate structure 1302, and a projection of the first active region 1201 in the substrate 11 and a projection of the second active region 1202 in the substrate 11 intersect with a projection of the second gate structure 1302 in the substrate 11, respectively.

It should be noted that the integrated circuit layout is a planar geometric description of the physical condition of a real integrated circuit, and includes information about the shape, area, and position of each hardware unit on the chip. That is, the patterns in the integrated circuit layout characterize the hardware units in the integrated circuit and their electrical connections.

In the embodiment of the present application, the circuit structure in fig. 9 has a corresponding relationship with fig. 1. With reference to fig. 1 and fig. 9, a projection of the third active region 1203 in the substrate 11 and a projection of the fourth active region 1204 in the substrate 11 intersect with a projection of the first gate structure 1301 in the substrate 11, respectively, so as to represent source-drain regions at two sides of the first gate structure 1301 in the third active region 1203, and the source-drain regions at two sides of the first gate structure 1301 and the first gate structure 1301 together form a first PMOS transistor PU1; and the fourth active region 1204 is in the source-drain regions at two sides of the first gate structure 1301, and the source-drain regions at two sides of the first gate structure 1301 and the first gate structure 1301 together form a third NMOS transistor PD1. The projection of the first active region 1201 in the substrate 11 and the projection of the second active region 1202 in the substrate 11 intersect with the projection of the second gate structure 1302 in the substrate 11, respectively, which represents the source-drain regions at two sides of the second gate structure 1302 in the first active region 1201, and the source-drain regions at two sides of the second gate structure 1302 and the second gate structure 1302 together form a fourth NMOS tube PD2; and source-drain regions on two sides of the second gate structure 1302 in the second active region 1202, and the source-drain regions on two sides of the second gate structure 1302 and the second gate structure 1302 together form a second PMOS transistor PU2.

The first contact structure 1401 connects the first active region 1201, the second active region 1202 and the first gate structure 1301, and it is characterized that the drain of the fourth NMOS transistor PD2, the drain of the second PMOS transistor PU2, the gate of the first PMOS transistor PU1 and the gate of the third NMOS transistor PD1 are electrically connected through the first contact structure 1401. The second contact structure 1402 is connected to the third active region 1203, the fourth active region 1204 and the second gate structure 1302, which means that the drain of the third NMOS transistor PD1, the drain of the first PMOS transistor PU1, the gate of the second PMOS transistor PU2 and the gate of the fourth NMOS transistor PD2 are electrically connected through the second contact structure 1402.

In the embodiment of the present application, as shown in fig. 1, a first active region 1201, a second active region 1202, a third active region 1203, and a fourth active region 1204 are sequentially arranged adjacently. The first active region 1201 and the fourth active region 1204 are centrosymmetric. The second active region 1202 is centrosymmetric to the third active region 1203. The first gate structure 1301 and the second gate structure 1302 are centrosymmetric. The first contact structure 1401 is centrosymmetric to the second contact structure 1402.

Accordingly, the first active region 1201, the second active region 1202, the third active region 1203, the fourth active region 1204, the first gate structure 1301, the second gate structure 1303, the first contact structure 1401, and the second contact structure 1402 can be disposed as the symmetrical semiconductor devices of the first PMOS transistor PU1 and the second PMOS transistor PU2, and the third NMOS transistor PD1 and the fourth NMOS transistor PD2 in fig. 9, which have symmetrical electrical connection relations.

In the present embodiment, as shown in fig. 2, at least one contact structure (i.e., the first contact structure 1401 and the second contact structure 1402) may have an L-shape. The length of each side of the L-shape may be as shown in table 1:

TABLE 1

It can be understood that the drain electrode of the fourth NMOS transistor PD2, the drain electrode of the second PMOS transistor PU2, the gate electrode of the first PMOS transistor PU1, and the gate electrode of the third NMOS transistor PD1 are directly connected through the first contact structure 1401; the drain electrode of the third NMOS transistor PD1, the drain electrode of the first PMOS transistor PU1, the gate electrode of the second PMOS transistor PU2, and the gate electrode of the fourth NMOS transistor PD2 are directly connected through the second contact structure 1402. Therefore, the use of connecting wires is reduced, the processing area can be saved, and the integration level of the integrated circuit is improved; meanwhile, the process of metal wiring is reduced, so that the processing technology is simplified, and the product yield can be improved.

In some embodiments of the present application, as shown in fig. 3, in the memory cell layout 01, further including: a third gate structure 1303 extending in the second direction; third contact structure 1403, fourth contact structure 1404, fifth contact structure 1405 and sixth contact structure 1406.

Wherein the projection of the third gate structure 1303 in the substrate 11 intersects the projection of the first active region 1201 in the substrate 11; the third contact structure 1403 and the fourth contact structure 1404 are both located in the first active region 1201; the third contact structure 1403 and the first contact structure 1401 are respectively located at two sides of the third gate structure 1303; the fourth contact structure 1404 and the first contact structure 1401 are respectively positioned at two sides of the second gate structure 1302; a fifth contact structure 1405 is located in the second active region 1202; the fifth contact structure 1405 and the first contact structure 1401 are respectively located at both sides of the second gate structure 1302; the sixth contact structure 1406 is located in the third gate structure 1303.

In this embodiment, with reference to fig. 3 and 9, the projection of the third gate structure 1303 in the substrate 11 intersects the projection of the first active region 1201 in the substrate 11, which represents the source-drain regions at two sides of the third gate structure 1303 in the first active region 1201, and the source-drain regions at two sides of the third gate structure 1303 and the third gate structure 1303 jointly form the second NMOS transistor PG2; the source of the second NMOS transistor PG2 is also the drain of the fourth NMOS transistor PD 2.

The third contact structure 1403 is located in the first active region 1201, and the third contact structure 1403 and the first contact structure 1401 are located at two sides of the third gate structure 1303, respectively, which indicates that the third contact structure 1403 is connected to the drain of the second NMOS transistor PG2, and the first contact structure 1401 is connected to the source of the second NMOS transistor PG2 (also referred to as the drain of the fourth NMOS transistor PD 2).

The fourth contact structure 1404 is located in the first active region 1201, and the fourth contact structure 1404 and the first contact structure 1401 are located at two sides of the second gate structure 1302, respectively, which indicates that the fourth contact structure 1404 is connected to the source of the fourth NMOS transistor PD2, and the first contact structure 1401 is connected to the drain of the fourth NMOS transistor PD2 (also referred to as the source of the second NMOS transistor PG 2).

The fifth contact structure 1405 is located in the second active region 1202, and the fifth contact structure 1405 and the first contact structure 1401 are located at two sides of the second gate structure 1302, respectively, which indicates that the fifth contact structure 1405 is connected to the source of the second PMOS transistor PU2, and the first contact structure 1401 is connected to the drain of the second PMOS transistor PU2.

The sixth contact structure 1406 is located in the third gate structure 1303, which indicates that the sixth contact structure 1406 is connected to the gate of the second NMOS transistor PG 2.

In some embodiments of the present application, as shown in fig. 3, in the memory cell layout 01, further includes: a fourth gate structure 1304 extending along the second direction; seventh contact structure 1407, eighth contact structure 1408, ninth contact structure 1409, and tenth contact structure 1410.

Wherein a projection of the fourth gate structure 1304 in the substrate 11 intersects a projection of the fourth active region 1204 in the substrate 11; the seventh contact structure 1407 is located in the third active region 1203; the seventh contact structure 1407 and the second contact structure 1402 are respectively located at two sides of the first gate structure 1301; eighth contact structure 1408 and ninth contact structure 1409 are both located in fourth active region 1204; the eighth contact structure 1408 and the second contact structure 1402 are respectively located at two sides of the first gate structure 1301; the ninth contact structure 1409 and the second contact structure 1402 are respectively located at two sides of the fourth gate structure 1304; a tenth contact structure 1410 is located in the fourth gate structure 1304.

In this embodiment, with reference to fig. 3 and fig. 9, a projection of the fourth gate structure 1304 in the substrate 11 intersects a projection of the fourth active region 1204 in the substrate 11, so as to represent source-drain regions at two sides of the fourth gate structure 1304 in the fourth active region 1204, and the source-drain regions at two sides of the fourth gate structure 1304 and the fourth gate structure 1304 are provided with the first NMOS transistor PG1; the source of the first NMOS transistor PG1 is also the drain of the third NMOS transistor PD1.

The seventh contact structure 1407 is located in the third active region 1203, and the seventh contact structure 1407 and the second contact structure 1402 are respectively located on two sides of the first gate structure 1301, which indicates that the seventh contact structure 1407 is connected to the source of the first PMOS transistor PU1, and the second contact structure 1402 is connected to the drain of the first PMOS transistor PU 1.

The eighth contact structure 1408 is located in the fourth active region 1204, and the eighth contact structure 1408 and the second contact structure 1402 are respectively located at two sides of the first gate structure 1301, which indicates that the eighth contact structure 1408 is connected to the source of the third NMOS transistor PD1, and the second contact structure 1402 is connected to the drain of the third NMOS transistor PD1 (also the source of the first NMOS transistor PG 1).

The ninth contact structure 1409 is located in the fourth active region 1204, and the ninth contact structure 1409 and the second contact structure 1402 are respectively located at two sides of the fourth gate structure 1304, which indicates that the ninth contact structure 1409 is connected to the drain of the first NMOS transistor PG1, and the second contact structure 1402 is connected to the source of the first NMOS transistor PG1 (also the drain of the third NMOS transistor PD 1).

A tenth contact structure 1410 is located in the fourth gate structure 1304, indicating that the tenth contact structure 1410 is connected to the gate of the first NMOS transistor PG 1.

In the embodiment, as shown in fig. 3, the third gate structure 1303 and the fourth gate structure 1304 are centrosymmetric. The first gate structure 1301 and the third gate structure 1303 are located on the same side of the second gate structure 1302, and the second gate structure 1302 and the fourth gate structure 1304 are located on the same side of the first gate structure 1301.

Accordingly, the first active region 1201, the fourth active region 1204, the third gate structure 1303, the fourth gate structure 1304, the first contact structure 1401, and the second contact structure 1402 can provide the symmetrical semiconductor devices of the first NMOS transistor PG1 and the second NMOS transistor PG2 in fig. 9, which have a symmetrical electrical connection relationship.

It will be appreciated that the memory cell circuit of fig. 9 is constructed with a new physical structure by means of active regions, gate structures and contact structures. Therefore, in the process of manufacturing the memory cell circuit, the use of connecting wires is reduced, the processing area is saved, and the integration level of an integrated circuit is improved; meanwhile, the process of metal wiring is reduced, the processing technology is simplified, and the yield of products can be improved.

In some embodiments of the present application, as shown in fig. 4, in the memory cell layout 01, further includes:

at least one metal line (horizontal line filling area in fig. 4) comprising: a first wire 1501, a second wire 1502, a third wire 1503, a fourth wire 1504, a fifth wire 1505, a sixth wire 1506, a seventh wire 1507, and an eighth wire 1508.

Wherein, the first metal line 1501, the second metal line 1502, the third metal line 1503, the fourth metal line 1504, the fifth metal line 1505, the sixth metal line 1506, the seventh metal line 1507 and the eighth metal line 1508 are connected to the third contact structure 1403, the fourth contact structure 1404, the fifth contact structure 1405, the sixth contact structure 1406, the seventh contact structure 1407, the eighth contact structure 1408, the ninth contact structure 1409 and the tenth contact structure 1410, respectively, in sequence.

In the embodiments of the present application, the metal line and the contact structure are correspondingly connected, and represent an active region or a gate structure connected to the contact structure, and are electrically connected with other objects through the contact structure and the metal line.

It can be understood that the electrical connection of each MOS port in the memory cell circuit and the corresponding electrical connection object is completed through the use of the metal wire.

An alternative flow chart of the SRAM memory cell layout design method will be described with reference to the steps shown in fig. 5.

S201, providing a substrate.

In the embodiment of the application, a substrate is required to be provided firstly when an SRAM memory cell layout is designed, and the SRAM memory cell is obtained by processing and manufacturing on the substrate. The substrate is a clean single crystal semiconductor wafer having a particular crystal plane and suitable electrical, optical and mechanical properties. The substrate is typically a single crystal silicon material, but may be other semiconductor materials.

S202, providing at least one active region extending along a first direction.

In the embodiment of the present application, a designer may set at least one active region extending in a first direction on a substrate in a layout. The active region is a region on the substrate for making an active device; the active device is capable of operating under an external power source.

Referring to fig. 1, the at least one active region may include: a first active region 1201, a second active region 1202, a third active region 1203 and a fourth active region 1204. The first active region 1201, the second active region 1202, the third active region 1203 and the fourth active region 1204 are arranged adjacently in this order.

It should be noted that the fabrication of the active region can be completed by the following method: the semiconductor device may dope portions of regions in the substrate to alter the electrical properties of those regions to form at least one active region. Taking a substrate of a single crystal silicon material as an example, a P-type active region can be formed by doping a 3-valent element, such as boron (B), into the silicon substrate, and the P-type active region contains a hole; an N-type active region, which includes free electrons, can be formed by doping a 5-valent element, such As phosphorus (P) or arsenic (As), into a silicon substrate. Semiconductor devices, such as PMOS and NMOS, may be formed based on the P-type active region and the N-type active region.

The doping of the substrate may be done by selective Diffusion or Ion Implantation (Ion Implantation) depending on the required doping depth. The diffusion is to directly contact the doping elements with the surface of the silicon substrate, and the doping elements are doped into the silicon substrate with the assistance of heat energy, and the doping depth of the diffusion is shallow. The ion implantation is to activate a doping material into a Plasma state (Plasma), and implant the Plasma into a region to be doped in the silicon substrate after high-energy acceleration, wherein the doping depth of the ion implantation is deeper. Since ion implantation causes Lattice Damage to a silicon substrate (Lattice Damage), thermal Annealing is also required to repair the Lattice Damage.

S203, arranging at least one grid structure extending along a second direction; the second direction is perpendicular to the first direction.

In the embodiment of the present application, a designer may set at least one gate structure extending along a second direction on an active region in a layout, where the second direction is perpendicular to the first direction.

Referring to fig. 1, the at least one gate structure may include: a first gate structure 1301 and a second gate structure 1302.

It should be noted that the gate structure includes a gate dielectric layer and other dielectric layers on the gate dielectric layer, a gate active region is below the gate dielectric layer, and the gate dielectric layer and other dielectric layers are deposited on the gate active region. The projection of the gate structure in the substrate is vertically intersected with the projection of the corresponding active region in the substrate, active drain regions are formed in the active regions on two sides of the gate structure, and the doping types of the source drain regions and the gate active regions are opposite. The gate structure and the source and drain regions on both sides thereof form a MOS.

S204, arranging at least one contact structure; wherein the at least one contact structure connects two adjacent active regions of the at least one active region and the target gate structure; the target gate structure belongs to at least one gate structure; the projection of the target gate structure in the substrate intersects the projections of the other active regions in the at least one active region except for two adjacent active regions in the substrate.

In the embodiment of the present application, after a designer sets at least one active region and at least one gate structure, the designer may set at least one contact structure in a layout. Wherein the at least one contact structure connects two adjacent active regions of the at least one active region and the target gate structure. And the projection of the target gate structure in the substrate is intersected with the projections of other active regions except two adjacent active regions in the substrate in at least one active region.

Referring to fig. 1, at least one contact structure may include: a first contact structure 1401 and a second contact structure 1402. The target gate structure may be a first gate structure 1301 and a first contact structure 1401 connects the first active region 1201, the second active region 1202 and the first gate structure 1301. The target gate structure may also be a second gate structure 1302, the second contact structure 1402 connecting the third active region 1203, the fourth active region 1204 and the second gate structure 1302.

In the present embodiment, as shown in fig. 2, at least one contact structure (i.e., the first contact structure 1401 and the second contact structure 1402) may have an L-shape. The length of each side of the L-shape may be as shown in table 1.

It should be noted that the material of the contact structure is a conductive material, so as to electrically connect the corresponding regions, that is, two adjacent active regions in at least one active region and the target gate structure can be electrically connected through at least one contact structure. Referring to fig. 1, a first active region 1201, a second active region 1202, and a first gate structure 1301 may be electrically connected through a first contact structure 1401; the third active region 1203, the fourth active region 1204, and the second gate structure 1302 may be electrically connected through the second contact structure 1402.

With continued reference to fig. 1, the projection of the third active region 1203 in the substrate 11 and the projection of the fourth active region 1204 in the substrate 11 intersect the projection of the first gate structure 1301 in the substrate 11, respectively; the projection of the first active region 1201 in the substrate 11 and the projection of the second active region 1202 in the substrate 11 intersect the projection of the second gate structure 1302 in the substrate 11, respectively.

The first active region 1201 is centrosymmetric to the fourth active region 1204. The second active region 1202 is centrosymmetric to the third active region 1203. The first gate structure 1301 and the second gate structure 1302 are centrosymmetric. The first contact structure 1401 is centrosymmetric to the second contact structure 1402.

Accordingly, the first active region 1201, the second active region 1202, the third active region 1203, the fourth active region 1204, the first gate structure 1301, the second gate structure 1303, the first contact structure 1401 and the second contact structure 1402 can form the symmetrical semiconductor devices of the first PMOS transistor PU1 and the second PMOS transistor PU2, and the third NMOS transistor PD1 and the fourth NMOS transistor PD2 in fig. 9, which have a symmetrical electrical connection relationship.

It can be understood that the drain electrode of the fourth NMOS transistor PD2, the drain electrode of the second PMOS transistor PU2, the gate electrode of the first PMOS transistor PU1, and the gate electrode of the third NMOS transistor PD1 are directly connected through the first contact structure 1401; the drain electrode of the third NMOS transistor PD1, the drain electrode of the first PMOS transistor PU1, the gate electrode of the second PMOS transistor PU2, and the gate electrode of the fourth NMOS transistor PD2 are directly connected through the second contact structure 1402. Therefore, the use of connecting wires is reduced, thereby saving the processing area and improving the integration level of the integrated circuit; meanwhile, the process of metal wiring is reduced, so that the processing technology is simplified, and the product yield can be improved.

In some embodiments of the present application, S205 shown in fig. 6 is further included after S202 shown in fig. 5, and will be described in conjunction with various steps.

S205, arranging a third gate structure and a fourth gate structure extending along a second direction; the projection of the third gate structure in the substrate intersects the projection of the first active region in the substrate; the projection of the fourth gate structure in the substrate intersects the projection of the fourth active region in the substrate.

In the embodiment of the present application, after the designer sets at least one active region, a third gate structure and a fourth gate structure that extend along the second direction may also be set on the layout.

Referring to fig. 3, the third gate structure 1303 and the fourth gate structure 1304 are centrosymmetric; the projection of the third gate structure 1303 in the substrate 11 intersects the projection of the first active region 1201 in the substrate 11; the projection of the fourth gate structure 1304 into the substrate 11 intersects the projection of the fourth active region 1204 into the substrate 11.

The third gate structure 1303 and the fourth gate structure 1304 are centrosymmetric. The first gate structure 1301 and the third gate structure 1303 are located on the same side of the second gate structure 1302, and the second gate structure 1302 and the fourth gate structure 1304 are located on the same side of the first gate structure 1301.

Accordingly, the first active region 1201, the fourth active region 1204, the third gate structure 1303, the fourth gate structure 1304, the first contact structure 1401, and the second contact structure 1402 can form the symmetrical semiconductor devices of the first NMOS transistor PG1 and the second NMOS transistor PG2 in fig. 9, which have a symmetrical electrical connection relationship.

S206, setting a third contact structure, a fourth contact structure, a fifth contact structure, a sixth contact structure, a seventh contact structure, an eighth contact structure, a ninth contact structure and a tenth contact structure; the third contact structure and the fourth contact structure are both positioned in the first active region; the fifth contact structure is positioned in the second active region; the sixth contact structure is positioned in the third gate structure; the seventh contact structure is located in the third active region; the eighth contact structure and the ninth contact structure are both positioned in the fourth active region; the tenth contact structure is located in the fourth gate structure.

In this embodiment of the application, a designer may further set a third contact structure, a fourth contact structure, a fifth contact structure, a sixth contact structure, a seventh contact structure, an eighth contact structure, a ninth contact structure, and a tenth contact structure in the layout.

Referring to fig. 4, the third contact structure 1403 and the fourth contact structure 1404 are both located in the first active region 1201; a fifth contact structure 1405 is located in the second active region 1202; the sixth contact structure 1406 is located in the third gate structure 1303; the seventh contact structure 1407 is located in the third active region 1203; eighth contact structure 1408 and ninth contact structure 1409 are both located in fourth active region 1204; a tenth contact structure 1410 is located in the fourth gate structure 1304.

The third contact structure 1403 and the first contact structure 1401 are respectively located at two sides of the third gate structure 1303, and it is characterized that the third contact structure 1403 and the first contact structure 1401 are respectively connected to the drain and the source of the second NMOS transistor PG 2. The fourth contact structure 1404 and the first contact structure 1401 are respectively located at two sides of the second gate structure 1302, and the fourth contact structure 1404 and the first contact structure 1401 are respectively connected with the source and the drain of the fourth NMOS transistor PD 2. The fifth contact structure 1405 and the first contact structure 1401 are respectively located at two sides of the second gate structure 1302, which means that the fifth contact structure 1405 and the first contact structure 1401 are respectively connected to the source and the drain of the second PMOS transistor PU2. The sixth contact structure 1406 is connected to the gate of the second NMOS transistor PG 2. The seventh contact structure 1407 and the second contact structure 1402 are respectively located on two sides of the first gate structure 1301, which means that the seventh contact structure 1407 and the second contact structure 1402 are respectively connected to the source and the drain of the first PMOS transistor PU 1. The eighth contact structure 1408 and the second contact structure 1402 are respectively located at two sides of the first gate structure 1301, and it is characterized that the eighth contact structure 1408 and the second contact structure 1402 are respectively connected to the source and the drain of the third NMOS transistor PD1. The ninth contact structure 1409 and the second contact structure 1402 are respectively located at two sides of the fourth gate structure 1304, which means that the ninth contact structure 1409 and the second contact structure 1402 are respectively connected to the drain and the source of the first NMOS transistor PG 1. The tenth contact structure 1410 is connected to the gate of the first NMOS transistor PG 1.

It should be noted that the semiconductor device may be manufactured by photolithography (photolithography) and etching (Etch) processes. The semiconductor device may form a patterned photoresist layer based on a reticle (mask) containing a specific pattern; and performing at least one etching process based on the patterned photoresist layer by adopting different etching selection ratios to form a contact structure at the corresponding position.

It will be appreciated that the memory cell circuit of fig. 9 is constructed with a new physical structure by means of active regions, gate structures and contact structures. Therefore, in the process of manufacturing the memory cell circuit, the use of connecting wires is reduced, the processing area is saved, and the integration level of the integrated circuit is improved; meanwhile, the process of metal wiring is reduced, the processing technology is simplified, and the product yield can be improved.

In some embodiments of the present application, S207 shown in fig. 7 is further included after S206 shown in fig. 6, and the description will be given in conjunction with each step.

S207, arranging a first metal wire, a second metal wire, a third metal wire, a fourth metal wire, a fifth metal wire, a sixth metal wire, a seventh metal wire and an eighth metal wire; the first metal wire, the second metal wire, the third metal wire, the fourth metal wire, the fifth metal wire, the sixth metal wire, the seventh metal wire and the eighth metal wire are respectively connected with the third contact structure, the fourth contact structure, the fifth contact structure, the sixth contact structure, the seventh contact structure, the eighth contact structure, the ninth contact structure and the tenth contact structure in sequence.

In the embodiment of the application, after the contact structure is set, a designer may set at least one metal line on the conductive material in the layout, and the metal line is electrically connected to the contact structure. At least one of the metal lines includes: the first metal wire, the second metal wire, the third metal wire, the fourth metal wire, the fifth metal wire, the sixth metal wire, the seventh metal wire and the eighth metal wire.

Referring to fig. 5, a first metal line 1501, a second metal line 1502, a third metal line 1503, a fourth metal line 1504, a fifth metal line 1505, a sixth metal line 1506, a seventh metal line 1507, and an eighth metal line 1508 respectively connect, in sequence, the third contact structure 1403, the fourth contact structure 1404, the fifth contact structure 1405, the sixth contact structure 1406, the seventh contact structure 1407, the eighth contact structure 1408, the ninth contact structure 1409, and the tenth contact structure 1410, respectively.

In the embodiment of the application, the metal line and the contact structure are correspondingly connected, and the active region or the gate structure connected to the contact structure is characterized and is electrically connected with other objects through the contact structure and the metal line.

It can be understood that the electrical connection of each MOS port in the memory cell circuit to the corresponding electrical connection object is completed through the use of the metal wire.

Fig. 8 is a schematic diagram of an alternative structure of an SRAM memory cell circuit according to an embodiment of the present application. As shown in fig. 8, the memory cell circuit 03 includes: a switching unit 301, a first latch unit 302, and a second latch unit 303.

The switching unit 301, the first latch unit 302, and the second latch unit 303 are connected to the point Q and the point QB through at least one contact structure; the first latch unit 302 is connected to the power source terminal V _DD (ii) a The second latch unit 303 is connected to the ground terminal; the switch unit 301 connects Bit Lines (BL) and bit bar (BLB); the switch unit 301 also receives a Word Line (WL) signal of a word line.

The switch unit 301 is configured to, in a read state and a write state, turn on the first latch unit 302 and the second latch unit 303 to the bit lines BL and BLB when triggered by a word line signal, so as to read and write a storage signal;

the first latch unit 302 and the second latch unit 303 constitute a latch circuit 304 for locking and holding a storage signal.

In some embodiments of the present application, as shown in fig. 9, the switching unit 301 includes: a first NMOS tube PG1 and a second NMOS tube PG2; the first latch unit 302 includes: a first PMOS tube PU1 and a second PMOS tube PU2; the second latch unit 303 includes: a third NMOS transistor PD1 and a fourth NMOS transistor PD2; the at least one contact structure includes: a first contact structure and a second contact structure.

In the embodiment of the present application, in conjunction with fig. 3 and 9, at least one contact structure includes: a first contact structure 1401 and a second contact structure 1402; the source electrode of the second NMOS tube PG2 is the drain electrode of a fourth NMOS tube PD2; the source electrode of the first NMOS transistor PG1 is the drain electrode of the third NMOS transistor PD1.

The drain of the fourth NMOS transistor PD2, the drain of the second PMOS transistor PU2, and the first PMOS transistor PU1 are connected to a point QB (shown in fig. 9) through a first contact structure 1401. The drain of the third NMOS transistor PD1, the drain of the first PMOS transistor PU1, and the gate of the second PMOS transistor PU2 are connected to a point Q (shown in fig. 9) through a second contact structure 1402.

In the embodiment of the present application, referring to fig. 9, the bit lines include a first bit line BL and a second bit line BLB, which are inverted in signal. The source electrodes of the first PMOS tube PU1 and the second PMOS tube PU2 are also connected with a power supply end V _DD . The source electrodes of the third and fourth NMOS transistors PD1 and PD2 are also connected to the ground terminal. The gates of the first NMOS transistor PG1 and the second NMOS transistor PG2 are also connected to a word line WL, and receive a word line signal. The drain electrode of the first NMOS tube PG1 is also connected with a first bit line BL; the drain of the second NMOS transistor PG2 is also connected to a second bit line BLB. With reference to fig. 3 and 9, table 2 shows the corresponding connection relationship between the contact structure in fig. 3 and each MOS port of the memory cell circuit 3 in fig. 9 and the electrical connection object:

contact structure	MOS port	Electric connection object
			1401	PG2 source, PD2 drain, PU1 gate and PU2 drain	QB
1402	PG1 source, PD1 drain, PU1 drain and PU2 gate	Q
			1403	PG2 drain electrode	BLB
1404	PD2 source electrode	Grounding terminal
			1405	PU2 source electrode	V	_DD
1406	PG2 grid	WL
			1407	PU1 source electrode	V	_DD
1408	PD1 source electrode	Grounding terminal
			1409	PG1 drain electrode	BL
1410	PG1 grid	WL

TABLE 2

In this embodiment of the application, the first NMOS tube PG1 is configured to conduct a drain of the first PMOS tube PU1, a drain of the third NMOS tube PD1, a gate of the second PMOS tube PU2, a gate of the fourth NMOS tube PD2, and the first bit line BL when triggered by a word line signal in a read state and a write state, so as to read and write a storage signal.

And the second NMOS transistor PG2 is configured to conduct a drain of the second PMOS transistor PU2, a drain of the fourth NMOS transistor PD2, a gate of the first PMOS transistor PU1, a gate of the third NMOS transistor PD1, and the second bit line BLB when triggered by a word line signal in a read state and a write state, so as to read and write a storage signal.

It can be understood that the drain electrode of the fourth NMOS transistor PD2, the drain electrode of the second PMOS transistor PU2, the gate electrode of the first PMOS transistor PU1, and the gate electrode of the third NMOS transistor PD1 are directly connected through the first contact structure 1401; the drain of the third NMOS transistor PD1, the drain of the first PMOS transistor PU1, the gate of the second PMOS transistor PU2, and the gate of the fourth NMOS transistor PD2 are directly connected through the second contact structure 1402. Therefore, the use of connecting wires is reduced, thereby saving the processing area and improving the integration level of the integrated circuit; meanwhile, the process of metal wiring is reduced, so that the processing technology is simplified, and the product yield can be improved.

The embodiment of the present application also provides a semiconductor structure 800, as shown in fig. 10. The semiconductor structure 800 is illustrated by the layout provided by the previous embodiments. Therefore, the use of connecting wires can be reduced, and the integration level of the integrated circuit is improved; the process of metal wiring is reduced, the processing technology is simplified, and the product yield is improved.

The embodiment of the present application further provides a semiconductor memory 900, as shown in fig. 10, the semiconductor memory 900 at least includes the semiconductor structure 800 shown in fig. 10.

It should be noted that, in the present application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments. Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict. The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An SRAM memory cell layout, comprising:

a substrate;

at least one active region extending in a first direction;

2. The SRAM memory cell layout of claim 1, wherein the at least one active region comprises: a first active region and a second active region; the at least one gate structure includes: a first gate structure; the at least one contact structure comprises: a first contact structure; wherein the content of the first and second substances,

the first contact structure connects the first active region, the second active region, and the first gate structure.

3. The SRAM memory cell layout of claim 2, wherein said at least one active region further comprises: a third active region and a fourth active region; the at least one gate structure further comprises: a second gate structure; the at least one contact structure further comprises: a second contact structure; wherein the content of the first and second substances,

the projection of the first active region in the substrate and the projection of the second active region in the substrate respectively intersect with the projection of the second gate structure in the substrate; the projection of the third active region in the substrate and the projection of the fourth active region in the substrate respectively intersect with the projection of the first gate structure in the substrate;

the second contact structure connects the third active region, the fourth active region, and the second gate structure.

4. The SRAM memory cell layout of claim 3, wherein the layout further comprises:

a third gate structure extending along the second direction;

a third contact structure, a fourth contact structure, a fifth contact structure, and a sixth contact structure; wherein the content of the first and second substances,

a projection of the third gate structure in the substrate intersects the projection of the first active region in the substrate;

the third contact structure and the fourth contact structure are both located in the first active region; the third contact structure and the first contact structure are respectively positioned at two sides of the third gate structure; the fourth contact structure and the first contact structure are respectively positioned at two sides of the second gate structure;

the fifth contact structure is located in the second active region; the fifth contact structure and the first contact structure are respectively positioned at two sides of the second gate structure;

the sixth contact structure is located in the third gate structure.

5. The SRAM memory cell layout of claim 3 or 4, wherein the layout further comprises:

a fourth gate structure extending along the second direction;

a seventh contact structure, an eighth contact structure, a ninth contact structure, and a tenth contact structure; wherein the content of the first and second substances,

a projection of the fourth gate structure in the substrate intersects a projection of the fourth active region in the substrate;

the seventh contact structure is located in the third active region; the seventh contact structure and the second contact structure are respectively positioned at two sides of the first gate structure;

the eighth contact structure and the ninth contact structure are both located in the fourth active region; the eighth contact structure and the second contact structure are respectively positioned at two sides of the first gate structure; the ninth contact structure and the second contact structure are respectively positioned at two sides of the fourth gate structure;

the tenth contact structure is located in the fourth gate structure.

6. The SRAM memory cell layout of claim 5, wherein the layout further comprises:

the first metal wire, the second metal wire, the third metal wire, the fourth metal wire, the fifth metal wire, the sixth metal wire, the seventh metal wire and the eighth metal wire; wherein, the first and the second end of the pipe are connected with each other,

the first metal wire, the second metal wire, the third metal wire, the fourth metal wire, the fifth metal wire, the sixth metal wire, the seventh metal wire and the eighth metal wire are respectively connected in sequence the third contact structure, the fourth contact structure, the fifth contact structure, the sixth contact structure, the seventh contact structure, the eighth contact structure, the ninth contact structure and the tenth contact structure.

7. The SRAM memory cell layout of claim 1, wherein the at least one contact structure is L-shaped.

8. The SRAM memory cell layout of claim 3,

the first active region, the second active region, the third active region and the fourth active region are sequentially arranged adjacently;

the first active region and the fourth active region are centrosymmetric; the second active region and the third active region are centrosymmetric; the first grid structure and the second grid structure are centrosymmetric; the first contact structure and the second contact structure are centrosymmetric.

9. The SRAM memory cell layout of claim 5,

the third gate structure and the fourth gate structure are centrosymmetric;

the first gate structure and the third gate structure are positioned on the same side of the second gate structure;

the second gate structure and the fourth gate structure are located on the same side of the first gate structure.

10. The SRAM memory cell layout of claim 5,

a source drain region in the fourth active region and the fourth gate structure form a first NMOS tube;

a source drain region in the first active region and the third gate structure form a second NMOS tube;

a source drain region in the third active region and the first grid structure form a first PMOS tube;

a source drain region in the second active region and the second grid structure form a second PMOS tube;

a source drain region in the fourth active region and the first gate structure form a third NMOS tube;

and the source-drain region in the first active region and the second gate structure form a fourth NMOS tube.

11. The SRAM memory cell layout of claim 10,

the source electrode of the second NMOS tube is the drain electrode of the fourth NMOS tube; the first contact structure is connected with the drain electrode of the fourth NMOS tube, the drain electrode of the second PMOS tube, the grid electrode of the first PMOS tube and the grid electrode of the third NMOS tube;

the source electrode of the first NMOS tube is the drain electrode of the third NMOS tube; the second contact structure is connected with the drain electrode of the third NMOS tube, the drain electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the fourth NMOS tube;

the third contact structure is connected with the drain electrode of the second NMOS tube;

the fourth contact structure is connected with the source electrode of the fourth NMOS tube;

the fifth contact structure is connected with the source electrode of the second PMOS tube;

the sixth contact structure is connected with the grid electrode of the second NMOS tube;

the seventh contact structure is connected with the source electrode of the first PMOS tube;

the eighth contact structure is connected with the source electrode of the third NMOS tube;

the ninth contact structure is connected with the drain electrode of the first NMOS tube;

the tenth contact structure is connected with the grid electrode of the first NMOS tube.

12. A layout design method of an SRAM memory cell is characterized by comprising the following steps:

providing a substrate;

providing at least one active region extending in a first direction;

providing at least one gate structure extending along a second direction; the second direction is perpendicular to the first direction;

providing at least one contact structure; wherein the content of the first and second substances,

13. The SRAM memory cell layout design method of claim 12,

the at least one active region includes: a first active region and a second active region;

the at least one gate structure includes: a first gate structure;

the at least one contact structure comprises: a first contact structure; wherein, the first and the second end of the pipe are connected with each other,

14. The SRAM memory cell layout design method of claim 13,

the at least one active region further comprises: a third active region and a fourth active region;

the at least one gate structure further comprises: a second gate structure;

the at least one contact structure further comprises: a second contact structure; wherein the content of the first and second substances,

15. The SRAM memory cell layout design method of claim 14, wherein after the providing at least one active region extending in a first direction, the method further comprises:

providing a third gate structure and a fourth gate structure extending along the second direction; the projection of the third gate structure in the substrate intersects the projection of the first active region in the substrate; a projection of the fourth gate structure in the substrate intersects a projection of the fourth active region in the substrate;

providing a third contact structure, a fourth contact structure, a fifth contact structure, a sixth contact structure, a seventh contact structure, an eighth contact structure, a ninth contact structure and a tenth contact structure; wherein the third contact structure and the fourth contact structure are both located in the first active region; the fifth contact structure is located in the second active region; the sixth contact structure is located in the third gate structure; the seventh contact structure is located in the third active region; the eighth contact structure and the ninth contact structure are both located in the fourth active region; the tenth contact structure is located in the fourth gate structure.

16. The layout design method for the SRAM memory cell according to claim 15, wherein after the third contact structure, the fourth contact structure, the fifth contact structure, the sixth contact structure, the seventh contact structure, the eighth contact structure, the ninth contact structure and the tenth contact structure are arranged, the method further comprises:

arranging a first metal wire, the second metal wire, the third metal wire, the fourth metal wire, the fifth metal wire, the sixth metal wire, the seventh metal wire and an eighth metal wire; the first metal wire, the second metal wire, the third metal wire, the fourth metal wire, the fifth metal wire, the sixth metal wire, the seventh metal wire and the eighth metal wire are respectively connected in sequence the third contact structure, the fourth contact structure, the fifth contact structure, the sixth contact structure, the seventh contact structure, the eighth contact structure, the ninth contact structure and the tenth contact structure.

17. An SRAM memory cell circuit, comprising: the latch circuit comprises a switch unit, a first latch unit and a second latch unit;

the switch unit is connected with a bit line; the switch unit also receives a word line signal; wherein, the first and the second end of the pipe are connected with each other,

18. The SRAM memory cell circuit of claim 17, wherein the switch unit comprises: the first NMOS tube and the second NMOS tube; the first latch unit includes: a first PMOS tube and a second PMOS tube; the second latch unit includes: a third NMOS transistor and a fourth NMOS transistor; the at least one contact structure comprises: a first contact structure and a second contact structure;

the source electrode of the second NMOS tube is the drain electrode of the fourth NMOS tube; the source electrode of the first NMOS tube is the drain electrode of the third NMOS tube; the drain electrode of the fourth NMOS tube, the drain electrode of the second PMOS tube and the grid electrode of the first PMOS tube are connected through the first contact structure; and the drain electrode of the third NMOS tube, the drain electrode of the first PMOS tube and the grid electrode of the second PMOS tube are connected through the second contact structure.

19. A semiconductor structure characterized in that it is shown by a layout according to any one of claims 1 to 11.

20. A semiconductor memory comprising the semiconductor structure of claim 19.