WO2023035470A1 - Sram memory cell layout and design method, circuit, semiconductor structure, and memory - Google Patents

Abstract

The present application provides an SRAM memory cell layout and a design method, a circuit, a semiconductor structure, and a memory. The layout comprises: a substrate; at least one active area extending along a first direction; at least one gate structure extending along a second direction, the second direction being perpendicular to the first direction; at least one contact structure, wherein the at least one contact structure is connected to two adjacent active areas in the at least one active area; and a target gate structure, the target gate structure belonging to the at least one gate structure, and the projection of the target gate structure in the substrate intersecting with the projection, in the substrate, of other active areas except the two adjacent active areas in the at least one active area. The present application can reduce the use of connecting wires, save the processing area, and improve the integration level of an integrated circuit. Moreover, the processing technology is simplified, and the risk of low yield is reduced.

Description

SRAM memory cell layout and design method, circuit, semiconductor structure, memory

Cross References to Related Applications

This application is based on the Chinese patent application with the application number 202111061849.6, the filing date is September 10, 2021, and the invention title is "SRAM memory cell layout and design method, circuit, semiconductor structure, memory", and requires the Chinese patent application Priority, the entire content of this Chinese patent application is hereby incorporated into this application as a reference.

technical field

The present disclosure relates to the field of integrated circuits, in particular to a SRAM memory cell layout and design method, circuit, semiconductor structure, and memory.

Background technique

With the development of electronic technology, the performance requirements of integrated circuits are also increasing. On the same processing area, more electronic components need to be integrated to increase the integration level of integrated circuits. At the same time, with the complexity of the integrated circuit structure, the processing technology is also more complicated, which brings the risk of low yield rate.

In integrated circuits, connecting wires are used to conduct conduction between semiconductor devices. In the process of arranging the connecting wires, it is necessary to arrange more metal materials to leave a margin space to avoid poor conduction. In this way, an additional processing area is occupied, which is not conducive to improving the integration level of the integrated circuit. At the same time, the process of arranging connection lines is relatively complicated, and there is a risk of low yield.

Contents of the invention

The embodiment of the present disclosure expects to propose a SRAM memory cell layout and design method, circuit, semiconductor structure, and memory, which can reduce the use of connecting wires, save the processing area, and improve the integration of integrated circuits; at the same time, simplify the processing technology and reduce low Yield risk.

The disclosed technical solution is achieved in this way:

An embodiment of the present disclosure provides a layout of an SRAM storage unit, the layout comprising:

Substrate;

at least one active region extending along a first direction;

at least one gate structure extending along a second direction; said second direction being perpendicular to said first direction;

at least one contact structure; where,

The at least one contact structure connects two adjacent active regions in the at least one active region and a target gate structure; the target gate structure belongs to the at least one gate structure;

The projection of the target gate structure in the substrate intersects the projections of other active regions in the at least one active region except for the two adjacent active regions in the substrate.

In some of these embodiments, the at least one active region includes: a first active region and a second active region; the at least one gate structure includes: a first gate structure; and the at least one contact structure includes : first contact structure; where,

The first contact structure connects the first active region, the second active region and the first gate structure.

In some of these embodiments, the at least one active region further includes: a third active region and a fourth active region; the at least one gate structure further includes: a second gate structure; the at least one contact The structure also includes: a second contact structure; wherein,

The projection of the first active region in the substrate and the projection of the second active region in the substrate respectively intersect with the projection of the second gate structure in the substrate; A projection of the third active region in the substrate and a projection of the fourth active region in the substrate respectively intersect with a projection of the first gate structure in the substrate;

The second contact structure connects the third active region, the fourth active region and the second gate structure.

In some of these embodiments, the layout also includes:

a third gate structure extending along the second direction;

The third contact structure, the fourth contact structure, the fifth contact structure and the sixth contact structure; wherein,

a projection of the third gate structure in the substrate intersects the projection of the first active region in the substrate;

Both the third contact structure and the fourth contact structure are located in the first active region; the third contact structure and the first contact structure are respectively located on both sides of the third gate structure; The fourth contact structure and the first contact structure are respectively located on both sides of the second gate structure;

The fifth contact structure is located in the second active region; the fifth contact structure and the first contact structure are respectively located on both sides of the second gate structure;

The sixth contact structure is located in the third gate structure.

In some of these embodiments, the layout also includes:

a fourth gate structure extending along the second direction;

The seventh contact structure, the eighth contact structure, the ninth contact structure and the tenth contact structure; wherein,

a projection of the fourth gate structure in the substrate intersects a projection of the fourth active region in the substrate;

The seventh contact structure is located in the third active region; the seventh contact structure and the second contact structure are respectively located on both sides of the first gate structure;

Both the eighth contact structure and the ninth contact structure are located in the fourth active region; the eighth contact structure and the second contact structure are respectively located on both sides of the first gate structure; The ninth contact structure and the second contact structure are respectively located on both sides of the fourth gate structure;

The tenth contact structure is located in the fourth gate structure.

In some of these embodiments, the layout also includes:

The first metal wire, the second metal wire, the third metal wire, the fourth metal wire, the fifth metal wire, the sixth metal wire, the seventh metal wire and the eighth metal wire; wherein,

The first metal wire, the second metal wire, the third metal wire, the fourth metal wire, the fifth metal wire, the sixth metal wire, the seventh metal wire and the The eighth metal wires respectively sequentially connect the third contact structure, the fourth contact structure, the fifth contact structure, the sixth contact structure, the seventh contact structure, the eighth contact structure, The ninth contact structure and the tenth contact structure.

In some of these embodiments, the at least one contact structure is L-shaped.

In some of these embodiments, the first active region, the second active region, the third active region and the fourth active region are arranged adjacently in sequence;

The first active region is symmetrical to the fourth active region; the second active region is symmetrical to the third active region; the first gate structure is symmetrical to the second The gate structure is center-symmetric; the first contact structure and the second contact structure are center-symmetric.

In some of these embodiments, the third gate structure is center-symmetric to the fourth gate structure;

The first gate structure and the third gate structure are located on the same side of the second gate structure;

The second gate structure and the fourth gate structure are located on the same side of the first gate structure.

In some of these embodiments, the source and drain regions in the fourth active region and the fourth gate structure form a first NMOS transistor;

The source and drain regions in the first active region and the third gate structure form a second NMOS transistor;

The source and drain regions in the third active region and the first gate structure form a first PMOS transistor;

The source and drain regions in the second active region and the second gate structure form a second PMOS transistor;

The source and drain regions in the fourth active region and the first gate structure form a third NMOS transistor;

The source and drain regions in the first active region and the second gate structure form a fourth NMOS transistor.

In some of these embodiments, the source of the second NMOS transistor is the drain of the fourth NMOS transistor; the first contact structure is connected to the drain of the fourth NMOS transistor and the drain of the second PMOS transistor. a drain, a gate of the first PMOS transistor, and a gate of the third NMOS transistor;

The source of the first NMOS transistor is the drain of the third NMOS transistor; the second contact structure connects the drain of the third NMOS transistor, the drain of the first PMOS transistor, and the second the gate of the PMOS transistor and the gate of the fourth NMOS transistor;

The third contact structure is connected to the drain of the second NMOS transistor;

The fourth contact structure is connected to the source of the fourth NMOS transistor;

The fifth contact structure is connected to the source of the second PMOS transistor;

The sixth contact structure is connected to the gate of the second NMOS transistor;

The seventh contact structure is connected to the source of the first PMOS transistor;

The eighth contact structure is connected to the source of the third NMOS transistor;

The ninth contact structure is connected to the drain of the first NMOS transistor;

The tenth contact structure is connected to the gate of the first NMOS transistor.

An embodiment of the present disclosure also provides a method for designing an SRAM storage unit, the method comprising:

provide the substrate;

Setting at least one active region extending along the first direction; the at least one active region includes: a first active region and a second active region;

providing at least one gate structure extending along a second direction; said second direction being perpendicular to said first direction; a first gate structure;

providing at least one contact structure; wherein,

The at least one contact structure The contact structure connects two adjacent active regions in the at least one active region and a target gate structure; the target gate structure belongs to the at least one gate structure;

The projection of the target gate structure in the substrate intersects the projections of other active regions in the at least one active region except for the two adjacent active regions in the substrate.

In some of these embodiments, the at least one active region includes: a first active region and a second active region;

The at least one gate structure includes: a first gate structure;

The at least one contact structure includes: a first contact structure contact structure; wherein,

The first contact structure connects the first active region, the second active region and the first gate structure.

In some of these embodiments, the at least one active region further includes: a third active region and a fourth active region;

The at least one gate structure further includes: a second gate structure;

The at least one contact structure further includes: a second contact structure; wherein,

The projection of the first active region in the substrate and the projection of the second active region in the substrate respectively intersect with the projection of the second gate structure in the substrate; A projection of the third active region in the substrate and a projection of the fourth active region in the substrate respectively intersect with a projection of the first gate structure in the substrate;

The second contact structure connects the third active region, the fourth active region and the second gate structure.

In some of the embodiments, after setting at least one active region extending along the first direction, the method further includes:

A third gate structure and a fourth gate structure extending along the second direction are arranged; the projection of the third gate structure in the substrate intersects with the first active region on the substrate a projection in the substrate; the projection of the fourth gate structure in the substrate intersects the projection of the fourth active region in the substrate;

A third contact structure, a fourth contact structure, a fifth contact structure, a sixth contact structure, a seventh contact structure, an eighth contact structure, a ninth contact structure and a tenth contact structure are provided; wherein the third contact structure and The fourth contact structures are located in the first active region; the fifth contact structure is located in the second active region; the sixth contact structure is located in the third gate structure; The seventh contact structure is located in the third active region; the eighth contact structure and the ninth contact structure are both located in the fourth active region; the tenth contact structure is located in the fourth in the grid structure.

In some of the embodiments, after setting the third contact structure, the fourth contact structure, the fifth contact structure, the sixth contact structure, the seventh contact structure, the eighth contact structure, the ninth contact structure and the tenth contact structure , the method also includes:

setting the first metal line, the second metal line, the third metal line, the fourth metal line, the fifth metal line, the sixth metal line, the seventh metal line and the eighth metal line Metal wire; the first metal wire, the second metal wire, the third metal wire, the fourth metal wire, the fifth metal wire, the sixth metal wire, the seventh metal wire line and the eighth metal line are sequentially connected to the third contact structure, the fourth contact structure, the fifth contact structure, the sixth contact structure, the seventh contact structure, the eighth contact structures, the ninth contact structure and the tenth contact structure.

An embodiment of the present disclosure also provides a SRAM storage unit circuit, which is characterized in that it includes: a switch unit, a first latch unit, and a second latch unit;

The switch unit, the first latch unit and the second latch unit are connected through at least one contact structure;

The first latch unit is connected to the power terminal; the second latch unit is connected to the ground terminal;

The switch unit is connected to a bit line; the switch unit also receives a word line signal; wherein,

The switch unit is configured to turn on the first latch unit and the second latch unit to the bit lines for reading and writing of stored signals;

The first latch unit and the second latch unit form a latch circuit for locking and saving the storage signal.

In some of these embodiments, the switch unit includes: a first NMOS transistor and a second NMOS transistor; the first latch unit includes: a first PMOS transistor and a second PMOS transistor; the second latch unit includes : a third NMOS transistor and a fourth NMOS transistor; the at least one contact structure includes: a first contact structure and a second contact structure;

The source of the second NMOS transistor is the drain of the fourth NMOS transistor; the source of the first NMOS transistor is the drain of the third NMOS transistor; the drain of the fourth NMOS transistor, the The drain of the second PMOS transistor is connected to the gate of the first PMOS transistor through the first contact structure; the drain of the third NMOS transistor, the drain of the first PMOS transistor and the second The gate of the PMOS transistor is connected through the second contact structure.

An embodiment of the present disclosure also provides a semiconductor structure, which is characterized in that it is shown by the layout in the above solution.

An embodiment of the present disclosure also provides a semiconductor memory, which is characterized in that it includes the semiconductor structure in the above solution.

It can be seen that the embodiments of the present disclosure provide a SRAM memory cell layout and design method, circuit, semiconductor structure, and memory. The SRAM memory cell layout includes: a substrate; at least one active region extending along a first direction; at least one gate structure extending in two directions, wherein the second direction is perpendicular to the first direction; and at least one contact structure. Wherein at least one contact structure connects two adjacent active regions in at least one active region and the target gate structure; the target gate structure belongs to at least one gate structure; the projections of the target gate structure in the substrate intersect Projections of other active regions in at least one active region except for two adjacent active regions in the substrate. In this way, the semiconductor device is directly connected through the contact structure, reducing the use of connecting wires, thereby saving the processing area and improving the integration of integrated circuits; at the same time, reducing the process of metal wiring, thus simplifying the processing technology and improving Product yield.

Description of drawings

FIG. 1 is a first schematic diagram of a SRAM memory cell layout provided by an embodiment of the present disclosure;

FIG. 2 is a second schematic diagram of a SRAM memory cell layout provided by an embodiment of the present disclosure;

FIG. 3 is a third schematic diagram of a SRAM memory cell layout provided by an embodiment of the present disclosure;

FIG. 4 is a schematic diagram 4 of a SRAM memory cell layout provided by an embodiment of the present disclosure;

FIG. 5 is a flow chart 1 of a SRAM memory cell layout design method provided by an embodiment of the present disclosure;

Fig. 6 is a flowchart two of a SRAM memory cell layout design method provided by an embodiment of the present disclosure;

FIG. 7 is a third flowchart of a layout design method for a SRAM memory cell provided by an embodiment of the present disclosure;

FIG. 8 is a first schematic diagram of a SRAM storage unit circuit provided by an embodiment of the present disclosure;

FIG. 9 is a second schematic diagram of a SRAM storage unit circuit provided by an embodiment of the present disclosure;

FIG. 10 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure will be further elaborated below in conjunction with the accompanying drawings and embodiments, and the described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained under the premise of no creative work belong to the protection scope of the present disclosure.

In the following description, references to "some embodiments" describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or a different subset of all possible embodiments, and Can be combined with each other without conflict.

If there is a similar description of "first/second" in the application documents, add the following explanation. In the following description, the terms "first/second/third" are only used to distinguish similar objects and do not mean With regard to the specific ordering of objects, it can be understood that "first/second/third" can be interchanged in specific order or sequential order if allowed, so that the embodiments of the present disclosure described here can operate in a performed in an order other than that shown or described.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure.

In an integrated circuit, various semiconductor devices are formed on a semiconductor substrate, and connecting wires are used to conduct conduction between various semiconductor devices. However, in the process of arranging the connecting wires, a part of metal material needs to be arranged at the contact position between the connecting wires and the semiconductor device to leave a margin space to avoid poor conduction and affect the performance of the integrated circuit. In this way, not only more space needs to be reserved for arranging connecting wires, but additional processing area is occupied, which is not conducive to improving the integration of integrated circuits; at the same time, the process of arranging connecting wires is more complicated, which has higher risks and leads to low yield.

FIG. 1 is a layout of a SRAM memory cell provided by an embodiment of the present disclosure. As shown in FIG. 1, the layout of the storage cell 01 includes: a substrate 11 (a blank filling area in FIG. 1); at least An active region (dotted filling region in FIG. 1 ), comprising: a first active region 1201, a second active region 1202, a third active region 1203 and a fourth active region 1204; At least one gate structure (area filled with oblique lines in FIG. 1 ), including: a first gate structure 1301 and a second gate structure 1302, wherein the second direction is perpendicular to the first direction; at least one contact structure (in FIG. 1 The area enclosed by the bold black frame) includes: the first contact structure 1401 and the second contact structure 1402 .

Wherein at least one contact structure connects two adjacent active regions in at least one active region and a target gate structure, wherein the target gate structure belongs to at least one gate structure. Referring to FIG. 1 , the target gate structure can be the first gate structure 1301, and the first contact structure 1401 connects the first active region 1201, the second active region 1202 and the first gate structure 1301; the target gate structure can also be For the second gate structure 1302 , the second contact structure 1402 connects the third active region 1203 , the fourth active region 1204 and the second gate structure 1302 .

The projection of the target gate structure on the substrate intersects the projections of other active regions in the at least one active region except two adjacent active regions on the substrate. Referring to FIG. 1, the target gate structure may be a first gate structure 1301, and the projection of the third active region 1203 in the substrate 11 and the projection of the fourth active region 1204 in the substrate 11 intersect with the first gate structure respectively. The projection of the pole structure 1301 in the substrate 11; the target gate structure can also be the second gate structure 1302, the projection of the first active region 1201 in the substrate 11 and the second active region 1202 in the substrate 11 The projections of are respectively intersected with the projections of the second gate structure 1302 in the substrate 11 .

It should be noted that the layout of an integrated circuit is a description of the plane geometry of the physical situation of the real integrated circuit, which includes the shape, area and position information of each hardware unit on the chip. That is to say, the graphics in the layout of the integrated circuit represent the hardware units and their electrical connections in the integrated circuit.

In the embodiment of the present disclosure, the circuit structure in FIG. 9 has a corresponding relationship with that in FIG. 1 . 1 and 9, the projection of the third active region 1203 on the substrate 11 and the projection of the fourth active region 1204 on the substrate 11 respectively intersect the projection of the first gate structure 1301 on the substrate 11 , representing the source and drain regions on both sides of the first gate structure 1301 in the third active region 1203, the source and drain regions on both sides of the first gate structure 1301 and the first gate structure 1301 together form the first PMOS transistor PU1 and, the source and drain regions on both sides of the first gate structure 1301 in the fourth active region 1204, the source and drain regions on both sides of the first gate structure 1301 and the first gate structure 1301 together form the third NMOS transistor PD1. The projection of the first active region 1201 in the substrate 11 and the projection of the second active region 1202 in the substrate 11 respectively intersect with the projection of the second gate structure 1302 in the substrate 11, representing the first active The source and drain regions on both sides of the second gate structure 1302 in the region 1201, the source and drain regions on both sides of the second gate structure 1302 and the second gate structure 1302 together form a fourth NMOS transistor PD2; and, the second active The source and drain regions on both sides of the second gate structure 1302 in the region 1202, the source and drain regions on both sides of the second gate structure 1302 and the second gate structure 1302 jointly form the second PMOS transistor PU2.

The first contact structure 1401 connects the first active region 1201, the second active region 1202 and the first gate structure 1301, representing the drain of the fourth NMOS transistor PD2, the drain of the second PMOS transistor PU2, the first PMOS The gate of the transistor PU1 and the gate of the third NMOS transistor PD1 are electrically connected through the first contact structure 1401 . The second contact structure 1402 connects the third active region 1203, the fourth active region 1204 and the second gate structure 1302, representing the drain of the third NMOS transistor PD1, the drain of the first PMOS transistor PU1, the second PMOS The gate of the transistor PU2 and the gate of the fourth NMOS transistor PD2 are electrically connected through the second contact structure 1402 .

In the embodiment of the present disclosure, as shown in FIG. 1 , the first active region 1201 , the second active region 1202 , the third active region 1203 and the fourth active region 1204 are arranged adjacently in sequence. The first active region 1201 and the fourth active region 1204 are center-symmetric. The second active region 1202 is symmetrical to the third active region 1203 . The first gate structure 1301 is symmetrical to the second gate structure 1302 . The first contact structure 1 401 and the second contact structure 1402 are centrally symmetrical.

Thus, the first active region 1201, the second active region 1202, the third active region 1203, the fourth active region 1204, the first gate structure 1301, the second gate structure 1303, the first contact structure 1401 and The second contact structure 1402 can set the first PMOS transistor PU1 and the second PMOS transistor PU2, the third NMOS transistor PD1 and the fourth NMOS transistor PD2 of the symmetrical semiconductor devices shown in FIG. 9, and these semiconductor devices have symmetrical electrical connections. relation.

In an embodiment of the present disclosure, as shown in FIG. 2 , the shape of at least one contact structure (ie, the first contact structure 1401 and the second contact structure 1402 ) may be L-shaped. The lengths of each side of the L-shape can be as shown in Table 1:

side	Length (nm)
A	140-150
B	60-65
C	111-15
D.	25-30
E.	46-52
f	60-65
G	100-115
h	25-30

Table 1

It can be understood that, through the first contact structure 1401, the drain of the fourth NMOS transistor PD2, the drain of the second PMOS transistor PU2, the gate of the first PMOS transistor PU1, and the gate of the third NMOS transistor PD1 are directly connected. ; Through the second contact structure 1402, the drain of the third NMOS transistor PD1, the drain of the first PMOS transistor PU1, the gate of the second PMOS transistor PU2 and the gate of the fourth NMOS transistor PD2 are directly connected. In this way, the use of connecting wires is reduced, thereby saving the processing area and improving the integration of integrated circuits; meanwhile, the process of metal wiring is reduced, thereby simplifying the processing technology and improving the product yield.

In some embodiments of the present disclosure, as shown in FIG. 3 , the memory cell layout 01 further includes: a third gate structure 1303 extending along the second direction; a third contact structure 1403 , a fourth contact structure 1404 , a Five contact structures 1405 and sixth contact structures 1406 .

Wherein, the projection of the third gate structure 1303 in the substrate 11 intersects the projection of the first active region 1201 in the substrate 11; the third contact structure 1403 and the fourth contact structure 1404 are both located in the first active region 1201 Middle; the third contact structure 1403 and the first contact structure 1401 are respectively located on both sides of the third gate structure 1303; the fourth contact structure 1404 and the first contact structure 1401 are respectively located on both sides of the second gate structure 1302; the fifth The contact structure 1405 is located in the second active region 1202 ; the fifth contact structure 1405 and the first contact structure 1401 are respectively located on two sides of the second gate structure 1302 ; the sixth contact structure 1406 is located in the third gate structure 1303 .

In the embodiment of the present disclosure, referring to FIG. 3 and FIG. 9 , the projection of the third gate structure 1303 in the substrate 11 intersects the projection of the first active region 1201 in the substrate 11, representing the first active region The source and drain regions on both sides of the third gate structure 1303 in 1201, the source and drain regions on both sides of the third gate structure 1303 and the third gate structure 1303 together form the second NMOS transistor PG2; the source of the second NMOS transistor PG2 The pole is also the drain of the fourth NMOS transistor PD2.

The third contact structure 1403 is located in the first active region 1201, and the third contact structure 1403 and the first contact structure 1401 are respectively located on both sides of the third gate structure 1303, indicating that the third contact structure 1403 is connected to the second NMOS transistor PG2 The drain of the first contact structure 1401 is connected to the source of the second NMOS transistor PG2 (also the drain of the fourth NMOS transistor PD2).

The fourth contact structure 1404 is located in the first active region 1201, and the fourth contact structure 1404 and the first contact structure 1401 are respectively located on both sides of the second gate structure 1302, which indicates that the fourth contact structure 1404 is connected to the fourth NMOS transistor PD2 The source of the first contact structure 1401 is connected to the drain of the fourth NMOS transistor PD2 (also the source of the second NMOS transistor PG2).

The fifth contact structure 1405 is located in the second active region 1202, and the fifth contact structure 1405 and the first contact structure 1401 are respectively located on both sides of the second gate structure 1302, which means that the fifth contact structure 1405 is connected to the second PMOS transistor PU2 The source of the first contact structure 1401 is connected to the drain of the second PMOS transistor PU2.

The sixth contact structure 1406 is located in the third gate structure 1303, which means that the sixth contact structure 1406 is connected to the gate of the second NMOS transistor PG2.

In some embodiments of the present disclosure, as shown in FIG. 3 , the memory cell layout 01 further includes: a fourth gate structure 1304 extending along the second direction; a seventh contact structure 1407 , an eighth contact structure 1408 , a Nine contact structures 1409 and tenth contact structures 1410 .

Wherein, the projection of the fourth gate structure 1304 in the substrate 11 intersects the projection of the fourth active region 1204 in the substrate 11; the seventh contact structure 1407 is located in the third active region 1203; the seventh contact structure 1407 The eighth contact structure 1408 and the ninth contact structure 1409 are both located in the fourth active region 1204; the eighth contact structure 1408 and the second contact structure 1402 They are respectively located on both sides of the first gate structure 1301 ; the ninth contact structure 1409 and the second contact structure 1402 are respectively located on both sides of the fourth gate structure 1304 ; the tenth contact structure 1410 is located in the fourth gate structure 1304 .

In the embodiment of the present disclosure, referring to FIG. 3 and FIG. 9 , the projection of the fourth gate structure 1304 in the substrate 11 intersects the projection of the fourth active region 1204 in the substrate 11, representing the fourth active region In 1204, the source and drain regions on both sides of the fourth gate structure 1304, the source and drain regions on both sides of the fourth gate structure 1304 and the fourth gate structure 1304 are provided with a first NMOS transistor PG1; the source of the first NMOS transistor PG1 It is also the drain of the third NMOS transistor PD1.

The seventh contact structure 1407 is located in the third active region 1203, and the seventh contact structure 1407 and the second contact structure 1402 are respectively located on both sides of the first gate structure 1301, indicating that the seventh contact structure 1407 is connected to the first PMOS transistor PU1 The source of the first PMOS transistor PU1 is connected to the second contact structure 1402 .

The eighth contact structure 1408 is located in the fourth active region 1204, and the eighth contact structure 1408 and the second contact structure 1402 are respectively located on both sides of the first gate structure 1301, which indicates that the eighth contact structure 1408 is connected to the third NMOS transistor PD1 The source of the second contact structure 1402 is connected to the drain of the third NMOS transistor PD1 (also the source of the first NMOS transistor PG1 ).

The ninth contact structure 1409 is located in the fourth active region 1204, and the ninth contact structure 1409 and the second contact structure 1402 are respectively located on both sides of the fourth gate structure 1304, which means that the ninth contact structure 1409 is connected to the first NMOS transistor PG1 The drain of the second contact structure 1402 is connected to the source of the first NMOS transistor PG1 (also the drain of the third NMOS transistor PD1).

The tenth contact structure 1410 is located in the fourth gate structure 1304 , which means that the tenth contact structure 1410 is connected to the gate of the first NMOS transistor PG1 .

In the embodiment of the present disclosure, as shown in FIG. 3 , the third gate structure 1303 and the fourth gate structure 1304 are center-symmetric. The first gate structure 1301 and the third gate structure 1303 are located on the same side of the second gate structure 1302 , and the second gate structure 1302 and the fourth gate structure 1304 are located on the same side of the first gate structure 1301 .

Therefore, the first active region 1201, the fourth active region 1204, the third gate structure 1303, the fourth gate structure 1304, the first contact structure 1401 and the second contact structure 1402 can be arranged symmetrically as shown in FIG. The first NMOS transistor PG1 and the second NMOS transistor PG2 of the semiconductor devices have a symmetrical electrical connection relationship.

It can be understood that the memory cell circuit in FIG. 9 is constructed with a new physical structure through the active region, the gate structure and the contact structure. Therefore, in the process of manufacturing the memory unit circuit, the use of connecting wires is reduced, the processing area is saved, and the integration degree of the integrated circuit is improved; at the same time, the process of metal wiring is reduced, the processing technology is simplified, and the product yield rate can be improved.

In some embodiments of the present disclosure, as shown in FIG. 4 , the memory cell layout 01 further includes:

At least one metal line (the area filled with horizontal lines in FIG. 4 ), including: a first metal line 1501, a second metal line 1502, a third metal line 1503, a fourth metal line 1504, a fifth metal line 1505, and a sixth metal line 1506 , the seventh metal line 1507 and the eighth metal line 1508 .

Among them, the first metal wire 1501, the second metal wire 1502, the third metal wire 1503, the fourth metal wire 1504, the fifth metal wire 1505, the sixth metal wire 1506, the seventh metal wire 1507 and the eighth metal wire 1508, respectively connect the third contact structure 1403, the fourth contact structure 1404, the fifth contact structure 1405, the sixth contact structure 1406, the seventh contact structure 1407, the eighth contact structure 1408, the ninth contact structure 1409 and the tenth contact structure 1410.

In the embodiments of the present disclosure, the metal wire and the contact structure are correspondingly connected, which represents the active region or the gate structure connected to the contact structure, and is electrically connected with the metal wire and other objects through the contact structure.

It can be understood that, through the use of metal wires, the electrical connection between each MOS port in the memory cell circuit and the corresponding electrical connection object is completed.

An optional flow chart of the SRAM memory cell layout design method will be described in conjunction with the steps shown in FIG. 5 .

S201, providing a substrate.

In the embodiments of the present disclosure, to design the layout of the SRAM storage unit, a substrate needs to be provided first, and the SRAM storage unit is manufactured on the substrate. A substrate is a clean single crystal semiconductor flake with specific crystal planes and appropriate electrical, optical and mechanical properties. The substrate is usually a single crystal silicon material, but it can also be other semiconductor materials.

S202. Set at least one active region extending along a first direction.

In the embodiments of the present disclosure, the designer may set at least one active region extending along the first direction on the substrate in the layout. Among them, the active area is the area where the active devices are made on the substrate; the active devices can work under the external power supply.

Referring to FIG. 1 , at least one active region may include a first active region 1201 , a second active region 1202 , a third active region 1203 and a fourth active region 1204 . The first active region 1201 , the second active region 1202 , the third active region 1203 and the fourth active region 1204 are arranged adjacently in sequence.

It should be noted that the manufacturing of the active region can be completed by the following method: the semiconductor device can dope some regions in the substrate to change the electrical characteristics of these regions to form at least one active region. Taking the substrate of single crystal silicon material as an example, doping trivalent elements such as boron (B) into the silicon substrate can form a P-type active region, which contains holes; Doping 5-valent elements, such as phosphorus (P) and arsenic (As), can form an N-type active region, and the N-type active region contains free electrons. Based on the P-type active region and the N-type active region, semiconductor devices such as PMOS and NMOS can be formed.

Among them, according to the required doping depth, diffusion (Diffusion) or ion implantation (Ion Implantation) can be selected to complete the doping of the substrate. Diffusion is to directly contact the doping element with the surface of the silicon substrate. With the assistance of thermal energy, the doping element is doped into the silicon substrate, and the doping depth of the diffusion is relatively shallow. Ion implantation is to activate the doping material into a plasma state (Plasma), and after high-energy acceleration, it is implanted into the region that needs to be doped in the silicon substrate, and the doping depth of ion implantation is relatively deep. Since ion implantation will cause lattice damage (Lattice Damage) to the silicon substrate, thermal annealing is also required to repair the lattice damage.

S203, providing at least one gate structure extending along a second direction; the second direction is perpendicular to the first direction.

In an embodiment of the present disclosure, a designer may arrange at least one gate structure extending along a second direction on the active region in the layout, wherein the second direction is perpendicular to the first direction.

Referring to FIG. 1 , at least one gate structure may include: a first gate structure 1301 and a second gate structure 1302 .

It should be noted that the gate structure includes a gate dielectric layer and other dielectric layers on the gate dielectric layer, the gate active region is under the gate dielectric layer, and the gate dielectric layer and other dielectric layers are deposited on the gate active region. . The projection of the gate structure on the substrate perpendicularly intersects the projection of the corresponding active region on the substrate. The active region forms source and drain regions on both sides of the gate structure. Miscellaneous types are the opposite. The gate structure and the source and drain regions on both sides form the MOS.

S204, setting at least one contact structure; wherein, at least one contact structure connects two adjacent active regions in at least one active region, and the target gate structure; the target gate structure belongs to at least one gate structure; the target gate The projection of the structure on the substrate intersects the projections of other active regions in the at least one active region except two adjacent active regions on the substrate.

In the embodiments of the present disclosure, after setting at least one active region and at least one gate structure, the designer can set at least one contact structure in the layout. Wherein at least one contact structure connects two adjacent active regions in at least one active region and the target gate structure. The target gate structure belongs to at least one gate structure, and the projection of the target gate structure on the substrate intersects with the projections of other active regions except two adjacent active regions in the substrate in at least one active region .

Referring to FIG. 1 , at least one contact structure may include: a first contact structure 1401 and a second contact structure 1402 . The target gate structure may be the first gate structure 1301 , and the first contact structure 1401 connects the first active region 1201 , the second active region 1202 and the first gate structure 1301 . The target gate structure can also be the second gate structure 1302 , and the second contact structure 1402 connects the third active region 1203 , the fourth active region 1204 and the second gate structure 1302 .

In an embodiment of the present disclosure, as shown in FIG. 2 , the shape of at least one contact structure (ie, the first contact structure 1401 and the second contact structure 1402 ) may be L-shaped. The lengths of each side of the L-shape may be as shown in Table 1.

It should be noted that the material of the contact structure is a conductive material, so that the corresponding regions are electrically connected, that is to say, through at least one contact structure, two adjacent active regions in at least one active region and the target gate can be connected Pole structure is electrically connected. Referring to FIG. 1, through the first contact structure 1401, the first active region 1201, the second active region 1202 and the first gate structure 1301 can be electrically connected; through the second contact structure 1402, the third active region can be connected 1203 , the fourth active region 1204 and the second gate structure 1302 are electrically connected.

Continuing to refer to FIG. 1, the projection of the third active region 1203 on the substrate 11 and the projection of the fourth active region 1204 on the substrate 11 respectively intersect with the projection of the first gate structure 1301 on the substrate 11; The projection of the first active region 1201 on the substrate 11 and the projection of the second active region 1202 on the substrate 11 respectively intersect with the projection of the second gate structure 1302 on the substrate 11 .

The first active region 1201 and the fourth active region 1204 are center-symmetric. The second active region 1202 is symmetrical to the third active region 1203 . The first gate structure 1301 is symmetrical to the second gate structure 1302 . The first contact structure 1401 is symmetrical to the second contact structure 1402 .

Thus, the first active region 1201, the second active region 1202, the third active region 1203, the fourth active region 1204, the first gate structure 1301, the second gate structure 1303, the first contact structure 1401 and The second contact structure 1402 can form a symmetrical semiconductor device such as the first PMOS transistor PU1 and the second PMOS transistor PU2, the third NMOS transistor PD1 and the fourth NMOS transistor PD2 as shown in FIG. 9, and these semiconductor devices have symmetrical electrical connections. relation.

It can be understood that, through the first contact structure 1401, the drain of the fourth NMOS transistor PD2, the drain of the second PMOS transistor PU2, the gate of the first PMOS transistor PU1, and the gate of the third NMOS transistor PD1 are directly connected. ; Through the second contact structure 1402, the drain of the third NMOS transistor PD1, the drain of the first PMOS transistor PU1, the gate of the second PMOS transistor PU2 and the gate of the fourth NMOS transistor PD2 are directly connected. In this way, the use of connecting wires is reduced, thereby saving the processing area and improving the integration of integrated circuits; meanwhile, the process of metal wiring is reduced, thereby simplifying the processing technology and improving the product yield.

In some embodiments of the present disclosure, S205 shown in FIG. 6 is further included after S202 shown in FIG. 5 , which will be described in conjunction with each step.

S205, providing a third gate structure and a fourth gate structure extending along the second direction; the projection of the third gate structure on the substrate intersects the projection of the first active region on the substrate; the fourth gate The projection of the structure on the substrate intersects the projection of the fourth active region on the substrate.

In the embodiment of the present disclosure, after setting at least one active region, the designer may also set the third gate structure and the fourth gate structure extending along the second direction on the layout.

Referring to FIG. 3, the third gate structure 1303 and the fourth gate structure 1304 are centrally symmetrical; the projection of the third gate structure 1303 on the substrate 11 intersects the projection of the first active region 1201 on the substrate 11; The projection of the fourth gate structure 1304 on the substrate 11 intersects the projection of the fourth active region 1204 on the substrate 11 .

The third gate structure 1303 is symmetrical to the fourth gate structure 1304 . The first gate structure 1301 and the third gate structure 1303 are located on the same side of the second gate structure 1302 , and the second gate structure 1302 and the fourth gate structure 1304 are located on the same side of the first gate structure 1301 .

Therefore, the first active region 1201, the fourth active region 1204, the third gate structure 1303, the fourth gate structure 1304, the first contact structure 1401 and the second contact structure 1402 can be formed symmetrically as shown in FIG. The first NMOS transistor PG1 and the second NMOS transistor PG2 of the semiconductor devices have a symmetrical electrical connection relationship.

S206, providing a third contact structure, a fourth contact structure, a fifth contact structure, a sixth contact structure, a seventh contact structure, an eighth contact structure, a ninth contact structure, and a tenth contact structure; wherein, the third contact structure and The fourth contact structures are located in the first active area; the fifth contact structure is located in the second active area; the sixth contact structure is located in the third gate structure; the seventh contact structure is located in the third active area; Both the eight-contact structure and the ninth contact structure are located in the fourth active region; the tenth contact structure is located in the fourth gate structure.

In the embodiment of the present disclosure, the designer can also set the third contact structure, the fourth contact structure, the fifth contact structure, the sixth contact structure, the seventh contact structure, the eighth contact structure, the ninth contact structure and the sixth contact structure in the layout. Ten contact structures.

Referring to FIG. 4, both the third contact structure 1403 and the fourth contact structure 1404 are located in the first active region 1201; the fifth contact structure 1405 is located in the second active region 1202; the sixth contact structure 1406 is located in the third gate structure 1303; the seventh contact structure 1407 is located in the third active region 1203; both the eighth contact structure 1408 and the ninth contact structure 1409 are located in the fourth active region 1204; the tenth contact structure 1410 is located in the fourth gate structure 1304 middle.

The third contact structure 1403 and the first contact structure 1401 are respectively located on both sides of the third gate structure 1303 , which means that the third contact structure 1403 and the first contact structure 1401 are respectively connected to the drain and source of the second NMOS transistor PG2 . The fourth contact structure 1404 and the first contact structure 1401 are located on both sides of the second gate structure 1302 respectively, which means that the fourth contact structure 1404 and the first contact structure 1401 are respectively connected to the source and drain of the fourth NMOS transistor PD2. The fifth contact structure 1405 and the first contact structure 1401 are respectively located on two sides of the second gate structure 1302 , which means that the fifth contact structure 1405 and the first contact structure 1401 are respectively connected to the source and drain of the second PMOS transistor PU2 . The sixth contact structure 1406 is connected to the gate of the second NMOS transistor PG2. The seventh contact structure 1407 and the second contact structure 1402 are respectively located on both sides of the first gate structure 1301 , which means that the seventh contact structure 1407 and the second contact structure 1402 are respectively connected to the source and drain of the first PMOS transistor PU1 . The eighth contact structure 1408 and the second contact structure 1402 are located on both sides of the first gate structure 1301 respectively, which means that the eighth contact structure 1408 and the second contact structure 1402 are respectively connected to the source and drain of the third NMOS transistor PD1. The ninth contact structure 1409 and the second contact structure 1402 are respectively located on both sides of the fourth gate structure 1304, which means that the ninth contact structure 1409 and the second contact structure 1402 are respectively connected to the drain and source of the first NMOS transistor PG1. The tenth contact structure 1410 is connected to the gate of the first NMOS transistor PG1.

It should be noted that the semiconductor device can manufacture the above-mentioned contact structure through processes such as photolithography (Photomasking) and etching (Etch). The semiconductor device can form a patterned photoresist layer based on a mask (mask) containing a specific pattern; then, based on the patterned photoresist layer, perform at least one etching with different etching selection ratios to form contact structure.

It can be understood that the memory cell circuit in FIG. 9 is constructed with a new physical structure through the active region, the gate structure and the contact structure. Therefore, in the process of manufacturing the memory unit circuit, the use of connecting wires is reduced, the processing area is saved, and the integration degree of the integrated circuit is improved; at the same time, the process of metal wiring is reduced, the processing technology is simplified, and the product yield rate can be improved.

In some embodiments of the present disclosure, S207 shown in FIG. 7 is further included after S206 shown in FIG. 6 , which will be described in conjunction with each step.

S207, setting the first metal wire, the second metal wire, the third metal wire, the fourth metal wire, the fifth metal wire, the sixth metal wire, the seventh metal wire and the eighth metal wire; the first metal wire, the second metal wire The metal wire, the third metal wire, the fourth metal wire, the fifth metal wire, the sixth metal wire, the seventh metal wire and the eighth metal wire respectively connect the third contact structure, the fourth contact structure, the fifth contact structure, A sixth contact structure, a seventh contact structure, an eighth contact structure, a ninth contact structure and a tenth contact structure.

In the embodiment of the present disclosure, after setting up the above-mentioned contact structure, the designer may set at least one metal wire on the conductive material in the layout to electrically connect with the contact structure. The at least one metal wire includes: a first metal wire, a second metal wire, a third metal wire, a fourth metal wire, a fifth metal wire, a sixth metal wire, a seventh metal wire and an eighth metal wire.

4, the first metal line 1501, the second metal line 1502, the third metal line 1503, the fourth metal line 1504, the fifth metal line 1505, the sixth metal line 1506, the seventh metal line 1507 and the eighth metal line 1508, respectively connecting the third contact structure 1403, the fourth contact structure 1404, the fifth contact structure 1405, the sixth contact structure 1406, the seventh contact structure 1407, the eighth contact structure 1408, the ninth contact structure 1409 and the tenth contact structure Structure 1410.

In the embodiments of the present disclosure, the metal wire and the contact structure are connected correspondingly, which represents the active region or the gate structure connected to the contact structure, and is electrically connected with other objects through the contact structure and the metal wire.

It can be understood that, through the use of metal wires, the electrical connection between each MOS port in the memory cell circuit and the corresponding electrical connection object is completed.

FIG. 8 is a schematic structural diagram of an optional SRAM storage unit circuit provided by an embodiment of the present disclosure. As shown in FIG. 8 , the storage unit circuit 03 includes: a switch unit 301 , a first latch unit 302 and a second latch unit 303 .

The switch unit 301, the first latch unit 302 and the second latch unit 303 are connected to point Q and point QB through at least one contact structure; the first latch unit 302 is connected to the power supply terminal V _DD ; the second latch unit 303 is connected to ground end; the switch unit 301 is connected to a bit line (bit line, BL) and an inverted bit line (bit line bar, BLB); the switch unit 301 also receives a word line signal of a word line (word line, WL).

Wherein, the switch unit 301 is configured to connect the first latch unit 302 and the second latch unit 303 to the bit lines BL and BLB in the case of being triggered by a word line signal in the read state and the write state. , to read and write the storage signal;

The first latch unit 302 and the second latch unit 303 form a latch circuit 304 for locking and storing the storage signal.

In some embodiments of the present disclosure, as shown in FIG. 9 , the switch unit 301 includes: a first NMOS transistor PG1 and a second NMOS transistor PG2; the first latch unit 302 includes: a first PMOS transistor PU1 and a second PMOS transistor PU2; the second latch unit 303 includes: a third NMOS transistor PD1 and a fourth NMOS transistor PD2; at least one contact structure includes: a first contact structure and a second contact structure.

In the embodiment of the present disclosure, referring to FIG. 3 and FIG. 9 , at least one contact structure includes: a first contact structure 1401 and a second contact structure 1402; the source of the second NMOS transistor PG2 is the drain of the fourth NMOS transistor PD2; The source of the NMOS transistor PG1 is the drain of the third NMOS transistor PD1.

The drain of the fourth NMOS transistor PD2, the drain of the second PMOS transistor PU2 and the first PMOS transistor PU1 are connected to the point QB (shown in FIG. 9 ) through the first contact structure 1401 . The drain of the third NMOS transistor PD1, the drain of the first PMOS transistor PU1 and the gate of the second PMOS transistor PU2 are connected to the point Q (shown in FIG. 9 ) through the second contact structure 1402 .

In an embodiment of the present disclosure, referring to FIG. 9 , the bit lines include a first bit line BL and a second bit line BLB, and signals of the two are inverted. The sources of the first PMOS transistor PU1 and the second PMOS transistor PU2 are also connected to the power supply terminal V _DD . The sources of the third NMOS transistor PD1 and the fourth NMOS transistor PD2 are also connected to the ground terminal. The gates of the first NMOS transistor PG1 and the second NMOS transistor PG2 are also connected to the word line WL to receive the word line signal. The drain of the first NMOS transistor PG1 is also connected to the first bit line BL; the drain of the second NMOS transistor PG2 is also connected to the second bit line BLB. Combining FIG. 3 and FIG. 9, the contact structure in FIG. 3, the corresponding connection relationship with each MOS port of the storage unit circuit 3 in FIG. 9, and the electrical connection objects are shown in Table 2:

contact structure	MOS port	electrical connection object
1401	PG2 source, PD2 drain, PU1 gate and PU2 drain		QB
1402	PG1 source, PD1 drain, PU1 drain and PU2 gate	Q
1403	PG2 drain	BLB
1404	PD2 source	ground terminal
1405	PU2 source	V DD
1406	PG2 gate		WL
1407	PU1 source	V DD
1408	PD1 source	ground terminal
1409	PG1 drain	BL
1410	PG1 gate	WL

Table 2

In the embodiment of the present disclosure, the first NMOS transistor PG1 is used to connect the drain of the first PMOS transistor PU1 and the third NMOS transistor PD1 to The drain of the second PMOS transistor PU2, the gate of the fourth NMOS transistor PD2 and the first bit line BL are turned on, so as to read and write the storage signal.

The second NMOS transistor PG2 is used to connect the drain of the second PMOS transistor PU2, the drain of the fourth NMOS transistor PD2, the first PMOS The gate of the transistor PU1 , the gate of the third NMOS transistor PD1 and the second bit line BLB are turned on for reading and writing of storage signals.

It can be understood that, through the first contact structure 1401, the drain of the fourth NMOS transistor PD2, the drain of the second PMOS transistor PU2, the gate of the first PMOS transistor PU1, and the gate of the third NMOS transistor PD1 are directly connected. ; Through the second contact structure 1402, the drain of the third NMOS transistor PD1, the drain of the first PMOS transistor PU1, the gate of the second PMOS transistor PU2 and the gate of the fourth NMOS transistor PD2 are directly connected. In this way, the use of connecting wires is reduced, thereby saving the processing area and improving the integration of integrated circuits; meanwhile, the process of metal wiring is reduced, thereby simplifying the processing technology and improving the product yield.

An embodiment of the present disclosure also provides a semiconductor structure 800 , as shown in FIG. 10 . The semiconductor structure 800 is illustrated by the layout provided in the previous embodiments. Therefore, the use of connecting wires can be reduced, the integration degree of the integrated circuit can be improved; the process of metal wiring can be reduced, the processing technology can be simplified, and the product yield rate can be improved.

An embodiment of the present disclosure also provides a semiconductor memory 900 , as shown in FIG. 10 , the semiconductor memory 900 includes at least the semiconductor structure 800 shown in FIG. 10 .

It should be noted that in this disclosure, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements , but also includes other elements not expressly listed, or also includes elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising that element.

The serial numbers of the above-mentioned embodiments of the present disclosure are for description only, and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be combined arbitrarily to obtain new method embodiments if there is no conflict. The features disclosed in several product embodiments provided in the present disclosure can be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above is only a specific implementation of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope of the present disclosure. should fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the protection scope of the claims.

Industrial Applicability

It can be seen that the embodiments of the present disclosure provide a SRAM memory cell layout and design method, circuit, semiconductor structure, and memory. The SRAM memory cell layout includes: a substrate; at least one active region extending along a first direction; at least one gate structure extending in two directions, wherein the second direction is perpendicular to the first direction; and at least one contact structure. Wherein at least one contact structure connects two adjacent active regions in at least one active region and the target gate structure; the target gate structure belongs to at least one gate structure; the projections of the target gate structure in the substrate intersect Projections of other active regions in at least one active region except for two adjacent active regions in the substrate. In this way, the semiconductor device is directly connected through the contact structure, reducing the use of connecting wires, thereby saving the processing area and improving the integration of integrated circuits; at the same time, reducing the process of metal wiring, thus simplifying the processing technology and improving Product yield.

Claims (20)

1. A SRAM memory cell layout, comprising:

   Substrate;

   at least one active region extending along a first direction;

   at least one gate structure extending along a second direction; said second direction being perpendicular to said first direction;

   at least one contact structure; where,

   The at least one contact structure connects two adjacent active regions in the at least one active region and a target gate structure; the target gate structure belongs to the at least one gate structure;

   The projection of the target gate structure in the substrate intersects the projections of other active regions in the at least one active region except for the two adjacent active regions in the substrate.
2. The SRAM memory cell layout according to claim 1, wherein said at least one active region comprises: a first active region and a second active region; said at least one gate structure comprises: a first gate structure; The at least one contact structure includes: a first contact structure; wherein,

   The first contact structure connects the first active region, the second active region and the first gate structure.
3. The SRAM memory cell layout according to claim 2, wherein said at least one active region further comprises: a third active region and a fourth active region; said at least one gate structure further comprises: a second gate structure; the at least one contact structure also includes: a second contact structure; wherein,

   The projection of the first active region in the substrate and the projection of the second active region in the substrate respectively intersect with the projection of the second gate structure in the substrate; A projection of the third active region in the substrate and a projection of the fourth active region in the substrate respectively intersect with a projection of the first gate structure in the substrate;

   The second contact structure connects the third active region, the fourth active region and the second gate structure.
4. The layout of the SRAM storage unit according to claim 3, wherein the layout further comprises:

   a third gate structure extending along the second direction;

   The third contact structure, the fourth contact structure, the fifth contact structure and the sixth contact structure; wherein,

   a projection of the third gate structure in the substrate intersects the projection of the first active region in the substrate;

   Both the third contact structure and the fourth contact structure are located in the first active region; the third contact structure and the first contact structure are respectively located on both sides of the third gate structure; The fourth contact structure and the first contact structure are respectively located on both sides of the second gate structure;

   The fifth contact structure is located in the second active region; the fifth contact structure and the first contact structure are respectively located on both sides of the second gate structure;

   The sixth contact structure is located in the third gate structure.
5. The layout of the SRAM memory cell according to claim 3 or 4, wherein the layout further comprises:

   a fourth gate structure extending along the second direction;

   The seventh contact structure, the eighth contact structure, the ninth contact structure and the tenth contact structure; wherein,

   a projection of the fourth gate structure in the substrate intersects a projection of the fourth active region in the substrate;

   The seventh contact structure is located in the third active region; the seventh contact structure and the second contact structure are respectively located on both sides of the first gate structure;

   Both the eighth contact structure and the ninth contact structure are located in the fourth active region; the eighth contact structure and the second contact structure are respectively located on both sides of the first gate structure; The ninth contact structure and the second contact structure are respectively located on both sides of the fourth gate structure;

   The tenth contact structure is located in the fourth gate structure.
6. The layout of the SRAM storage unit according to claim 5, wherein the layout further comprises:

   The first metal wire, the second metal wire, the third metal wire, the fourth metal wire, the fifth metal wire, the sixth metal wire, the seventh metal wire and the eighth metal wire; wherein,

   The first metal wire, the second metal wire, the third metal wire, the fourth metal wire, the fifth metal wire, the sixth metal wire, the seventh metal wire and the The eighth metal wires respectively sequentially connect the third contact structure, the fourth contact structure, the fifth contact structure, the sixth contact structure, the seventh contact structure, the eighth contact structure, The ninth contact structure and the tenth contact structure.
7. The SRAM memory cell layout according to claim 1, wherein the at least one contact structure is L-shaped.
8. The SRAM memory cell layout according to claim 3, wherein,

   The first active region, the second active region, the third active region and the fourth active region are arranged adjacently in sequence;

   The first active region is symmetrical to the fourth active region; the second active region is symmetrical to the third active region; the first gate structure is symmetrical to the second The gate structure is center-symmetric; the first contact structure and the second contact structure are center-symmetric.
9. The SRAM memory cell layout according to claim 5, wherein,

   The third gate structure is centrosymmetric to the fourth gate structure;

   The first gate structure and the third gate structure are located on the same side of the second gate structure;

   The second gate structure and the fourth gate structure are located on the same side of the first gate structure.
10. The SRAM memory cell layout according to claim 5, wherein,

    The source and drain regions in the fourth active region and the fourth gate structure form a first NMOS transistor;

    The source and drain regions in the first active region and the third gate structure form a second NMOS transistor;

    The source and drain regions in the third active region and the first gate structure form a first PMOS transistor;

    The source and drain regions in the second active region and the second gate structure form a second PMOS transistor;

    The source and drain regions in the fourth active region and the first gate structure form a third NMOS transistor;

    The source and drain regions in the first active region and the second gate structure form a fourth NMOS transistor.
11. The SRAM memory cell layout according to claim 10, wherein,

    The source of the second NMOS transistor is the drain of the fourth NMOS transistor; the first contact structure connects the drain of the fourth NMOS transistor, the drain of the second PMOS transistor, the first the gate of the PMOS transistor and the gate of the third NMOS transistor;

    The source of the first NMOS transistor is the drain of the third NMOS transistor; the second contact structure connects the drain of the third NMOS transistor, the drain of the first PMOS transistor, and the second the gate of the PMOS transistor and the gate of the fourth NMOS transistor;

    The third contact structure is connected to the drain of the second NMOS transistor;

    The fourth contact structure is connected to the source of the fourth NMOS transistor;

    The fifth contact structure is connected to the source of the second PMOS transistor;

    The sixth contact structure is connected to the gate of the second NMOS transistor;

    The seventh contact structure is connected to the source of the first PMOS transistor;

    The eighth contact structure is connected to the source of the third NMOS transistor;

    The ninth contact structure is connected to the drain of the first NMOS transistor;

    The tenth contact structure is connected to the gate of the first NMOS transistor.
12. A method for layout design of an SRAM memory cell, comprising:

    provide the substrate;

    providing at least one active region extending along a first direction;

    providing at least one gate structure extending along a second direction; said second direction being perpendicular to said first direction;

    providing at least one contact structure; wherein,

    The at least one contact structure connects two adjacent active regions in the at least one active region and a target gate structure; the target gate structure belongs to the at least one gate structure;

    The projection of the target gate structure in the substrate intersects the projections of other active regions in the at least one active region except for the two adjacent active regions in the substrate.
13. The SRAM memory cell layout design method according to claim 12, wherein,

    The at least one active area includes: a first active area and a second active area;

    The at least one gate structure includes: a first gate structure;

    The at least one contact structure includes: a first contact structure contact structure; wherein,

    The first contact structure connects the first active region, the second active region and the first gate structure.
14. The SRAM memory cell layout design method according to claim 13, wherein,

    The at least one active area further includes: a third active area and a fourth active area;

    The at least one gate structure further includes: a second gate structure;

    The at least one contact structure further includes: a second contact structure; wherein,

    The projection of the first active region in the substrate and the projection of the second active region in the substrate respectively intersect with the projection of the second gate structure in the substrate; A projection of the third active region in the substrate and a projection of the fourth active region in the substrate respectively intersect with a projection of the first gate structure in the substrate;

    The second contact structure connects the third active region, the fourth active region and the second gate structure.
15. The SRAM memory cell layout design method according to claim 14, wherein, after setting at least one active region extending along the first direction, the method further comprises:

    A third gate structure and a fourth gate structure extending along the second direction are arranged; the projection of the third gate structure in the substrate intersects with the first active region on the substrate a projection in the substrate; the projection of the fourth gate structure in the substrate intersects the projection of the fourth active region in the substrate;

    A third contact structure, a fourth contact structure, a fifth contact structure, a sixth contact structure, a seventh contact structure, an eighth contact structure, a ninth contact structure and a tenth contact structure are provided; wherein the third contact structure and The fourth contact structures are located in the first active region; the fifth contact structure is located in the second active region; the sixth contact structure is located in the third gate structure; The seventh contact structure is located in the third active region; the eighth contact structure and the ninth contact structure are both located in the fourth active region; the tenth contact structure is located in the fourth in the gate structure.
16. The SRAM memory cell layout design method according to claim 15, wherein said setting the third contact structure, the fourth contact structure, the fifth contact structure, the sixth contact structure, the seventh contact structure, the eighth contact structure, the After the nine-contact structure and the tenth contact structure, the method further includes:

    setting the first metal line, the second metal line, the third metal line, the fourth metal line, the fifth metal line, the sixth metal line, the seventh metal line and the eighth metal line Metal wire; the first metal wire, the second metal wire, the third metal wire, the fourth metal wire, the fifth metal wire, the sixth metal wire, the seventh metal wire line and the eighth metal line are sequentially connected to the third contact structure, the fourth contact structure, the fifth contact structure, the sixth contact structure, the seventh contact structure, the eighth contact structures, the ninth contact structure and the tenth contact structure.
17. A kind of SRAM storage unit circuit, comprising: switch unit, first latch unit and second latch unit;

    The switch unit, the first latch unit and the second latch unit are connected through at least one contact structure;

    The first latch unit is connected to the power terminal; the second latch unit is connected to the ground terminal;

    The switch unit is connected to a bit line; the switch unit also receives a word line signal; wherein,

    The switch unit is configured to turn on the first latch unit and the second latch unit to the bit lines for reading and writing of stored signals;

    The first latch unit and the second latch unit form a latch circuit for locking and saving the storage signal.
18. The SRAM storage unit circuit according to claim 17, wherein the switch unit comprises: a first NMOS transistor and a second NMOS transistor; the first latch unit comprises: a first PMOS transistor and a second PMOS transistor; The second latch unit includes: a third NMOS transistor and a fourth NMOS transistor; the at least one contact structure includes: a first contact structure and a second contact structure;

    The source of the second NMOS transistor is the drain of the fourth NMOS transistor; the source of the first NMOS transistor is the drain of the third NMOS transistor; the drain of the fourth NMOS transistor, the The drain of the second PMOS transistor is connected to the gate of the first PMOS transistor through the first contact structure; the drain of the third NMOS transistor, the drain of the first PMOS transistor and the second The gate of the PMOS transistor is connected through the second contact structure.
19. A semiconductor structure, the semiconductor structure is represented by the layout according to any one of claims 1 to 11.
20. A semiconductor memory comprising the semiconductor structure as claimed in claim 19.

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