CN117438294A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

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Publication number
CN117438294A
CN117438294A CN202210814758.3A CN202210814758A CN117438294A CN 117438294 A CN117438294 A CN 117438294A CN 202210814758 A CN202210814758 A CN 202210814758A CN 117438294 A CN117438294 A CN 117438294A
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region
doped region
gate
substrate
doped
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张卫民
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes

Abstract

The embodiment of the disclosure provides a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate; forming a first doped region and a second doped region in a substrate; forming a first grid electrode and a second grid electrode on the substrate, wherein the first grid electrode is overlapped with the first doping region, the second grid electrode is overlapped with the second doping region, the first grid electrode extends along a first direction, the second grid electrode extends along a second direction, and the first direction is perpendicular to the second direction; and performing ion implantation on the first doped region and the second doped region, forming a first implanted region in the first doped region, and forming a second implanted region in the second doped region, wherein the doping concentration of the first implanted region is smaller than that of the second implanted region. The semiconductor structure utilizes the vertical layout of the first grid electrode and the second grid electrode, the doping concentration of the formed first injection region is smaller than that of the second injection region formed in the corresponding region of the second grid electrode in the same step, and further, the on-state current of the formed transistor is different, and the stability of the semiconductor structure is improved.

Description

Semiconductor structure and preparation method thereof
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
In the field of integrated circuits, the stability of semiconductor devices is of paramount importance. There are many factors affecting the stability of a semiconductor device, for example, for Static Random-Access Memory (SRAM), static noise margin (SNM, static Noise Margin) is a key indicator for characterizing the stability, and is generally defined as the ratio of the operating current of a driving transistor to the operating current of an Access transistor. One method of improving SRAM read SNM is to use wider pull-down transistors or longer access transistors, but with the continuous expansion of technology scale, the requirement on memory footprint is higher and higher, and the method cannot meet the requirement; another approach is to perform different doping concentrations for the pull-down transistor and the access transistor, however, this requires an additional mask to achieve, which is costly.
Therefore, there is a need for a method that can increase SRAM read SNM without taking up area and without requiring additional masks.
Disclosure of Invention
The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, which can improve SRAM reading SNM and improve the stability of the semiconductor structure under the conditions of not influencing the occupied area of the semiconductor structure and not arranging an additional mask.
An embodiment of the present disclosure provides a semiconductor structure, including: providing a substrate; forming a first doped region and a second doped region in the substrate; forming a first gate and a second gate on the substrate, wherein the first gate overlaps the first doped region, the second gate overlaps the second doped region, the first gate extends along a first direction, the second gate extends along a second direction, and the first direction is perpendicular to the second direction; and performing ion implantation on the first doped region and the second doped region, forming a first implanted region in the first doped region, and forming a second implanted region in the second doped region, wherein the doping concentration of the first implanted region is smaller than that of the second implanted region.
In an embodiment, the step of performing the ion implantation comprises a first type of light doping and/or a second type of halo doping.
In an embodiment, in the first type of light doping and/or the second type of halo doping, the angle of the ion implantation is adjusted to change the doping concentration of the first implantation region, and the angle of the ion implantation is set to be an included angle between the direction of the ion implantation and the first gate.
In one embodiment, the method further comprises the following steps: and after ion implantation, carrying out heavy doping, forming a first source drain region in the first doped region, and forming a second source drain region in the second doped region.
In one embodiment, the method further comprises the following steps: forming a first mask with a first opening on the first source drain region, and forming a second mask with a second opening on the second source drain region, wherein the size of the first opening along the first direction is larger than the size of the second opening along the second direction; forming a first opening in the first source drain region and a second opening in the second source drain region by taking the first mask and the second mask as shielding materials; forming a first conductive plug in the first opening, forming a second conductive plug in the second opening, wherein the first conductive plug is connected with the first source drain region, the second conductive plug is connected with the second source drain region, and the length of the first conductive plug along the first direction is greater than the length of the second conductive plug along the second direction.
In an embodiment, in the step of forming a first mask having a first opening on the first source drain region and forming a second mask having a second opening on the second source drain region, a width of the first opening in the second direction is greater than a width of the second opening in the first direction.
In one embodiment, the method further comprises the following steps: in the step of forming the first doped region and the second doped region in the substrate, a third doped region is also formed in the substrate; in the step of forming the first grid electrode and the second grid electrode on the substrate, a third grid electrode is also formed on the substrate, the third grid electrode overlaps the third doping region, and the third grid electrode is arranged in parallel and at intervals with the first grid electrode; and the step of carrying out ion implantation on the first doped region and the second doped region further comprises the step of carrying out ion implantation on the third doped region to form a third implanted region, wherein the doping concentration of the third implanted region is smaller than that of the second implanted region.
In an embodiment, in the step of forming the first doped region and the second doped region in the substrate, a fourth doped region is further formed in the substrate, and the second gate further overlaps the fourth doped region; and in the step of performing ion implantation on the first doped region and the second doped region, performing ion implantation on the fourth doped region to form a fourth implanted region, wherein the doping concentration of the first implanted region is smaller than that of the fourth implanted region.
An embodiment of the present disclosure also provides a semiconductor structure, including: the substrate is internally provided with a first doping region and a second doping region; a first gate electrode disposed on the substrate and overlapping the first doped region, the first gate electrode extending in a first direction, a first implant region disposed in the first doped region; the second grid electrode is arranged on the substrate and overlapped with the second doped region, the second grid electrode extends along a second direction, the first direction is perpendicular to the second direction, a second injection region is arranged in the second doped region, and the doping concentration of the first injection region is smaller than that of the second injection region.
In an embodiment, the first doped region and the second doped region are of the same doping type.
In an embodiment, a length of the first gate protruding from the first doped region is smaller than a length of the second gate protruding from the second doped region.
In an embodiment, the semiconductor device further comprises a first source drain region, a second source drain region, a first conductive plug and a second conductive plug, wherein the first source drain region is arranged in the first doped region, the first conductive plug is connected with the first source drain region, the second source drain region is arranged in the second doped region, the second conductive plug is connected with the second source drain region, and the length of the first conductive plug along the first direction is greater than the length of the second conductive plug along the second direction.
In an embodiment, in a second direction, a distance from the first conductive plug edge to the first gate edge is a first distance, and in the first direction, a distance from the second conductive plug edge to the second gate edge is a second distance, the first distance being greater than the second distance.
In an embodiment, the semiconductor device further includes a third doped region and a third gate third doped region, the third doped region is disposed in the substrate, the third gate overlaps the third doped region, the third gate and the first gate are disposed in parallel and spaced apart, a set distance is provided between the first gate and the third gate, the third doped region is disposed in the third doped region, and a doping concentration of the third doped region is smaller than a doping concentration of the second doped region.
In an embodiment, the set distance is positively correlated to the height of the first gate or the third gate.
In an embodiment, a fourth doped region is further disposed in the substrate, the second gate further overlaps the fourth doped region, the doping type of the fourth doped region is the same as that of the second doped region, a fourth implantation region is disposed in the fourth doped region, and the doping concentration of the first implantation region is smaller than that of the fourth implantation region.
In an embodiment, a fifth doped region and a sixth doped region are further disposed in the substrate, the first gate further overlaps the fifth doped region, the third gate further overlaps the sixth doped region, the fifth doped region is different from the first doped region in doping type, and the sixth doped region is different from the third doped region in doping type.
According to the semiconductor structure provided by the embodiment of the disclosure, by utilizing the vertical layout of the first grid electrode and the second grid electrode, the doping concentration of the first injection region formed in the corresponding region of the first grid electrode is smaller than that of the second injection region formed in the corresponding region of the second grid electrode in the same step, so that the on-state current of the subsequently formed transistor is different, and the stability of the semiconductor structure is improved.
Drawings
Fig. 1 is a schematic step diagram of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;
FIGS. 2-8 are schematic views of a semiconductor structure formed by the main process steps of a preparation method according to an embodiment of the present disclosure;
fig. 9 is a circuit diagram of a semiconductor structure provided by an embodiment of the present disclosure.
Detailed Description
The following describes in detail the specific embodiments of the semiconductor structure and the method for manufacturing the same according to the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic step diagram of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, and fig. 2 to 8 are schematic semiconductor structures formed by main process steps in the method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. In this embodiment, the semiconductor structure may be, but is not limited to, SRAM.
Referring to fig. 1 and 2, fig. 2 is a top view, step S10, providing a substrate 200.
The substrate 200 is used to support a semiconductor device thereon. The base 200 may include a silicon substrate, a Germanium (Ge) substrate, a silicon Germanium (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc.; the substrate 200 may also be a substrate including other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc., and the substrate 200 may also be a stacked structure, such as a silicon/germanium silicon stack, etc.; in addition, the substrate 200 may be a substrate after ion implantation, and may be doped P-type or N-type; the substrate 200 may also have a plurality of peripheral devices formed therein, such as field effect transistors, capacitors, inductors, and/or diodes, etc. In this embodiment, the substrate 200 is a silicon substrate, and further includes other device structures, such as a transistor structure, a metal wiring structure, etc., but not shown because it is irrelevant to the disclosure.
Referring to fig. 1 and 3, in fig. 3, (a) is a top view, (B) is a cross-sectional view along line A-A in (a), (C) is a cross-sectional view along line B-B in (a), (D) is a cross-sectional view along line C-C in (a), and (e) is a cross-sectional view along line D-D in (a), and in step S11, a first doped region 201 and a second doped region 202 are formed in the substrate 200. In this step, a third doped region 203 is also formed.
In this step, the first, second and third doped regions 201, 201 and 203 may be formed by performing ion implantation of the first conductivity type in the substrate 200. In this embodiment, the first doped region 201, the second doped region 202 and the third doped region 203 have the same conductivity type and are P-type, and in this step, a P-type doped region may be formed by performing boron ion implantation into the substrate 200. The first doped region 201, the second doped region 202 and the third doped region 203 serve as well regions of a subsequently formed NMOS transistor.
In this embodiment, the second doped region 202 and the first doped region 201 are arranged along the first direction D1, and the first doped region 201 and the third doped region 203 are arranged along the second direction D2. The first direction D1 is perpendicular to the second direction D2, and in this embodiment, the first direction D1 is a Y direction in a cartesian coordinate system, and the second direction D2 is an X direction in the cartesian coordinate system.
It may be understood that, arranging along the first direction D1 includes arranging the second doped region 202 and the first doped region 201 opposite to each other in the first direction D1, and also includes arranging the second doped region 202 and the first doped region 201 opposite to each other in the first direction; the arrangement along the second direction D2 comprises the arrangement of the two opposite sides in the second direction D2 and the arrangement of the two opposite sides in the second direction D2 in a staggered manner. For example, the arrangement of the first doped region 201 and the third doped region 203 along the second direction D2 includes that the first doped region 201 and the third doped region 203 are disposed opposite to each other in the second direction, and also includes that the first doped region 201 and the second doped region 203 are disposed offset in the second direction.
In this embodiment, in this step, the fourth doped region 204 is also formed. For example, the fourth doped region 204 is formed by performing ion implantation of the first conductivity type in the substrate 200. The second doped region 202 and the fourth doped region 204 are arranged in the second direction D2, and the fourth doped region 204 and the third doped region 203 are arranged in the first direction D1.
The doping type of the fourth doped region 204 is the same as that of the second doped region 202, for example, both are P-type doping, and the fourth doped region 204 serves as a well region of the NMOS transistor to be formed later.
In this embodiment, in this step, a fifth doped region 205 and a sixth doped region 206 are also formed in the substrate 200. In this step, the fifth doped region 205 and the sixth doped region 206 may be formed by performing ion implantation of the second conductive type in the substrate 200. In this embodiment, the fifth doped region 205 and the sixth doped region 206 have the same conductivity type and are both N-type, and in this step, the N-type doped region may be formed by performing phosphorus ion implantation into the substrate 200. The fifth doped region 205 and the sixth doped region 206 serve as well regions for subsequently formed PMOS transistors.
In this embodiment, the fifth doped region 205 and the sixth doped region 206 are arranged along the second direction D2. The first doped region 201 and the fifth doped region 205 are arranged along the first direction D1, that is, in the first direction D1, the fifth doped region 205 and the second doped region 202 are respectively disposed at two ends of the first doped region 201. The third doped region 201 and the sixth doped region 206 are arranged along the first direction D1, that is, in the first direction D1, the sixth doped region 206 and the fourth doped region 204 are respectively disposed at two ends of the third doped region 203.
Referring to fig. 1 and 4, in fig. 4, (a) is a top view, (B) is a cross-sectional view along line A-A in (a), (C) is a cross-sectional view along line B-B in (a), (D) is a cross-sectional view along line C-C in (a), (e) is a cross-sectional view along line D-D in (a), a first gate 210 and a second gate 220 are formed on the substrate 200, the first gate 210 overlapping the first doped region 201, the second gate 220 overlapping the second doped region 202, and the first gate 210 extending along a first direction D1 and the second gate 220 extending along a second direction D2. In this embodiment, in this step, a third gate electrode 230 is further formed on the substrate 200, the third gate electrode 230 is disposed in parallel with the first gate electrode 220 at a distance, and the third gate electrode 230 overlaps the third doped region 203. In this embodiment, the first gate 210 further overlaps the fifth doped region 205, the second gate 220 further overlaps the fourth doped region 204, and the third gate 230 further overlaps the sixth doped region 206.
In this step, the first gate 210, the second gate 220 and the third gate 230 may be polysilicon gates, and the first gate 210, the second gate 220 and the third gate 230 may be formed by chemical vapor deposition. It is understood that a gate dielectric layer 300 is also required to be formed between the first, second and third gates 210, 220 and 230 and the respective doped regions of the substrate before the first, second and third gates 210, 220 and 230 are formed. The gate dielectric layer 300 is used as an isolation layer between the doped regions of the first gate 210, the second gate 220, the third gate 230 and the substrate 200.
Referring to fig. 1 and 5, in fig. 5, (a) is a top view, (B) is a cross-sectional view along line A-A in (a), (C) is a cross-sectional view along line B-B in (a), (D) is a cross-sectional view along line C-C in (a), and (e) is a cross-sectional view along line D-D in (a), ion implantation is performed in step S13 on the first doped region 201 and the second doped region 202, a first implanted region 310 is formed in the first doped region 201, and a second implanted region 320 is formed in the second doped region 202, wherein the doping concentration of the first implanted region 310 is less than the doping concentration of the second implanted region 320.
In this step, when ion implantation is performed, as shown in fig. 5 (b), the direction of ion implantation is shown by an arrow in the figure, and the direction of ion implantation forms an angle θ with the first gate 210, and the angle θ is the angle of ion implantation. When the ion implantation is performed on the first doped region 201, since the direction of the ion implantation has an angle θ with the first gate 210, a portion of the ions blocked by the first gate 210 is not implanted into the first doped region 201, and in this embodiment, the third gate 230 also blocks the ion implantation, so that more ions are not implanted into the first doped region 201, i.e. the dose of the ions implanted into the first doped region 201 is smaller than the implantation dose when the first gate 210 is not blocked. Since the first gate 210 is perpendicular to the second gate 220, the direction of the ion implantation is parallel to the plane of the second gate 220, and when the ion implantation is performed, the ions implanted into the second doped region 202 are not blocked by the second gate 220, and meanwhile, the distance between the end of the first gate 210 and the second gate 220 is large, and the blocking is not formed, the dose of the ions implanted into the second doped region 202 is normal, so that the doping concentration of the first implanted region 310 formed is smaller than the doping concentration of the second implanted region 320 under the same ion implantation dose.
In some embodiments, while performing the ion implantation, the ion implantation angle is kept unchanged, and the ion implantation is performed multiple times by rotating the ion implantation angle around the direction perpendicular to the substrate by a set angle, and the first gate 210 is blocked by the third gate 230, which is adjacent to one side of the third gate 230, and part of the ions are not implanted into the first doped region 201, so that the doping concentration of the first implanted region 310 is reduced.
The method for manufacturing a semiconductor structure according to the embodiments of the present disclosure does not need to provide a mask additionally, but utilizes the layout of the first gate 210 and the second gate 220 to realize the difference of the doping concentrations of the first implantation region 310 and the second implantation region 320. Also, in the present embodiment, the doping concentration of the first implantation region 310 is further reduced by the layout of the third gate 230 and the first gate 210.
In this embodiment, under the same ion implantation angle, the dose of the ions implanted in the first implantation region 310, that is, the doping concentration of the first implantation region 310 is positively correlated with the distance between the first gate 210 and the third gate 330, that is, the larger the distance between the first gate 210 and the third gate 330 is, the smaller the area where the first gate 210 is blocked, the larger the doping concentration of the first implantation region 310 is, the smaller the distance between the first gate 210 and the third gate 330 is, the larger the area where the first gate 210 is blocked is, and the doping concentration of the first implantation region 310 is about small.
In some embodiments, the ion implantation includes performing a first type of lightly doped (LDD) and/or a second type of HALO doped (HALO). The first type and the second type are both conductive types. In this embodiment, the first type is opposite to the conductivity type of the first doped region 201, and the second type is the same as the conductivity type of the first doped region 201.
In an embodiment, after the first type of light doping is performed in the first doped region 201 and the second doped region 202, a second type of halo doping is performed, and the doping concentration of the first type of light doping and the second type of halo doping performed in the first doped region 201 is smaller than the doping concentration of the first type of light doping and the second type of halo doping performed in the second doped region 202, which are affected by the distance between the first gate 210 and the third gate 230.
In this step, ion implantation is further performed to the third doped region 203 to form a third implanted region 330, where the doping concentration of the third implanted region 330 is less than the doping concentration of the second implanted region 320; ion implantation is performed to the fourth doped region 204 to form a fourth implanted region 340, and the doping concentration of the first implanted region 310 is smaller than the doping concentration of the fourth implanted region 340. In this embodiment, the ion implantation conductivity types of the first implantation region 310, the second implantation region 320, the third implantation region 330 and the fourth implantation region 340 are the same.
Similarly, when the third gate 230 is blocked by itself and the first gate 210 is blocked, a part of ions are not implanted into the third doped region 203, i.e., the dose of the ions implanted into the third doped region 203 is smaller than the dose of the ions when the third gate 230 is not blocked, and the doping concentration of the third implanted region 330 is smaller than the doping concentration of the second implanted region 320 at the same dose of the ion implantation. The method for manufacturing a semiconductor structure according to the embodiments of the present disclosure does not need to provide a mask additionally, but utilizes the layout of the first gate 210, the second gate 220, and the third gate 230 to realize the difference of the doping concentrations of the third implantation region 330 and the second implantation region 320.
In this embodiment, since the fourth implantation region 204 corresponds to the second gate 220, the doping concentration of the fourth implantation region 204 is the same as that of the second implantation region 202 and is greater than that of the first implantation region 201 and the second implantation region 202.
In some embodiments, the doping concentration of the first implant region 310 may be changed by adjusting the angle of the ion implantation, which is set to an angle between the direction of the ion implantation and the first gate 210. As shown in fig. 5 (b), the direction of ion implantation is shown by an arrow in the figure, and the included angle θ between the direction of ion implantation and the first gate 210 is the angle of ion implantation. The smaller the included angle θ, the larger the ion dose implanted into the first doped region 201 at the same ion implantation dose.
In this embodiment, ion implantation is further performed to the fifth doped region 205 and the sixth doped region 206 to form a fifth implanted region 350 and a sixth implanted region 360. The ion implantation conductivity type of the fifth implantation region 350 and the sixth implantation region 360 is the same, but opposite to the ion implantation conductivity type of the first implantation region 310, the second implantation region 320, the third implantation region 330 and the fourth implantation region 340.
The preparation method provided by the embodiment of the disclosure can reduce the concentration of ion implantation by utilizing the shielding effect between the grid electrodes, so that implantation regions with different doping concentrations are formed in the same step, and the current of the transistor correspondingly formed subsequently is changed.
In this embodiment, after performing ion implantation, the preparation method further includes the steps of:
referring to fig. 6, in fig. 6, (a) is a top view, (B) is a cross-sectional view along line A-A in (a), (C) is a cross-sectional view along line B-B in (a), (D) is a cross-sectional view along line C-C in (a), and (e) is a cross-sectional view along line D-D in (a), after ion implantation, heavy doping is performed, a first source drain region SD1 is formed in the first doped region 201, and a second source drain region SD2 is formed in the second doped region 202. In this step, a third source-drain region SD3 is further formed in the third doped region 203, and a fourth source-drain region SD4 is formed in the fourth doped region 204, where the conductivity types of the doped ions of the first source-drain region SD1, the second source-drain region SD2, the third source-drain region SD3, and the fourth source-drain region SD4 are the same, for example, N-type conductivity.
In this embodiment, after forming the first source drain region SD1, the second source drain region SD2, the third source drain region SD3, and the fourth source drain region SD4, the method further includes: a fifth source-drain region SD5 is formed in the fifth doped region 205, and a sixth source-drain region SD6 is formed in the sixth doped region 206, wherein the conductivity types of the doped ions of the fifth source-drain region SD5 and the sixth source-drain region SD6 are the same, for example, P-type conductivity.
Referring to fig. 7, in fig. 7, (a) is a top view, (B) is a cross-sectional view along a line A-A in (a), (C) is a cross-sectional view along a line B-B in (a), (D) is a cross-sectional view along a line C-C in (a), and (e) is a cross-sectional view along a line D-D in (a), a first mask 400 having a first opening 401 is formed on the first source drain region SD1, a second mask 500 having a second opening 501 is formed on the second source drain region SD2, and a dimension of the first opening 401 along the first direction D1 is larger than a dimension of the second opening 501 along the second direction D2.
In this step, a third mask 600 having a third opening 601 is further formed on the third source drain region SD3, a fourth mask 700 having a fourth opening 701 is formed on the fourth source drain region SD4, a fifth mask 800 having a fifth opening 801 is formed on the fifth source drain region SD5, and a sixth mask 900 having a sixth opening 901 is formed on the sixth source drain region SD 6.
In this embodiment, the size of the third opening 601 along the first direction D1 is larger than the size of the fourth opening 701 along the second direction D2. The size of the fourth opening 701 along the second direction D2 is equal to the size of the second opening 501 along the second direction D2.
In some embodiments, the width of the first opening 401 along the second direction D2 is greater than the width of the second opening 501 along the first direction D1.
In this embodiment, the first mask 400, the second mask 500, the third mask 600, the fourth mask 700, the fifth mask 800 and the sixth mask 900 are the same layer mask, while in other embodiments, the first mask 400, the second mask 500, the third mask 600, the fourth mask 700, the fifth mask 800 and the sixth mask 900 may be different layers mask.
Referring to fig. 8, in fig. 8, (a) is a top view, (B) is a cross-sectional view along line A-A in (a), (C) is a cross-sectional view along line B-B in (a), (D) is a cross-sectional view along line C-C in (a), and (e) is a cross-sectional view along line D-D in (a), a first conductive plug 402 is formed in the first opening 401, a second conductive plug 502 is formed in the second opening 501, the first conductive plug 402 is connected to the first source drain region SD1, and the second conductive plug 502 is connected to the second source drain region SD 2.
The length of the first conductive plug 402 along the first direction D1 is greater than the length of the second conductive plug 502 along the second direction D2, and the width of the first conductive plug 402 along the second direction D2 is greater than the width of the second conductive plug 502 along the first direction D1, which is affected by the sizes of the first opening 401 and the second opening 501.
In this step, a third conductive plug 602 is formed in the third opening 601 by using the third mask 600, the fourth mask 700, the fifth mask 800 and the sixth mask 900 as shielding, and the third conductive plug 602 is connected to the third source drain region SD 3; forming a fourth conductive plug 702 in the fourth opening 701, where the fourth conductive plug 702 is connected to the fourth source drain region SD 4; forming a fifth conductive plug 802 in the fifth opening 801, wherein the fifth conductive plug 802 is connected with the fifth source drain region SD 5; a sixth conductive plug 902 is formed in the sixth opening 901, and the sixth conductive plug 902 is connected to the sixth source drain region SD 6.
In this embodiment, the third conductive plug 602 has a larger dimension along the first direction D1 than the fourth conductive plug 702 due to the third opening 601 and the fourth opening 701. The dimension of the fourth conductive plug 702 along the second direction D2 is equal to the dimension of the second conductive plug 502 along the second direction D2.
After forming the first conductive plug 402, the second conductive plug 502, the third conductive plug 602, the fourth conductive plug 702, the fifth conductive plug 802, and the ninth conductive plug 902, the method of manufacturing further includes a step of removing the first mask 400, the second mask 500, the third mask 600, the fourth mask 700, the fifth mask 800, and the ninth mask 900.
The preparation method provided by the embodiment of the disclosure can form conductive plugs with different sizes in the same step, so that the transistors formed later are different.
The embodiment of the disclosure further provides a semiconductor structure, please refer to fig. 2 to 9, wherein fig. 9 is a circuit diagram of the semiconductor structure provided in the embodiment of the disclosure, and the semiconductor structure includes a substrate 200, a first gate 210, and a second gate 220.
The substrate 200 is provided with a first doped region 201 and a second doped region 202. In this embodiment, a third doped region 203, a fourth doped region 204, a fifth doped region 205, and a sixth doped region 206 are further disposed in the substrate 200. The doping types of the first doped region 201, the second doped region 201, the third doped region 203, and the fourth doped region 204 are the same, and can be used as well regions of NMOS transistors, for example, P-type doping. The doping types of the fifth doped region 205 and the sixth doped region 206 are the same, for example. All are N-type doped and can be used as a well region of the PMOS transistor.
The first gate 210 is disposed on the substrate 200 and overlaps the first doped region 201, the first gate 210 extends along a first direction D1, and a first implant region 310 is disposed in the first doped region 201. In this embodiment, a first source drain region SD1 is further disposed in the first doped region 201. The first gate 210, the first injection region 310, and the first source drain region SD1 form a first pull-down transistor PD1, and the first pull-down transistor PD1 is an NMOS transistor. In this embodiment, the first conductive plug 402 is connected to the first source drain region SD1.
The second gate 220 is disposed on the substrate 200 and overlaps the second doped region 202, the second gate 220 extends along a second direction D2, the first direction D1 is perpendicular to the second direction D2, and a second implantation region 320 is disposed in the second doped region 202. In this embodiment, a second source drain region SD2 is further disposed in the second doped region 202. The second gate 220, the second injection region 320 and the second source drain region SD2 constitute a first access transistor PG1, and the first access transistor PG1 is an NMOS transistor. In this embodiment, the second conductive plug 502 is connected to the second source drain region SD2.
In this embodiment, if the doping concentration of the first type of light doping of the first implantation region 310 is smaller than that of the second implantation region 320, the hot carrier injection effect (HCI, hot carrier injection) of the first pull-down transistor PD1 is improved; if the doping concentration of the second type of halo doping of the first injection region 310 is smaller than the doping concentration of the second type of halo doping of the second injection region 320, the on-current of the formed first pull-down transistor PD1 is larger than the on-current of the first access transistor PG1, so that the static noise margin of SRAM reading can be improved, and the stability of SRAM can be improved.
In this embodiment, the length L1 of the first conductive plug 402 along the first direction D1 is greater than the length L2 of the second conductive plug 502 along the second direction D2, the contact area of the first conductive plug 402 and the first source drain region SD1 is greater than the contact area of the second conductive plug 502 and the second source drain region SD2, and then the contact resistance of the first conductive plug 402 and the first source drain region SD1 is smaller than the contact resistance of the second conductive plug 502 and the second source drain region SD2, so that the on-current of the formed first pull-down transistor PD1 may be further greater than the on-current of the first access transistor PG 1.
In this embodiment, referring to fig. 8, in the second direction D2, the distance from the edge of the first conductive plug 402 to the edge of the first gate 210 is a first distance H1, in the first direction D1, the distance from the edge of the second conductive plug 502 to the edge of the second gate 220 is a second distance H2, and the first distance H1 is greater than the second distance H2, i.e., the first conductive plug 402 is further away from the corresponding first gate 210, so that the gate-drain coupling capacitance of the formed first pull-down transistor PD1 is further smaller than the gate-drain coupling capacitance of the first access transistor PG1, i.e., the delay time of the first pull-down transistor PD1 is smaller than the delay time of the first access transistor PG1, and thus the static noise margin of the read SRAM can be further improved, and the stability of the SRAM can be improved.
In this embodiment, the length of the first gate 210 protruding from the first doped region 201 is smaller than the length of the second gate 220 protruding from the second doped region 202. For example, referring to fig. 4, the length W1 of the first gate 210 protruding from the first doped region 201 is smaller than the length W2 of the second gate 220 protruding from the second doped region 202, so that the on-current of the formed first pull-down transistor PD1 is larger than the on-current of the first access transistor PG1, and thus the static noise margin of SRAM reading can be further improved, and the stability of SRAM can be improved.
In this embodiment, the semiconductor structure further includes a third doped region 203, a third gate 230, and a third implanted region 330. The third doped region 203 is disposed in the substrate 200, the third gate 230 overlaps the third doped region 203, and the third gate 230 is disposed in parallel with the first gate 210 at a distance. The third implant region 330 is disposed in the third doped region 203. In this embodiment, a third source drain region SD3 is further disposed in the third doped region 203. The third gate 230, the third injection region 330 and the third source drain region SD3 constitute a second pull-down transistor PD2, and the second pull-down transistor PD2 is an NMOS transistor. In this embodiment, the third conductive plug 602 is connected to the third source drain region SD3.
The doping concentration of the third injection region 330 is smaller than that of the second injection region 320, so that the on-current of the formed second pull-down transistor PD2 is larger than that of the first access transistor PG1, and the static noise margin of SRAM reading can be improved, and the stability of SRAM can be improved.
In this embodiment, a set distance E is provided between the first gate 210 and the third gate 230, and the set distance E is positively correlated to the height of the first gate 210 or the third gate 230. For example, the greater the height of the first gate 210, the greater the set distance may be, so that the doping concentrations of the first and third implant regions 201 and 203 are controlled to be smaller than the doping concentration of the second implant region 202 when the first and third implant regions 201 and 203 are formed. For example, in one embodiment, the set distance is less than 60 nanometers.
In this embodiment, a fourth doped region 204 is further disposed in the substrate 200, the second gate 220 further overlaps the fourth doped region 204, the fourth doped region 204 has the same doping type as the second doped region 202, and a fourth implantation region 340 is disposed in the fourth doped region 204. A fourth source drain region SD4 is also disposed within the fourth doped region 204. The second gate 220, the fourth injection region 340 and the fourth source drain region SD4 constitute a second access transistor PG2, and the second access transistor PG2 is an NMOS transistor. In this embodiment, the fourth conductive plug 702 is connected to the fourth source drain region SD4.
In this embodiment, the doping concentration of the first injection region 310 is smaller than the doping concentration of the fourth injection region 340, the doping concentration of the second injection region 320 is equal to the doping concentration of the fourth injection region 340, the doping concentration of the third injection region 330 is smaller than the doping concentration of the third injection region 340, so that the on-current of the first pull-down transistor PD1 and the second pull-down transistor PD2 is larger than the on-current of the second access transistor PG2, and thus the static noise margin of SRAM reading can be improved, and the stability of SRAM is improved.
In this embodiment, the structure of the second access transistor PG2 is the same as that of the first access transistor PG1, and the structure of the second pull-down transistor PD2 is the same as that of the first pull-down transistor PD1, which is not described again.
In this embodiment, the first gate 210 further overlaps the fifth doped region 205, and a fifth implantation region 350 and a fifth source drain region SD5 are further disposed in the fifth doped region 205. The first gate 210, the fifth doped region 205, and the fifth source drain region SD5 constitute a first pull-up transistor PU1, and the first pull-up transistor PU1 is a PMOS transistor. The fifth conductive plug 802 is connected to the fifth source drain region SD5.
The third gate 230 further overlaps the sixth doped region 206, and a sixth implant region 360 and a sixth source drain region SD6 are further disposed within the sixth doped region 206. The third gate 230, the sixth doped region 206 and the sixth source drain region SD6 constitute a second pull-up transistor PU2, and the second pull-up transistor PU2 is a PMOS transistor. The sixth conductive plug 902 is connected to the sixth source drain region SD6.
With continued reference to fig. 9, the gate of the first access transistor PG1 and the gate of the second access transistor PG2 are both connected to the same word line WL; the source region of the first access transistor PG1 is connected to a first bit line BL, the source region of the second access transistor PG2 is connected to a second bit line BLB, and the second bit line BLB and the first bit line BL form a pair of bit line structures that are mutually inverted. The source region of the first pull-up transistor PU1 and the source region of the second pull-up transistor PU2 are both connected to a power supply voltage Vdd, and the drain region of the first pull-up transistor PU1, the drain region of the first pull-down transistor PD1, the drain region of the first access transistor PG1, the gate of the second pull-up transistor PU2, and the gate of the second pull-down transistor PD2 are all connected to a first node Q1. The drain region of the second pull-up transistor PU2, the drain region of the second pull-down transistor PD2, the drain region of the second access transistor PG2, the gate of the first pull-up transistor PU1, and the gate of the first pull-down transistor PD1 are all connected to the second node Q2. The first node and the second node store information that is inverted and interlocked with each other. The source of the first pull-down transistor PD1 and the source of the second pull-down transistor PD2 are both grounded Vss.
The ratio of the working current of the semiconductor structure driving transistor (pull-down transistor) to the working current of the access transistor is larger, and the semiconductor structure driving transistor has higher read static noise margin and high stability.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.

Claims (17)

1. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a first doped region and a second doped region in the substrate;
forming a first gate and a second gate on the substrate, wherein the first gate overlaps the first doped region, the second gate overlaps the second doped region, the first gate extends along a first direction, the second gate extends along a second direction, and the first direction is perpendicular to the second direction; and performing ion implantation on the first doped region and the second doped region, forming a first implanted region in the first doped region, and forming a second implanted region in the second doped region, wherein the doping concentration of the first implanted region is smaller than that of the second implanted region.
2. The method of manufacturing a semiconductor structure according to claim 1, wherein the step of performing ion implantation comprises a first type of light doping and/or a second type of halo doping.
3. The method of manufacturing a semiconductor structure according to claim 2, wherein in the first type of light doping and/or the second type of halo doping, the angle of the ion implantation is adjusted to change the doping concentration of the first implantation region, the angle of the ion implantation being set to an angle between the direction of the ion implantation and the first gate.
4. The method of fabricating a semiconductor structure of claim 1, further comprising the steps of: and after ion implantation, carrying out heavy doping, forming a first source drain region in the first doped region, and forming a second source drain region in the second doped region.
5. The method of fabricating a semiconductor structure of claim 4, further comprising the steps of:
forming a first mask with a first opening on the first source drain region, and forming a second mask with a second opening on the second source drain region, wherein the size of the first opening along the first direction is larger than the size of the second opening along the second direction;
Forming a first conductive plug in the first opening, forming a second conductive plug in the second opening, wherein the first conductive plug is connected with the first source drain region, the second conductive plug is connected with the second source drain region, and the length of the first conductive plug along the first direction is greater than the length of the second conductive plug along the second direction.
6. The method of claim 5, wherein in the step of forming a first mask having a first opening over the first source drain region and forming a second mask having a second opening over the second source drain region, a width of the first opening in the second direction is greater than a width of the second opening in the first direction.
7. The method of fabricating a semiconductor structure of claim 1, further comprising the steps of:
in the step of forming the first doped region and the second doped region in the substrate, a third doped region is also formed in the substrate;
in the step of forming the first grid electrode and the second grid electrode on the substrate, a third grid electrode is also formed on the substrate, the third grid electrode overlaps the third doping region, and the third grid electrode is arranged in parallel and at intervals with the first grid electrode;
And the step of carrying out ion implantation on the first doped region and the second doped region further comprises the step of carrying out ion implantation on the third doped region to form a third implanted region, wherein the doping concentration of the third implanted region is smaller than that of the second implanted region.
8. The method of claim 7, wherein in the step of forming a first doped region and a second doped region in the substrate, a fourth doped region is further formed in the substrate, and the second gate further overlaps the fourth doped region; and in the step of performing ion implantation on the first doped region and the second doped region, performing ion implantation on the fourth doped region to form a fourth implanted region, wherein the doping concentration of the first implanted region is smaller than that of the fourth implanted region.
9. A semiconductor structure, comprising:
the substrate is internally provided with a first doping region and a second doping region;
a first gate electrode disposed on the substrate and overlapping the first doped region, the first gate electrode extending in a first direction, a first implant region disposed in the first doped region;
The second grid electrode is arranged on the substrate and overlapped with the second doped region, the second grid electrode extends along a second direction, the first direction is perpendicular to the second direction, a second injection region is arranged in the second doped region, and the doping concentration of the first injection region is smaller than that of the second injection region.
10. The semiconductor structure of claim 9, wherein the first doped region is of the same doping type as the second doped region.
11. The semiconductor structure of claim 9, wherein a length of the first gate protruding from the first doped region is less than a length of the second gate protruding from the second doped region.
12. The semiconductor structure of claim 9, further comprising a first source drain region, a second source drain region, a first conductive plug and a second conductive plug, the first source drain region disposed within the first doped region, the first conductive plug connected to the first source drain region, the second source drain region disposed within the second doped region, the second conductive plug connected to the second source drain region, the first conductive plug having a length along the first direction that is greater than a length along the second direction of the second conductive plug.
13. The semiconductor structure of claim 12, wherein in a second direction, a distance from the first conductive plug edge to the first gate edge is a first distance, and in the first direction, a distance from the second conductive plug edge to the second gate edge is a second distance, the first distance being greater than the second distance.
14. The semiconductor structure of claim 9, further comprising a third doped region disposed within the substrate, a third gate overlapping the third doped region and spaced apart from the first gate in parallel, the first gate having a set distance from the third gate, and a third implanted region disposed in the third doped region, the third implanted region having a doping concentration less than the doping concentration of the second implanted region.
15. The semiconductor structure of claim 14, wherein the set distance is positively correlated to a height of the first gate or the third gate.
16. The semiconductor structure of claim 14, wherein a fourth doped region is further disposed within the substrate, the second gate further overlaps the fourth doped region, the fourth doped region is of the same doping type as the second doped region, a fourth implanted region is disposed within the fourth doped region, and the doping concentration of the first implanted region is less than the doping concentration of the fourth implanted region.
17. The semiconductor structure of claim 16, wherein a fifth doped region and a sixth doped region are further disposed within the substrate, the first gate further overlaps the fifth doped region, the third gate further overlaps the sixth doped region, the fifth doped region is of a different doping type than the first doped region, and the sixth doped region is of a different doping type than the third doped region.
CN202210814758.3A 2022-07-12 2022-07-12 Semiconductor structure and preparation method thereof Pending CN117438294A (en)

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