CN115776820A - Semiconductor structure and manufacturing method thereof, memory and memory system - Google Patents

Abstract

The embodiment of the disclosure discloses a semiconductor structure, a manufacturing method thereof and a memory, wherein the semiconductor structure comprises: the semiconductor device comprises a first semiconductor layer, an isolation structure and a second semiconductor layer which are sequentially stacked; at least one first device, a part of the structure of the first device is positioned in the first semiconductor layer; at least one second device, a partial structure of the second device being located in the second semiconductor layer.

Description

Semiconductor structure and manufacturing method thereof, memory and memory system

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor structure, a method for manufacturing the same, a memory, and a memory system.

Background

As a typical nonvolatile semiconductor memory, a NAND (Not-And) flash memory has become a mainstream product in the memory market due to its high memory density, controllable production cost, appropriate erasing speed, and retention characteristics. However, semiconductor memories also face a number of challenges.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor structure, a method of manufacturing the same, a memory and a memory system.

According to an aspect of the present disclosure, there is provided a semiconductor structure including:

the semiconductor device comprises a first semiconductor layer, an isolation structure and a second semiconductor layer which are sequentially stacked;

at least one first device, a part of the structure of the first device is positioned in the first semiconductor layer;

at least one second device, a partial structure of the second device being located in the second semiconductor layer.

In the above scheme, the operating voltage of the first device is higher than the operating voltage of the second device.

In the foregoing solution, the semiconductor structure further includes:

and the connecting structure is positioned on one side of the first device and the second device and penetrates through the second semiconductor layer, the isolation structure and the first semiconductor layer, and the connecting structure is electrically connected with the first device.

In the above scheme, the isolation structure comprises a gas isolation material and/or a solid isolation material.

In the above scheme, the isolation structure comprises a gas isolation material and a solid isolation material; wherein the isolation structures of the first and second devices at an orthographic projection of a plane in which the isolation structures are located comprise a gas isolation material.

In the above scheme, the semiconductor structure further includes:

the first insulating layer covers the surface, far away from the isolation structure, of the first semiconductor layer;

the first device includes: the first doped region is located in the first semiconductor layer, and the first gate structure and the first interconnection structure are located in the first insulating layer at positions corresponding to the first doped region.

In the above scheme, the semiconductor structure further includes:

the second insulating layer covers the surface, far away from the isolation structure, of the second semiconductor layer;

the second device includes: the second doped region is located in the second semiconductor layer, and the second gate structure and the second interconnection structure are located in the second insulating layer at positions corresponding to the second doped region.

According to another aspect of the present disclosure, there is provided a memory including: a memory array and peripheral circuitry coupled with the memory array; wherein the peripheral circuit comprises any of the semiconductor structures of the above aspects.

According to another aspect of the present disclosure, there is provided a storage system including: one or more of the above-described memories; and

a memory controller coupled with and controlling the memory.

According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor structure, the method comprising:

providing a base structure, wherein the base structure comprises a first surface and a second surface which are oppositely arranged, and at least one first device is formed at the first surface;

thinning the base structure from the second surface;

forming a second semiconductor layer on the thinned second surface;

forming at least one second device in the second semiconductor layer;

an isolation structure is formed between the first semiconductor and the second semiconductor.

In the foregoing solution, the forming the isolation structure includes:

before forming the second semiconductor layer, forming a sacrificial layer on the thinned second surface; after the second semiconductor layer is formed, removing the sacrificial layer to form the isolation structure;

forming a second semiconductor layer on the thinned second surface, including:

and forming the second semiconductor layer on the sacrificial layer through an epitaxial process.

In the foregoing solution, the forming the isolation structure includes:

filling an isolation material at the position where the sacrificial layer is removed to form an isolation structure; the isolation material comprises a gas isolation material and/or a solid isolation material.

In the above solution, etching selection ratios of the material of the sacrificial layer to the material of the substrate structure and the material of the second semiconductor layer are different.

In the above scheme, the base structure includes a substrate and a first semiconductor layer stacked, and a surface of the substrate away from the first semiconductor layer is a second surface of the base structure; forming the first semiconductor layer by an epitaxial process;

thinning the base structure from the second surface includes:

and removing the substrate through an etching process, wherein etching is stopped on the surface of the first semiconductor layer.

In the above aspect, forming the first device includes: forming a first doped region in the first semiconductor layer; forming a first insulating layer on the surface of the first semiconductor layer far away from the substrate, and forming a first grid structure corresponding to the first doping region and a first interconnection structure electrically connected with the first grid structure and the first doping region in the first insulating layer.

In the above scheme, forming the second device includes: forming a second doped region in the second semiconductor layer; and forming a second insulating layer on the surface of the second semiconductor layer far away from the substrate structure, and forming a second grid structure corresponding to the second doping region and a second interconnection structure electrically connected with the second grid structure and the second doping region in the second insulating layer.

In the foregoing solution, the method further includes: and forming a connection structure penetrating through the second semiconductor layer, the isolation structure and the base structure on one side of the first device and the second device, wherein the connection structure is electrically connected with the first device.

In the above aspect, forming the connection structure includes:

forming a via hole penetrating through the second insulating layer, the second semiconductor layer, the isolation structure, the first semiconductor layer and extending into the first insulating layer;

and filling a conductive material in the through hole to form a connecting structure, wherein the connecting structure is electrically connected with the first interconnection structure.

In the above scheme, the method further comprises:

forming a carrier at a surface of the first device remote from the second surface before thinning the base structure from the second surface.

The embodiment of the disclosure provides a semiconductor structure, a manufacturing method thereof, a memory and a memory system. In the embodiments of the present disclosure, the formed first device and the second device are respectively located on two sides of the sacrificial layer, and an isolation structure is formed by removing the sacrificial layer, so that the first device and the second device are isolated by the isolation structure. That is, in the implementation of the present disclosure, an isolation structure is disposed between the first device and the second device, so as to prevent mutual crosstalk between the two devices; compared with the method for isolating the first device from the second device by using a semiconductor material, the isolation structure has a better isolation effect, and meanwhile, a thinner isolation structure can play a better isolation role, so that the thinner isolation structure can provide favorable process conditions for the formation of a subsequent connection structure, and the process difficulty of the connection structure is reduced.

Drawings

FIG. 1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

FIG. 2a is a schematic diagram of an exemplary memory card with a memory system according to an embodiment of the present disclosure;

FIG. 2b is a schematic diagram of an exemplary solid state drive with a memory system according to an embodiment of the present disclosure;

fig. 3 is a schematic cross-sectional view of a part of a peripheral circuit of a memory according to an embodiment of the present disclosure;

fig. 4 is a schematic flow chart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 5-16 are schematic cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the present disclosure.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be further elaborated with reference to the drawings and the embodiments. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, and are provided solely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.

It is understood that the meaning of "on 8230; \8230on", "on 82308230; \8230, above and" on 8230; \8230303030a "above" in this disclosure should be interpreted in the broadest manner such that "on 8230; \8230above" not only means its meaning of "on something" with no intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of "on" something with intervening features or layers therebetween.

Moreover, spatially relative terms such as "on 8230; \8230; above", "on 8230; above", "on", "upper", etc., may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In embodiments of the present disclosure, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a variety of semiconductor materials, such as silicon, silicon germanium, arsenic, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The layer may comprise a plurality of sub-layers. For example, the interconnect layer may include one or more conductors and contact sub-layers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sub-layers.

In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.

Fig. 1 illustrates a block diagram of an example system 100 with memory in accordance with some aspects of the present disclosure. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual Reality (VR) device, augmented Reality (AR) device, or any other suitable electronic device having storage therein. As shown in fig. 1, system 100 may include a host 108 and a memory system 102, memory system 102 having one or more memories 104 and a memory controller 106. Host 108 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on a chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. Host 108 may be configured to send data to memory 104 or receive data from memory 104.

According to some embodiments, memory controller 106 is coupled to memory 104 and host 108, and is configured to control memory 104. Memory controller 106 may manage data stored in memory 104 and communicate with host 108. In some implementations, the memory controller 106 is designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, compact Flash (CF) card, universal Serial Bus (USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and so forth. In some implementations, the memory controller 106 is designed for operation in a high duty cycle environment SSD or embedded multimedia card (eMMC) that is used as a data store and enterprise storage array for mobile devices such as smart phones, tablet computers, laptop computers, and the like.

The memory controller 106 and the one or more memories 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of end electronic products. In one example as shown in FIG. 2a, the memory controller 106 and the single memory 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like. Memory card 202 may also include a memory card connector 204 that couples memory card 202 with a host (e.g., host 108 in FIG. 1). In another example as shown in fig. 2b, the memory controller 106 and the plurality of memories 104 may be integrated into the SSD 206. SSD206 can also include an SSD connector 208 that couples SSD206 with a host (e.g., host 108 in fig. 1). In some implementations, the storage capacity and/or operating speed of SSD206 is greater than the storage capacity and/or operating speed of memory card 202.

In some embodiments, the memory 104 may comprise a three-dimensional NAND-type memory. The three-dimensional NAND type memory is a main development direction in the current memory field, wherein memory cells are stacked in a direction perpendicular to a substrate, more memory cells can be formed in a smaller area, and the memory cells have larger storage capacity compared with a traditional two-dimensional memory.

With the development of three-dimensional NAND type memory technology, the number of layers of three-dimensional NAND stacks is continuously increased, a memory part is continuously improved, and the corresponding peripheral circuit is improved to adapt to the memory part, so that higher requirements are put on the reduction of the area of the peripheral circuit part, and the wide attention is paid to how to reduce the area of the peripheral circuit part. The memory 104 may include a memory array and peripheral circuitry coupled to the memory array. Still taking the memory array as a three-dimensional NAND-type memory array as an example for illustration, fig. 3 shows a schematic partial cross-sectional view of a peripheral circuit of a memory according to an embodiment of the disclosure. As shown in fig. 3, the peripheral circuits may include Low Voltage/ultra Low Voltage (LV/LLV) devices and High Voltage (HV) devices, which are classified according to the operating voltages of the devices, the Low Voltage/Low Voltage (LV/LLV) devices and the High Voltage (HV) devices are disposed on the front and back sides of the wafer, and the embedded circuits are led out Through a Through-Silicon Via (TSV) technology. In FIG. 3, LV/LLV device 301 and HV device 302 are formed on both sides of substrate 300. Compared with the LV/LLV device 301 and the HV device 302 simultaneously disposed on one side of the substrate 300, the three-dimensional structure in which the LV/LLV device 302 and the HV device 301 are disposed on the front and back sides of the substrate 300 is more favorable for reducing the area occupied by the peripheral circuit.

However, in the method of forming the LV/LLV device 302 and the HV device 301 on the front and back sides of the substrate 300, on one hand, a sufficiently thick substrate is reserved between the LV/LLV device 302 and the HV device 301 to prevent the mutual crosstalk between the LV/LLV device 302 and the HV device 301, that is, the distance between the LV/LLV device 302 and the HV device 301 along the thickness direction of the substrate is large, and at this time, the sufficiently thick substrate causes difficulty in the formation of the subsequent connection structure 303, that is, the difficulty in the process of electrically leading out the HV device 301 from one side of the substrate to the other side of the substrate is large; on the other hand, in the process of thinning the substrate, a barrier layer cannot be formed, so that the uniformity of the thinned substrate is poor, and the requirement of a Depth of Field (DOF) window of lithography in a subsequent process such as a TSV process is difficult to meet.

Accordingly, to solve one or more of the above problems, embodiments of the present disclosure provide a method for fabricating a semiconductor structure, which can effectively reduce mutual interference between a first device and a second device, and also reduce difficulty in electrically leading out the first device. Fig. 4 is a schematic flow chart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. As shown in fig. 4, a method for fabricating a semiconductor structure according to an embodiment of the present disclosure includes the following steps:

s100: providing a base structure, wherein the base structure comprises a first surface and a second surface which are oppositely arranged, and at least one first device is formed at the first surface;

s200: thinning the base structure from the second surface;

s300: forming a second semiconductor layer on the thinned second surface;

s400: forming at least one second device in the second semiconductor layer;

s500: an isolation structure is formed between the first semiconductor layer and the second semiconductor layer.

It should be understood that the steps shown in FIG. 4 are not exclusive, and other steps may be performed before, after, or between any of the steps in the operations shown; the steps shown in fig. 4 may be sequentially adjusted according to actual needs. Fig. 5 to 16 are schematic cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the present disclosure. It should be noted that fig. 5 to fig. 16 are schematic views illustrating a complete implementation process of a manufacturing method of a semiconductor structure, and parts not labeled in some of the drawings may be shared with each other. The method for fabricating the semiconductor structure according to the embodiment of the present disclosure is described in detail below with reference to fig. 4 and 5 to 16.

In step S100, a first device is formed on a first surface of the base structure.

In some embodiments, the base structure may include a substrate and a first semiconductor layer stacked on the substrate, the first semiconductor layer may be an epitaxial layer formed on the substrate by an epitaxial process, a surface of the first semiconductor layer away from the substrate is a first surface of the base structure, and a surface of the substrate away from the first semiconductor layer is a second surface of the base structure. The thickness of the first semiconductor layer, relative to the substrate, can be conveniently controlled by controlling the epitaxial process, illustratively the thickness of the first semiconductor layer is less than the thickness of the substrate. The substrate may include a substrate of elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.); the first semiconductor layer may include a substrate of elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.). In some specific examples, the substrate and the first semiconductor layer are both silicon; preferably, the doping concentration of the substrate silicon is different from the doping concentration of the first semiconductor layer silicon. It is understood that the doping concentration of the substrate silicon is different from that of the first semiconductor layer silicon, which can facilitate etching in the subsequent process.

In some embodiments, forming a first device on a first surface of the base structure comprises:

forming a first doped region in the first semiconductor layer; and forming a first insulating layer on the surface of the first semiconductor layer far away from the substrate, and forming a first grid structure corresponding to the first doping region and a first interconnection structure electrically connected with the first grid structure and the first doping region in the first insulating layer.

The formation of the first device will be described in detail below with reference to fig. 5 to 6.

As shown in fig. 5, a first doped region 503 is formed in the first semiconductor layer 502 of the base structure 50.

In some embodiments, the method of forming the first doping region 503 includes, but is not limited to, a doping process, a diffusion process, and the like.

Illustratively, a P-well or an N-well is formed in the first semiconductor layer 502 by means of diffusion, and then a source and a drain are formed in the P-well or the N-well by means of ion implantation.

Next, as shown in fig. 6, a first gate structure 504 is formed on the surface of the first semiconductor layer, away from the substrate, of the corresponding first doping region 503, then a first insulating layer 506 covering the first gate structure 504 is formed, and next, a first interconnection structure 505 connected to the first gate structure and the first doping region is formed in the first insulating layer 506.

In some embodiments, as shown in fig. 6, the method further comprises forming an interconnect layer 505' in the first insulating layer 506, the first interconnect structures 505 each being connected to the interconnect layer 505', the interconnect structures subsequently being electrically connected to the first interconnect structure 505 of the first device through the interconnect layer 505 '.

In some embodiments, the first gate structure 504 may include a gate oxide layer on the surface of the first semiconductor layer of the first doped region 503 away from the substrate, and a gate on the gate oxide layer. The first gate structure 504 may further include: and the protective side walls are positioned on two sides of the grid electrode.

The material of the gate includes a metallic material or a semiconductor conductive material, such as copper (Cu), cobalt (Co), tungsten (W), molybdenum (Mo), doped silicon, polysilicon, or any combination thereof, and the like.

In some embodiments, the method of forming the first insulating layer 506 includes one or more of photolithography, deposition, such as chemical vapor deposition, physical vapor deposition, etc., etching, etc.

In some embodiments, methods of forming the first gate structure 504 include, but are not limited to, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), and the like. In some embodiments, the material of the first insulating layer 506 includes silicon oxide (SiO) ₂ ) Silicon nitride, and the like.

In some embodiments, the first insulating layer comprises a first sub-insulating layer, a second sub-insulating layer, and a third sub-insulating layer; the method of forming the first interconnect structure 505, the interconnect layer 505', includes: forming a first sub-insulating layer wrapping the first gate structure; forming a first groove penetrating through the first sub-insulating layer and respectively connected with the first gate structure and the first doped region, and filling a conductive material in the first groove to form a first interconnection structure 505; a second sub-insulating layer is formed on the first sub-insulating layer, an interconnect layer 505' connected to the first interconnect structure 505 is formed in the second sub-insulating layer, and a third sub-insulating layer is formed on the second sub-insulating layer.

In some embodiments, the material of the first interconnect structure 505 comprises a metal, such as copper (Cu), cobalt (Co), tungsten (W), molybdenum (Mo), and the like.

In step S200, the base structure is mainly thinned.

In some embodiments, a carrier is formed on a surface of the first insulating layer remote from the first semiconductor layer before thinning the base structure from the second surface.

Next, in some embodiments, thinning the base structure from the second surface comprises:

and removing the substrate through an etching process, wherein etching is stopped on the surface of the first semiconductor layer.

The thinning process of the base structure will be described in detail with reference to fig. 7 to 9. As shown in fig. 7, a carrier 507 is formed on the surface of the first insulating layer away from the first semiconductor layer.

In some embodiments, the material of the carrier 507 includes silicon (Si), germanium (Ge), and the like.

In some embodiments, the substrate may be silicon bonded to the surface of the first semiconductor layer by means of bonding.

The semiconductor structure after formation of carrier 507 is then placed upside down with carrier 507 placed below, as shown in fig. 8.

It will be appreciated that when the base structure is subsequently thinned, the carrier 507 acts as a support plane to provide protection for the first device formed, so as to prevent damage to the first device when the base structure is thinned.

Next, as shown in fig. 9, the semiconductor structure under the carrier 507 is thinned, the substrate 501 is removed by an etching process, and the etching is stopped on the surface of the first semiconductor layer 502.

In some embodiments, the etching process used includes dry etching and wet etching.

Illustratively, the substrate 501 is removed by wet etching, and the etching is stopped at the surface of the first semiconductor layer 502.

It is understood that when the doping concentration of the first semiconductor layer silicon 502 is different from that of the substrate silicon 501, the etching selectivity is different. The substrate 501 can be removed quickly by wet etching and the difference between the etching selectivity of the wet etching and the etching selectivity of the wet etching, so that the time spent on the substrate is shorter than that spent on the substrate subjected to direct chemical mechanical polishing, and meanwhile, the problem of poor thickness uniformity of the processed base structure is solved.

In addition, the first device can be easily stopped on the thin first semiconductor layer through wet etching, and compared with the case that the first device is directly formed in the substrate, the thickness of the carrier where the first device is located can be controlled more conveniently.

In step S300, a second semiconductor layer is mainly formed.

In some embodiments, a sacrificial layer is formed on the thinned second surface prior to forming the second semiconductor layer.

As shown in fig. 10, a sacrificial layer 508 is sequentially stacked on the thinned second surface.

In some embodiments, the sacrificial layer 508 is formed by a method including, but not limited to, chemical vapor deposition, physical vapor deposition, and the like.

Next, in some embodiments, the second semiconductor layer is formed on the sacrificial layer. Methods of forming the second semiconductor layer 509 include, but are not limited to, epitaxial growth, chemical vapor deposition, physical vapor deposition, and the like. Preferably, the second semiconductor layer 509 is formed on the sacrificial layer by an epitaxial process.

In some embodiments, the material of the second semiconductor layer 509 includes silicon (Si), germanium (Ge), and the like.

In some embodiments, the etching selectivity ratio of the material of the sacrificial layer to the material of the base structure and the second semiconductor layer is different. Here, the etching selectivity ratio of the material of the sacrificial layer 508 to the material of the base structure 50 and the second semiconductor layer 509 is different, so that the sacrificial layer 508 is easy to be removed separately while the material of the base structure 50 and the second semiconductor layer 509 remains. In some embodiments, the material of the sacrificial layer 508 includes, but is not limited to, silicon germanium (SiGe).

It should be noted that, the sacrificial layer, such as silicon germanium (SiGe), has a fixed lattice constant and crystal orientation, and the lattice constant and crystal orientation are relatively matched with those of the second semiconductor layer, such as single crystal silicon, so as to provide a growth plane and a support plane for the epitaxial growth of the second semiconductor layer, and simultaneously, increase the uniformity of the wafer thickness.

In step S400, a second device is mainly formed in the second semiconductor layer.

Here, the operating voltage of the second device is different from the operating voltage of the first device.

In some embodiments, forming the second device comprises: forming a second doped region in the second semiconductor layer; and forming a second insulating layer on the surface of the second semiconductor layer far away from the sacrificial layer, and forming a second grid structure corresponding to the second doped region and a second interconnection structure electrically connected with the second grid structure and the second doped region in the second insulating layer.

The formation process of the second device will be described in detail with reference to fig. 11 to 12.

As shown in fig. 11, a second doped region 510 is formed in the second semiconductor layer 509.

In some embodiments, the method of forming the second doped region 510 includes, but is not limited to, a doping process, a diffusion process, and the like.

Illustratively, a P-well or an N-well is formed in the second semiconductor layer 509 by means of diffusion, and then a source and a drain are formed in the P-well or the N-well by means of ion implantation.

Next, as shown in fig. 12, a second gate structure 511 is formed on the surface of the corresponding second doped region 510 away from the surface of the sacrificial layer, then a second insulating layer 512 is formed to cover the second gate structure 511, and then a second interconnection structure 513 connected to the second gate structure 511 and the second doped region 510 is formed in the second insulating layer 512.

In some embodiments, as shown in fig. 12, the method further comprises forming an interconnect layer in the second insulating layer 512, the second interconnect structures 513 each being connected to the interconnect layer and subsequently connected to electrical signals through the interconnect layer.

In some embodiments, the second gate structure 511 may include a gate oxide layer on a surface of the second semiconductor layer of the second doped region 510 away from the first semiconductor layer, and a gate on the gate oxide layer. The second gate structure 511 may further include: and the protective side walls are positioned on two sides of the grid electrode.

The material of the gate includes a metal material or a semiconductor conductive material, for example, copper (Cu), cobalt (Co), tungsten (W), molybdenum (Mo), doped silicon, polysilicon, or any combination thereof, and the like.

Here, the composition, material, and formation method of the second insulating layer 512 are similar to those of the first insulating layer, and thus are not described in detail.

Here, the composition, material, and formation method of the second gate structure 511 are similar to those of the first gate structure, and thus, detailed description thereof is omitted.

Here, the composition, material, and formation method of the second interconnect structure are similar to those of the first interconnect structure, and thus, detailed description thereof is omitted.

In some embodiments, the operating voltage of the first device is higher than the operating voltage of the second device.

It can be understood that the peripheral circuit is split and redistributed according to the working voltage of the device, and is respectively arranged on different planes, and then three-dimensionally stacked, so that the voltage is conveniently provided for the devices on different planes. Because the storage structure is formed by stacking above the second device and the ion implantation and activation are performed on the semiconductor in the subsequent process, the first device with higher operating voltage is arranged on the side far away from the storage structure, and can bear the high voltage applied by the ion implantation and activation.

In step S500, an isolation structure is mainly formed.

In some embodiments, forming an isolation structure comprises:

filling an isolation material at the position where the sacrificial layer is removed to form an isolation structure; the barrier material comprises a gas barrier material and/or a solid barrier material.

As shown in fig. 13, a recess 514 is formed, the recess 514 extending through at least the sacrificial layer 508.

In some embodiments, the method of removing the sacrificial layer includes, but is not limited to, wet etching.

Illustratively, a groove 514 is formed through the second insulating layer 512, the second semiconductor layer 509, and the sacrificial layer 508 by dry etching, and then the sacrificial layer 508 is removed by wet etching to form an isolation structure 515.

Here, the etching selectivity of the sacrificial layer silicon germanium (SiGe) is different from that of the silicon first semiconductor layer 502 and the silicon second semiconductor layer 509, and the sacrificial layer silicon germanium (SiGe) can be easily removed without damaging the silicon first semiconductor layer 502 and the silicon second semiconductor layer 509.

At this time, the isolation structure 515 formed by removing the sacrificial layer 508 is filled with air, and in some embodiments, the isolation structure 515 is filled with a gas isolation material including, but not limited to, an inert gas and nitrogen.

In some embodiments, the isolation structure 515 formed by removing the sacrificial layer 508 may be filled with a solid isolation material, including but not limited to an insulating material, such as silicon oxide, silicon nitride.

In some embodiments, the method of filling the isolation structure 515 with an insulating material includes, but is not limited to, atomic Layer Deposition (ALD).

In some embodiments, the isolation structure comprises a gas isolation material and a solid isolation material; wherein the isolation structures of the first and second devices at an orthographic projection of a plane in which the isolation structures are located comprise gas isolation materials.

Illustratively, the isolation structure 515 formed by removing the sacrificial layer 508 may be filled with an insulating material, such as silicon oxide, by atomic layer deposition, for example, only a portion around the formed recess 514 is filled, and the rest portions, such as the orthographic projection of the first device and the second device on the plane of the isolation structure, are filled with air, as shown in fig. 14; alternatively, at the location where the sacrificial layer 508 is removed, a layer of solid barrier material 515' is formed, and the remaining space is filled with a gas barrier material, as shown in fig. 15.

Illustratively, as shown in FIG. 13, the entire insulation structure is filled with a gas material; as shown in fig. 16, the entire isolation structure is filled with a solid material.

It can be understood that the conductivity of the inert gas, the insulating material, is less than the conductivity of the semiconductor material, silicon, which can effectively prevent crosstalk between the first device and the second device during operation; through the arrangement of the isolation structure, the distance between the first device and the second device can be reduced, the distance is reduced, the process difficulty is reduced for penetrating through the silicon through hole in the subsequent process step, and optical alignment and etching are facilitated.

Meanwhile, the thicknesses of the semiconductor structures of the first device and the second device formed by depositing the sacrificial layer and the second semiconductor layer are more uniform, the process difficulty is further reduced by penetrating through silicon vias in subsequent process steps, and the uniformity of the thickness of the semiconductor structures meets the Depth of Field (DOF) window of photoetching.

Furthermore, the isolation material filled between isolation structures 515 may be used as a support to provide a platform for the second device, thereby maintaining stability of the overall semiconductor structure.

Next, a connection structure is mainly formed, and the electrical connection of the first device is achieved through the connection structure.

In some embodiments, a connection structure is formed through the second semiconductor layer, the isolation structure, and the base structure on one side of the first and second devices, the connection structure electrically connecting the first devices.

Specifically, a through hole penetrating through the second insulating layer, the second semiconductor layer, the isolation structure, the first semiconductor layer and extending into the first insulating layer is formed;

and filling a conductive material in the through hole to form a connecting structure, wherein the connecting structure is electrically connected with the first interconnection structure.

The via formed here to penetrate through the second insulating layer, the second semiconductor layer, the isolation structure, the first semiconductor layer, and extend into the first insulating layer may be a through-silicon via. The isolation structure reduces the difficulty for realizing the through silicon via process.

In some embodiments, the vias required to form the connecting structures may be performed simultaneously with the removal of the recesses formed in the sacrificial layer.

In some embodiments, the method for forming the through hole required by the connection structure includes, but is not limited to, dry etching and wet etching.

Illustratively, a through hole penetrating through the second semiconductor layer, the isolation structure and the base structure is formed by dry etching, wherein the base structure refers to the first semiconductor layer after the substrate is removed, the through hole extends into the first insulating layer where the first device is located, and then the sacrificial layer is removed by wet etching through the through hole.

Next, as shown in fig. 16, a conductive material is filled in the via 515 to form a connection structure 516, and the connection structure 516 is electrically connected to the first interconnect structure 505.

In some embodiments, methods of forming the connecting structure include, but are not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, and the like.

In some embodiments, the material of the connection structure 516 includes a metal, such as copper (Cu), cobalt (Co), tungsten (W), molybdenum (Mo), and the like.

It can be understood that the electrical connection of the first device is realized by leading out the circuit formed by the embedded first device through the connection structure.

In some embodiments, a memory array is formed on a surface of the second insulating layer remote from the first device, wherein in some embodiments, the memory comprises a three-dimensional NAND-type memory.

It is understood that the peripheral circuit composed of the first device and the second device is connected to the memory structure, and is used for controlling the memory structure to write, read, refresh, etc. data.

According to another aspect of the present disclosure, an embodiment of the present disclosure further provides a semiconductor structure, including:

the semiconductor device comprises a first semiconductor layer, an isolation structure and a second semiconductor layer which are sequentially stacked;

at least one first device, a partial structure of the first device being located in the first semiconductor layer;

at least one second device, a partial structure of the second device being located in the second semiconductor layer.

In the foregoing solution, the semiconductor structure further includes:

and the connecting structure is positioned on one side of the first device and the second device and penetrates through the second semiconductor layer, the isolation structure and the first semiconductor layer, and the connecting structure is electrically connected with the first device.

In the above scheme, the operating voltage of the first device is higher than the operating voltage of the second device.

In the above scheme, the isolation structure comprises a gas isolation material and/or a solid isolation material.

In the above scheme, the isolation structure comprises a gas isolation material and a solid isolation material; wherein the isolation structures of the first and second devices at an orthographic projection of a plane in which the isolation structures are located comprise gas isolation materials.

In the foregoing solution, the semiconductor structure further includes:

the first insulating layer covers the surface, far away from the isolation structure, of the first semiconductor layer;

the first device includes: the first doped region is located in the first semiconductor layer, and the first gate structure and the first interconnection structure are located in the first insulating layer at positions corresponding to the first doped region.

In the above scheme, the semiconductor structure further includes:

the second insulating layer covers the surface, far away from the isolation structure, of the second semiconductor layer;

the second device includes: the second doped region is located in the second semiconductor layer, and the second gate structure and the second interconnection structure are located in the second insulating layer at positions corresponding to the second doped region.

According to another aspect of the present disclosure, an embodiment of the present disclosure further provides a memory, including:

a memory array and peripheral circuitry coupled with the memory array; wherein the peripheral circuit comprises any of the semiconductor structures described above.

In some embodiments, the memory comprises a three-dimensional NAND-type memory.

The disclosed embodiments also provide a memory system, which includes:

one or more memories as described in any of the above embodiments; and

a memory controller coupled with and controlling the memory.

Here, with respect to the specific structure and composition of the memory system, reference may be made to the related structure and composition of the memory system in fig. 1, fig. 2a, and fig. 2 b. For brevity, no further description is provided herein.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in a non-target manner. The above-described device embodiments are merely illustrative, for example, the division of the unit is only one logical function division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. Additionally, the various components shown or discussed are coupled or directly coupled to each other.

The features disclosed in the several method or apparatus embodiments provided in this disclosure may be combined in any combination to arrive at a new method or apparatus embodiment without conflict.

The scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims (19)

1. A semiconductor structure, comprising:

the semiconductor structure comprises a first semiconductor layer, an isolation structure and a second semiconductor layer which are sequentially stacked;

at least one first device, a partial structure of the first device being located in the first semiconductor layer;

at least one second device, a partial structure of the second device being located in the second semiconductor layer.

2. The semiconductor structure of claim 1, wherein an operating voltage of the first device is higher than an operating voltage of the second device.

3. The semiconductor structure of claim 2, further comprising:

and the connecting structure is positioned on one side of the first device and the second device and penetrates through the second semiconductor layer, the isolation structure and the first semiconductor layer, and the connecting structure is electrically connected with the first device.

4. The semiconductor structure of claim 1, wherein the isolation structure comprises a gas isolation material and/or a solid isolation material.

5. The semiconductor structure of claim 4, wherein the isolation structure comprises a gas isolation material and a solid isolation material; wherein the isolation structures of the first and second devices at an orthographic projection of a plane in which the isolation structures are located comprise gas isolation materials.

6. The semiconductor structure of claim 1, further comprising:

the first insulating layer covers the surface, far away from the isolation structure, of the first semiconductor layer;

the first device includes: the first doped region is located in the first semiconductor layer, and the first gate structure and the first interconnection structure are both located in the first insulating layer at positions corresponding to the first doped region.

7. The semiconductor structure of claim 1, further comprising:

the second insulating layer covers the surface, far away from the isolation structure, of the second semiconductor layer;

the second device includes: the second doped region is located in the second semiconductor layer, and the second gate structure and the second interconnection structure are located in the second insulating layer at positions corresponding to the second doped region.

8. A memory, comprising: a memory array and peripheral circuitry coupled with the memory array; wherein the peripheral circuit comprises a semiconductor structure as claimed in any one of claims 1 to 7.

9. A memory system, comprising:

one or more memories as recited in claim 8; and

a memory controller coupled with and controlling the memory.

10. A method of fabricating a semiconductor structure, comprising:

providing a base structure, wherein the base structure comprises a first surface and a second surface which are oppositely arranged, and at least one first device is formed at the first surface;

thinning the base structure from the second surface;

forming a second semiconductor layer on the thinned second surface;

forming at least one second device in the second semiconductor layer;

an isolation structure is formed between the base structure and the second semiconductor layer.

11. The method of claim 10, wherein forming the isolation structure comprises:

forming a sacrificial layer on the thinned second surface before forming the second semiconductor layer; after the second semiconductor layer is formed, removing the sacrificial layer to form the isolation structure;

forming a second semiconductor layer on the thinned second surface, including:

and forming the second semiconductor layer on the sacrificial layer through an epitaxial process.

12. The method of claim 11, wherein the forming the isolation structure comprises:

filling an isolation material at the position where the sacrificial layer is removed to form an isolation structure; the isolation material comprises a gas isolation material and/or a solid isolation material.

13. The method of claim 11, wherein the sacrificial layer is different from the base structure and the second semiconductor layer in etch selectivity.

14. The method of claim 10, wherein the step of forming the semiconductor structure comprises the step of forming a semiconductor layer on the substrate,

the substrate structure comprises a substrate and a first semiconductor layer which are stacked, and the surface of the substrate, which is far away from the first semiconductor layer, is a second surface of the substrate structure; forming the first semiconductor layer by an epitaxial process;

thinning the base structure from the second surface includes:

and removing the substrate through an etching process, wherein etching is stopped on the surface of the first semiconductor layer.

15. The method of claim 14, wherein forming the first device comprises:

forming a first doped region in the first semiconductor layer; and forming a first insulating layer on the surface of the first semiconductor layer far away from the substrate, and forming a first grid structure corresponding to the first doping region and a first interconnection structure electrically connected with the first grid structure and the first doping region in the first insulating layer.

16. The method of claim 15, wherein forming the second device comprises:

forming a second doped region in the second semiconductor layer; and forming a second insulating layer on the surface of the second semiconductor layer far away from the substrate structure, and forming a second grid structure corresponding to the second doped region and a second interconnection structure electrically connected with the second grid structure and the second doped region in the first insulating layer.

17. The method of fabricating a semiconductor structure of claim 10, further comprising:

and forming a connection structure penetrating through the second semiconductor layer, the isolation structure and the base structure on one side of the first device and the second device, wherein the connection structure is electrically connected with the first device.

18. The method of claim 16, wherein forming the connection structure comprises:

forming a via hole penetrating through the second insulating layer, the second semiconductor layer, the isolation structure, the first semiconductor layer and extending into the first insulating layer;

and filling a conductive material in the through hole to form a connecting structure, wherein the connecting structure is electrically connected with the first interconnection structure.

19. The method of fabricating a semiconductor structure of claim 10, further comprising:

forming a carrier at a surface of the first device remote from the second surface before thinning the base structure from the second surface.

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