CN115497949A

CN115497949A - Semiconductor device and manufacturing method thereof

Info

Publication number: CN115497949A
Application number: CN202211153862.9A
Authority: CN
Inventors: 刘小欣; 霍宗亮
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-09-21
Filing date: 2022-09-21
Publication date: 2022-12-20

Abstract

The disclosed embodiment provides a semiconductor device, including: a first semiconductor structure including a first substrate and a first peripheral circuit disposed on the first substrate; the first peripheral circuit includes a plurality of vertical transistors, each of the vertical transistors including: the vertical grid structure is positioned in the first substrate, and at least one side of the vertical grid structure is provided with a channel region; and the source electrode and the drain electrode are respectively positioned on two opposite sides of the channel region along the thickness direction of the first substrate.

Description

Semiconductor device and manufacturing method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor device and a method for manufacturing the same.

Background

The Semiconductor device includes a memory Array formed in an Array Wafer (Array Wafer) and peripheral circuits formed in a Complementary Metal Oxide Semiconductor (CMOS) Wafer for controlling signals to and from the memory Array. In the manufacturing process of a semiconductor device, the two different wafers are usually bonded together to obtain the semiconductor device. With the development of semiconductor technology, the size of semiconductor devices used to form memory arrays is reduced and the integration level is higher and higher with the same storage capacity. However, to implement more memory cells, more peripheral circuits are required. The continuous increase in the area of peripheral circuits has become a bottleneck in the overall size reduction of semiconductor devices.

Disclosure of Invention

According to a first aspect of the embodiments of the present disclosure, there is provided a semiconductor device, including:

a first semiconductor structure including a first substrate and a first peripheral circuit disposed on the first substrate; the first peripheral circuit includes a plurality of vertical transistors, each of the vertical transistors including:

the vertical grid structure is positioned in the first substrate, and at least one side of the vertical grid structure is provided with a channel region; and the source electrode and the drain electrode are respectively positioned on two opposite sides of the channel region along the thickness direction of the first substrate.

In the above scheme, the first semiconductor structure further includes:

a memory array, the first peripheral circuitry located at a periphery of the memory array.

In the above solution, the first semiconductor structure further includes:

a memory array, the first peripheral circuitry being located between the memory array and the first substrate.

In the above aspect, the semiconductor device further includes:

and the second semiconductor structure is in bonding connection with the first semiconductor structure and comprises a second substrate and a second peripheral circuit arranged on the second substrate.

In the above solution, the second substrate includes a first side and a second side opposite to each other, and the second peripheral circuit is located on the first side of the second substrate;

the second semiconductor structure further includes:

contact pads on a second side of the second substrate, the contact pads being electrically connected to the second peripheral circuitry by conductive contacts through the second substrate.

In the above-described aspect, the first peripheral circuit is configured to receive a first voltage signal, and the second peripheral circuit is configured to receive a second voltage signal, the first voltage signal having a voltage higher than a voltage of the second voltage signal.

According to a second aspect of the embodiments of the present disclosure, there is provided a method of manufacturing a semiconductor device, including:

forming a first semiconductor structure, wherein the first semiconductor structure comprises a first substrate and a first peripheral circuit arranged on the first substrate; the first peripheral circuit includes a plurality of vertical transistors, each of the vertical transistors including:

In the foregoing solution, the forming the first semiconductor structure includes:

forming the first peripheral circuitry and a memory array on the first substrate; the first peripheral circuitry is located peripheral to the memory array.

In the foregoing scheme, the forming the first semiconductor structure includes: sequentially forming the first peripheral circuit and a memory array on the first substrate; the first peripheral circuitry is located between the memory array and the first substrate.

In the above scheme, the method further comprises:

forming a memory array on the third substrate;

the forming a first semiconductor structure includes:

forming the first peripheral circuit on the first substrate;

bonding the first peripheral circuit and the memory array; the first peripheral circuitry is located between the memory array and the first substrate;

and removing the third substrate.

In the foregoing solution, the method further includes:

forming a second semiconductor structure on a second substrate, wherein the second semiconductor structure comprises a second substrate and a second peripheral circuit arranged on the second substrate;

and bonding the first semiconductor structure and the second semiconductor structure.

In the above solution, the second substrate includes a first surface and a second surface opposite to the first surface, and the second peripheral circuit is located on the first surface of the second substrate;

the method further comprises the following steps:

etching from the second surface of the second substrate to form a through hole penetrating through the second substrate, and filling a conductive material in the through hole to form a conductive contact;

forming contact pads on a second side of the second substrate, the contact pads being electrically connected to the second peripheral circuit through the conductive contacts.

According to a third aspect of the embodiments of the present disclosure, there is provided a memory including the semiconductor device as described above.

According to a fourth aspect of embodiments of the present disclosure, there is provided a memory system including:

at least one memory as described above; and

a controller coupled to the memory and configured to control the memory.

The disclosed embodiment provides a semiconductor device, which includes: the semiconductor device comprises a first semiconductor structure, a second semiconductor structure and a third semiconductor structure, wherein the first semiconductor structure comprises a first substrate, and a memory array and a first peripheral circuit which are arranged on the first substrate; the first peripheral circuit includes a plurality of vertical transistors, each of the vertical transistors including: the vertical grid structure is positioned in the first substrate, and at least one side of the vertical grid structure is provided with a channel region; the source electrode and the drain electrode are respectively positioned on two opposite sides of the channel region along the thickness direction of the first substrate; and the second semiconductor structure is in bonding connection with the first semiconductor structure and comprises a second substrate and a second peripheral circuit arranged on the second substrate. The disclosed embodiments can distribute peripheral circuits (i.e., first and second peripheral circuits) of a memory array in different levels by disposing the first and second peripheral circuits in the first and second semiconductor structures, respectively, and bonding the first and second semiconductor structures, thereby reducing the planar size of the peripheral circuits. Furthermore, the vertical transistor is adopted to form the first peripheral circuit, so that the plane size of the first peripheral circuit on the first substrate is greatly reduced, the size of the semiconductor device is favorably reduced, and the density of the semiconductor device is increased.

Drawings

FIG. 1 is a cross-sectional schematic view of a semiconductor device according to an exemplary embodiment;

FIG. 2A is a cross-sectional schematic view of another semiconductor device in accordance with an exemplary embodiment;

FIG. 2B is a partial enlarged view of the first peripheral circuit shown in FIG. 2A;

fig. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the disclosure

Fig. 4A is a schematic cross-sectional view of another semiconductor device provided in an embodiment of the present disclosure;

FIG. 4B is a partial enlarged view of the first peripheral circuit shown in FIG. 4A;

fig. 5 is a schematic cross-sectional view of yet another semiconductor device provided by an embodiment of the present disclosure;

fig. 6 is a schematic cross-sectional view of yet another semiconductor device provided by an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a system having a storage system provided by an embodiment of the present disclosure;

FIG. 8A is a diagram illustrating a memory card according to an embodiment of the present disclosure;

fig. 8B is a schematic diagram of a solid state drive according to an embodiment of the disclosure.

Detailed Description

The technical solutions of the present disclosure will be further explained in detail with reference to the drawings and examples. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, and are provided solely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.

It should be understood that spatial relationship terms such as "below … …", "below … …", "below … …", "above … …", "above", etc., may be used herein for ease of description to describe the relationship of one element or feature to other elements or features shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items. The technical means described in the embodiments of the present disclosure may be arbitrarily combined without conflict.

Fig. 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment. As shown in fig. 1, the semiconductor device 100 includes a first semiconductor structure 110 and a second semiconductor structure 120. The first semiconductor structure 110 includes a first substrate 111, and a first peripheral circuit 112 and a memory array 113 provided on the first substrate 111. The first semiconductor structure 110 may further include a pad extraction interconnect layer 114 under the first substrate 111. The pad out interconnect layer 114 may include interconnects, such as contact pads 115, in one or more Inter Level Dielectric (ILD) layers. In some embodiments, pad out interconnect layer 114 may pass electrical signals between semiconductor device 100 and external circuitry, e.g., for pad out purposes. In some embodiments, the first semiconductor structure 100 further includes one or more contacts 116, the contacts 116 coupling interconnects in the first semiconductor structure 110 to the pad out interconnect layer 114 for electrical connection through the first substrate 111. The material of the contact 116 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof.

The second semiconductor structure 120 includes a second substrate 121 and a second peripheral circuit 122 disposed on the second substrate 121. The second semiconductor structure 120 may further include a passivation layer 123 that replaces the pad-lead interconnect layer in the first semiconductor structure 110 to protect and package the semiconductor device 100 from the side of the second semiconductor structure 120 that does not have the pad-lead interconnect layer. The passivation layer 123 may include a dielectric material, such as silicon nitride or silicon oxide. In some embodiments, the second semiconductor structure 120 in the semiconductor device 100 further includes a handle/carrier substrate 124 in contact with the passivation layer 123, as a base substrate for the semiconductor device 100 to provide support.

In some embodiments, the first semiconductor structure 110 and the second semiconductor structure 120 are bond connected at a bonding interface 1101. The first peripheral circuit 112 may include a High Voltage (HV) circuit, such as a driving circuit, and the second peripheral circuit 122 may include a Low Voltage (LV) circuit or an ultra-Low Voltage (Low Voltage, LLV) circuit, such as at least one of an input/output (I/O) circuit, a page buffer circuit, or a logic circuit.

Fig. 2A is a cross-sectional schematic view of another semiconductor device, according to an example embodiment. As shown in fig. 2A, the semiconductor device 200 includes a first semiconductor structure 210 and a second semiconductor structure 220. The first semiconductor structure 210 includes a first substrate 211 and a first peripheral circuit 212 disposed on the first substrate 211, and the first semiconductor structure 210 may further include a polysilicon layer 214 on which a memory array 213 is formed.

The second semiconductor structure 220 includes a second substrate 221 and a second peripheral circuit 222 disposed on the second substrate 221. The second semiconductor structure 220 may further include a pad out interconnect layer 223, and the pad out interconnect layer 223 may include interconnects, such as contact pads 224, in one or more ILD layers. In some embodiments, the second semiconductor structure 220 further includes one or more contacts 225, the contacts 225 coupling interconnects in the second semiconductor structure 220 to the pad out interconnect layer 223 for electrical connection through the second substrate 221.

In some embodiments, the first semiconductor structure 210 and the second semiconductor structure 220 are bond connected at a bonding interface 2101. The first peripheral circuit 212 may include a HV circuit, such as a driver circuit, and the second peripheral circuit 222 may include a LV circuit or LLV circuit, such as at least one of an input/output (I/O) circuit, a page buffer circuit, or a logic circuit.

In the semiconductor device shown in fig. 1 and 2A, the first peripheral circuit and the second peripheral circuit are formed on two different substrates, so that the occupied area of the peripheral circuits is reduced, the area is optimized, and the size of the semiconductor device is reduced.

Fig. 2B is a partially enlarged view of the first peripheral circuit 212 shown in fig. 2A, the first peripheral circuit 212 including a plurality of horizontal transistors. As shown in fig. 2B, two adjacent horizontal transistors 212-1 and 212-2 are isolated by an isolation structure 215. Taking the horizontal transistor 212-2 as an example, the horizontal transistor 212-2 includes a gate 219 on the substrate 216, a source 217 and a drain 218 in the substrate 216 respectively on both sides of the gate 219, and in some embodiments, the horizontal transistor 212-2 further includes a dielectric layer 230 covering the isolation structure 215, the drain 217, the source 218 and the gate 219. The space between the drain 218 and source 217 and under the gate 217 is the horizontal channel region of the transistor 212-2, the planar size of a horizontal transistor having a horizontal channel region is large.

The first peripheral circuit shown in fig. 1 and 2A occupies an area of 30% or more in the first semiconductor structure, and in the case where the first peripheral circuit includes a plurality of horizontal transistors, it is difficult to reduce the planar size thereof.

In view of this, the disclosed embodiments provide a semiconductor device.

Referring to fig. 3, fig. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the disclosure, where the semiconductor device 300 includes:

a first semiconductor structure 310, the first semiconductor structure 310 comprising a first substrate 311 and a first peripheral circuit 312 disposed on the first substrate 311; the first peripheral circuit 312 includes a plurality of vertical transistors, each of which includes:

a vertical gate structure located in the first substrate 311, wherein a channel region is formed on at least one side of the vertical gate structure; and the source electrode and the drain electrode are respectively positioned on two opposite sides of the channel region along the thickness direction of the first substrate.

In the embodiment of the present disclosure, the first semiconductor structure 310 further includes: a memory array 313, the first peripheral circuitry 312 being located peripheral to the memory array 313. In some embodiments, the first peripheral circuitry 312 may be coupled to the memory array 313 by various interconnect structures (not shown in the figures), including conductive interconnect lines.

In some embodiments, the first semiconductor structure further includes a second peripheral circuit disposed on the first substrate, the second peripheral circuit being located at a periphery of the memory array. The second peripheral circuit includes a plurality of vertical transistors, each vertical transistor including:

In some embodiments, the first peripheral circuitry may comprise HV circuitry, such as driver circuitry, in particular the first peripheral circuitry comprises a column decoder/bit line driver or a row decoder/word line driver. The second peripheral circuit may include LV circuitry or LLV circuitry, such as at least one of input/output (I/O) circuitry, page buffer circuitry, or logic circuitry.

In some embodiments, the memory array includes a NAND flash memory array, and particularly, the memory array 313 includes a stack structure in which gate layers and insulating layers are alternately stacked and a channel structure extending through the stack structure. A first dielectric layer 314 is further disposed on the stacked structure, the first dielectric layer 314 is used for protecting the stacked structure, the channel structure and the first peripheral circuit 312 disposed on the first substrate 311, and a material of the first dielectric layer 314 may be, for example, silicon oxide, silicon nitride, etc. It should be noted that the memory array is not limited to a NAND flash memory array and may include any other suitable type of memory array, such as a NOR flash memory array, a Phase Change Memory (PCM) array, a resistive memory array, a magnetic memory array, to name a few.

According to the embodiment of the disclosure, the first peripheral circuit is formed by using the vertical transistor, so that the plane size of the first peripheral circuit on the first substrate is greatly reduced, the size of the semiconductor device is favorably reduced, and the density of the semiconductor device is increased.

Referring to fig. 4A, fig. 4A is a schematic cross-sectional view of another semiconductor device provided in an embodiment of the present disclosure, the semiconductor device 400 includes:

a first semiconductor structure 410, the first semiconductor structure 410 comprising a first substrate 411 and a first peripheral circuit 412 disposed on the first substrate 411; the first peripheral circuit 412 includes a plurality of vertical transistors, each of which includes:

In the embodiment of the present disclosure, the first semiconductor structure 410 further includes: a memory array 413, the first peripheral circuitry 412 being located peripheral to the memory array 413.

In the disclosed embodiment, the semiconductor device 400 further includes: a second semiconductor structure 420, the second semiconductor structure 420 being bonded to the first semiconductor structure 410, the second semiconductor structure 420 including a second substrate 421 and a second peripheral circuit 422 disposed on the second substrate 421.

In the present embodiment, the dotted line shown in fig. 4A is only used to distinguish the first peripheral circuit 412 of the first semiconductor structure 410 from the memory array 413, and it is emphasized that the dotted line does not exist in an actual semiconductor device.

In some embodiments, the first peripheral circuit 412 and the second peripheral circuit 422 are formed of a plurality of transistors, which may be CMOS transistors, for example.

In some embodiments, fig. 4B is a partial enlarged view of the first peripheral circuit 412 shown in fig. 4A, and as shown in fig. 4B, the first peripheral circuit 412 includes a plurality of vertical transistors, each of the vertical transistors including: a vertical gate structure located in the first substrate 411, the vertical gate structure including a gate 431 and a gate oxide layer 432, at least one side of the vertical gate structure being formed with a channel region 433; and a source electrode 435 and a drain electrode 434, the source electrode 435 and the drain electrode 434 being respectively located at opposite sides of the channel region 433 in a thickness direction of the first substrate. The source electrode and the drain electrode of the vertical transistor are respectively positioned at two opposite sides of the vertical channel region along the thickness direction of the first substrate, and the vertical channel region is at least positioned at one side of the vertical grid structure, so that the area of the transistor is greatly reduced, and the storage density of the semiconductor device is improved.

In some embodiments, the material of gate 431 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The gate oxide layer 432 is made of an insulating material, such as silicon dioxide (SiO) ₂ )。

In other embodiments, each vertical transistor includes: a vertical gate structure located in the first substrate 411, the vertical gate structure including a gate 431 and a gate oxide layer 432,

channel regions

433 and 436 being formed at two sides of the vertical gate structure, respectively; and a source electrode 435 and a drain electrode 434 respectively located at opposite sides of the channel region 433 in the first substrate thickness direction, and a source electrode 438 and a drain electrode 437 respectively located at opposite sides of the channel region 436 in the first substrate thickness direction. Thus, each vertical transistor increases the number of transistors by sharing the gate 431, improving the memory density of the semiconductor device.

In some embodiments, the vertical transistor further includes a sidewall protection structure 439 to prevent an electrical connection between the gate 431 and the source/drain, thereby improving the yield of the semiconductor device. The material of the sidewall protection structure 439 comprises a silicon nitride layer.

In an embodiment of the present disclosure, the first peripheral circuit 412 is configured to receive a first voltage signal, and the second peripheral circuit 422 is configured to receive a second voltage signal, the first voltage signal having a higher voltage than the second voltage signal. In one embodiment, the voltage of the first voltage signal may be greater than 3.3V, such as 5V-30V, and the voltage of the second voltage signal may be less than or equal to 3.3V.

In some embodiments, the first peripheral circuitry 412 may include HV circuitry, such as driver circuitry, in particular, the first peripheral circuitry 412 includes a column decoder/bit line driver or a row decoder/word line driver. The second peripheral circuitry 422 may include LV circuitry or LLV circuitry, such as at least one of input/output (I/O) circuitry, page buffer circuitry, or logic circuitry.

In some embodiments, the first substrate 411 may be a single crystalline silicon substrate, which may provide better carrier transport capability and lower carrier transport loss compared to a polycrystalline silicon substrate due to the absence of grain boundaries, and thus may serve as a substrate of the first peripheral circuit 411 to improve the performance of the semiconductor device.

The second substrate 421 may be a simple substance semiconductor material substrate (e.g., a Silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-Silicon substrate, etc.), or a Silicon-on-Insulator (SOI), germanium-on-Insulator (GeOI) substrate, etc.

In some embodiments, the memory array includes a NAND flash memory array, and in particular, the memory array 313 includes a stack structure in which gate layers and insulating layers are alternately stacked and a channel structure extending through the stack structure. A second dielectric layer 414 is further disposed on the stacked structure, the second dielectric layer 414 is used for protecting the stacked structure, the channel structure and the first peripheral circuit 412 disposed on the first substrate 411, and a material of the second dielectric layer 414 may be, for example, silicon oxide, silicon nitride, etc.

In an embodiment of the present disclosure, the second substrate includes opposing first and second sides, the second peripheral circuit being located on the first side of the second substrate;

the second semiconductor structure 420 further comprises:

contact pads 427 on a second side of said second substrate 421, said contact pads 427 being electrically connected to said second peripheral circuitry 412 by conductive contacts 428 extending through said second substrate 421. The second semiconductor structure 420 may further include a pad extraction interconnect layer 424 on the second side of the second substrate 421. The pad extraction interconnect layer 424 may include interconnects in one or more ILD layers, such as contact pads 427. In some embodiments, the pad out interconnect layer 424 may pass electrical signals between the semiconductor device 400 and external circuitry. In some embodiments, the first semiconductor structure 400 further includes one or more conductive contacts 428, the conductive contacts 428 coupling interconnects in the second semiconductor structure 420 to the pad extraction interconnect layer 424 for electrical connection through the second substrate 421. The material of the conductive contacts 428 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof.

In some embodiments, the second semiconductor structure 420 further includes a third dielectric layer 423, the third dielectric layer 423 is used for protecting the second peripheral circuit 422 disposed on the first side of the second substrate 421, and the material of the third dielectric layer 423 may be, for example, silicon oxide, silicon nitride, or the like.

In the disclosed embodiment, the second dielectric layer 414 and the third dielectric layer 423 may have a single-layer or stacked structure. The second dielectric layer 414 and the third dielectric layer 423 may be made of the same material or different materials, and may include one or more of Silicon oxide, silicon nitride, or Nitrogen-doped Silicon Carbide (NDC) as a dielectric material.

In the disclosed embodiment, the semiconductor device 400 further includes a bonding interface 4101 between the first semiconductor structure 410 and the second semiconductor structure 420. Bonding interface 4101 may be an interface between two semiconductor structures formed by any suitable bonding technique including, for example, hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, and the like.

In some embodiments, the first semiconductor structure 410 and the second semiconductor structure 420 are electrically connected through the first bonding pad 416 and the second bonding pad 426. In some embodiments, the first bonding pad 416 and the first peripheral circuitry 411 may be electrically connected by a first conductive interconnect line 415. Accordingly, the second bonding pad 426 and the second peripheral circuit 421 may also be electrically connected by the second conductive interconnection line 425. It is understood that the first peripheral circuitry 411 is electrically connected to the second peripheral circuitry 422 through the first metal interconnect 415, the first and

second bond pads

416, 426 and the second conductive interconnect line 425. Accordingly, the memory array 413 is electrically connected to the second peripheral circuitry 422 through the first conductive interconnect 415, the first and

second bond pads

416, 426, and the second conductive interconnect 425.

The disclosed embodiments can distribute peripheral circuits (i.e., first and second peripheral circuits) of a memory array in different levels by disposing the first and second peripheral circuits in the first and second semiconductor structures, respectively, and bonding the first and second semiconductor structures, thereby reducing the planar size of the peripheral circuits. Furthermore, the vertical transistor is adopted to form the first peripheral circuit, so that the plane size of the first peripheral circuit on the first substrate is greatly reduced, the size of the semiconductor device is favorably reduced, and the density of the semiconductor device is increased.

Referring to fig. 5, fig. 5 is a schematic cross-sectional view of another semiconductor device provided in an embodiment of the present disclosure, where the semiconductor device 500 includes:

a first semiconductor structure 510, the first semiconductor structure 510 comprising a first substrate 511 and a first peripheral circuit 513 disposed on the first substrate 511; the first peripheral circuit 513 includes a plurality of vertical transistors each including:

In the embodiment of the present disclosure, the first semiconductor structure 510 further includes: a memory array 516, and the first peripheral circuit 513 is positioned between the memory array 516 and the first substrate 511. In some embodiments, the first peripheral circuitry 513 may be coupled to the memory array 516 by various interconnect structures (not shown), including conductive interconnect lines. In some embodiments, the first peripheral circuitry 513 is located in the first device layer 512 of the first semiconductor structure 510.

In some embodiments, the first semiconductor structure 510 may further include a polysilicon layer 515 on which the memory array 516 is formed, in some embodiments, the polysilicon layer 515 is in contact with a source of the memory array 516. It should be understood that in some examples, polysilicon layer 515 may generally be a semiconductor layer that is not limited to a polysilicon layer.

In some embodiments, the first semiconductor structure 510 further includes a fourth dielectric layer 514 over the device layer 512, the material of the fourth dielectric layer 514 including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (low-k) dielectric, or any combination thereof.

By vertically integrating the first semiconductor structure and vertically separating the memory array and the first peripheral circuit into different planes in the first semiconductor structure, the semiconductor device size can be reduced and the semiconductor device density can be increased.

Referring to fig. 6, fig. 6 is a schematic cross-sectional view of another semiconductor device provided in an embodiment of the present disclosure, and the semiconductor device 600 includes:

a first semiconductor structure 610, the first semiconductor structure 610 comprising a first substrate 611 and a first peripheral circuit 613 disposed on the first substrate 611; the first peripheral circuit 613 includes a plurality of vertical transistors, each of which includes:

In an embodiment of the present disclosure, the first semiconductor structure 610 further includes: a memory array 616, said first peripheral circuitry 613 being located between said memory array 616 and said first substrate 611.

In the embodiment of the present disclosure, the semiconductor device 600 further includes: a second semiconductor structure 620, wherein the second semiconductor structure 620 is bonded to the first semiconductor structure 610, and the second semiconductor structure 620 includes a second substrate 621 and a second peripheral circuit 623 disposed on the second substrate 621.

It should be noted that, reference may be made to fig. 4B and the related description for specific structures of the plurality of vertical transistors included in the first peripheral circuit 613, which is not described herein again.

In the embodiment of the present disclosure, the first peripheral circuit 613 is located between the memory array 616 and the first substrate 611. In some embodiments, the first peripheral circuitry 613 is located in the first device layer 612 of the first semiconductor structure 610.

In some embodiments, the first semiconductor structure 610 may further include a polysilicon layer 615 on which a memory array 616 is formed, in some embodiments, the polysilicon layer 615 is in contact with a source of the memory array 616. That is, polysilicon layer 615 may serve as a common source plate for memory array 616. The polysilicon Layer 615 may be formed by a thin film Deposition process such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof. It should be understood that in some examples, polysilicon layer 615 may generally be a semiconductor layer that is not limited to a polysilicon layer.

In some embodiments, the first semiconductor structure 610 further includes a fifth dielectric layer 614 over the device layer 612, the material of the fifth dielectric layer 614 including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant (low-k) dielectric, or any combination thereof.

As shown in fig. 4, the first semiconductor structure 610 further includes a sixth dielectric layer 619 over and in contact with the memory array 616.

In some embodiments, the semiconductor device 600 further includes a bonding interface 6101 between the first semiconductor structure 610 and the second semiconductor structure 620.

In some embodiments, second semiconductor structure 620 further includes a seventh dielectric layer 624 over bonding interface 6101. The materials of the fifth dielectric layer 614, the sixth dielectric layer 619, and the seventh dielectric layer 624 may be the same or different.

In some embodiments, the second semiconductor structure 620 may include a device layer 622 over and in contact with a seventh dielectric layer 624, with the second peripheral circuitry located in the device layer 622.

In the disclosed embodiment, the first peripheral circuitry 613 is configured to receive a first voltage signal and the second peripheral circuitry 623 is configured to receive a second voltage signal, the first voltage signal having a higher voltage than the second voltage signal. In one embodiment, the voltage of the first voltage signal may be greater than 3.3V, such as 5V-30V, and the voltage of the second voltage signal may be less than or equal to 3.3V.

In some embodiments, the first peripheral circuitry 613 may include HV circuitry, such as driver circuitry, in particular, the first peripheral circuitry 613 includes a column decoder/bitline driver or a row decoder/wordline driver. The second peripheral circuit 623 may include an LV circuit or a LLV circuit, such as at least one of an input/output (I/O) circuit, a page buffer circuit, or a logic circuit.

the second semiconductor structure 620 further comprises:

a contact pad 626 on a second side of the second substrate 621, the contact pad 626 being electrically connected to the second peripheral circuitry 623 by a conductive contact 627 through the second substrate 621. The second semiconductor structure 620 may further include a pad extraction interconnect layer 625 on the second side of the second substrate 621. The bond pad exit interconnect layer 625 may include interconnects in one or more ILD layers, such as contact pads 626. In some embodiments, the pad out interconnect layer 625 may pass electrical signals between the semiconductor device 600 and an external circuit.

In some embodiments, the second semiconductor structure 620 further includes one or more conductive contacts 627, the conductive contacts 627 coupling interconnects in the second semiconductor structure 620 to the pad extraction interconnect layer 625 for electrical connection through the second substrate 621. The material of conductive contact 627 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof.

In the embodiment of the present disclosure, the semiconductor device 600 further includes a bonding interface 6101 between the first semiconductor structure 610 and the second semiconductor structure 620. Bonding interface 6101 may be an interface between two semiconductor structures formed by any suitable bonding technique including, for example, hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, and the like.

In some embodiments, the first semiconductor structure 610 and the second semiconductor structure 620 are electrically connected through the third bonding pad 618 and the fourth bonding pad 628. In some embodiments, the third bond pad 618 and the first peripheral circuitry 413 may be electrically connected by a third conductive interconnect 617. Accordingly, the fourth bonding pad 628 and the second peripheral circuit 623 may also be electrically connected through the fourth conductive interconnection line 629.

In some embodiments, the first and second

peripheral circuits

613 and 623 in the first and

second semiconductor structures

610 and 620 may be coupled to the memory array 616 in the first semiconductor structure 610 through various interconnect structures including conductive interconnect lines, such as a third conductive interconnect line 617 and a fourth conductive interconnect line 629. In addition, the first peripheral circuit 613, the second peripheral circuit 623 and the memory array 616 in the semiconductor memory 600 may be further coupled to an external device through a contact pad 627 and a pad extraction interconnection layer 625.

By vertically integrating the first semiconductor structure and the second semiconductor structure, and vertically separating the memory array and the first and second peripheral circuits into different planes in the first semiconductor structure, the semiconductor device size can be reduced, and the semiconductor device density can be increased.

The embodiment of the disclosure provides a manufacturing method of a semiconductor device, and the manufacturing method specifically comprises the following steps:

A method of manufacturing the semiconductor device of the present embodiment is described below with reference to fig. 4A.

Referring to fig. 4A, a first semiconductor structure 410 is formed, the first semiconductor structure 410 including a first substrate 411 and a first peripheral circuit 412 disposed on the first substrate 411. It should be noted that, reference may be made to fig. 4B and the related description for specific structures of the plurality of vertical transistors included in the first peripheral circuit 313, which are not repeated herein.

In an embodiment of the present disclosure, the forming the first semiconductor structure 410 includes: forming the first peripheral circuitry 412 and a memory array 413 on the first substrate; the first peripheral circuitry 412 is located peripheral to the storage array 413.

In some embodiments, the first substrate 411 may be a single crystalline silicon substrate, which may be used as a substrate of the first peripheral circuit 412 to improve the performance of the semiconductor device, compared to a polycrystalline silicon substrate, since the single crystalline silicon substrate may provide better carrier transport capability and lower carrier transport loss due to the absence of grain boundaries.

A second semiconductor structure 420 is formed on a second substrate 421, and the second semiconductor structure 420 includes the second substrate 421 and a second peripheral circuit 422 disposed on the second substrate 421.

In the embodiment of the present disclosure, a second dielectric layer 414 is formed in the first semiconductor structure 410, a third dielectric layer 423 is formed in the second semiconductor structure 420, the second dielectric layer 414 is used for protecting the first peripheral circuit 412 and the memory array 413, and the third dielectric layer 423 is used for protecting the second peripheral circuit 422. In practical applications, the second dielectric layer 414 and the third dielectric layer 423 may serve as an interconnection layer in which a plurality of conductive interconnection lines are formed to electrically connect the first peripheral circuit 412 and the second peripheral circuit 422 or to electrically connect the memory array 413 and the second peripheral circuit 422.

In an embodiment of the present disclosure, techniques for bonding the first and

second semiconductor structures

410 and 420 include, for example, hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, eutectic bonding, and the like.

In practical applications, forming the conductive contact 428 may be after the first semiconductor structure 410 and the second semiconductor structure 420 are bonded.

In the embodiment of the present disclosure, the second substrate 421 includes a first side and a second side opposite to each other, and the second peripheral circuit 422 is located on the first side of the second substrate 421; the method further comprises the following steps:

etching from the second side of the second substrate 421 to form a via through the second substrate, the via being filled with a conductive material to form a conductive contact 428;

contact pads 427 are formed on the second side of the second substrate, the contact pads 427 being electrically connected to the second peripheral circuitry 422 through the conductive contacts 428.

In some embodiments, the etching process for forming the via hole generally employs a plasma process. After etching the via hole, the via hole may be filled with a conductive material, specifically tungsten (W) or copper (Cu), to form a conductive contact 428 for leading out the second peripheral circuit 422.

In some embodiments, before the second substrate 421 is etched to form the through holes, the second substrate 421 may be thinned, that is, the second substrate 421 is thinned from a second surface of the second substrate 421, so as to reduce redundant parts and reduce the volume of the semiconductor device.

In some embodiments, the method of thinning the second substrate 421 may include: wet etching and/or Chemical Mechanical Polishing (CMP) removes portions of the substrate material. Specifically, a wet etching process may be used to remove a portion of the substrate, for example, a Tetramethylammonium hydroxide (TMAH) solution may be used to thin the second substrate 421, or a chemical mechanical polishing process may be used to remove a portion of the substrate.

Another formation process of the first semiconductor structure in the embodiment of the present disclosure is described below with reference to fig. 6.

As shown in fig. 6, a first peripheral circuit 613 and a memory array 616 are sequentially formed on the first substrate 611, and the first peripheral circuit 613 is located between the memory array 616 and the first substrate 611.

Specifically, after forming the first peripheral circuitry 613 on the first substrate 611, depositing a fifth dielectric layer 614, and forming the polysilicon layer 615 over the fifth dielectric layer 614 may form the polysilicon layer 615 by depositing polysilicon on the fifth dielectric layer 614 using one or more thin film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). In some embodiments, the polysilicon layer 615 is doped with a P-type or N-type dopant using an in-situ doping process during the deposition process or during an ion implantation/diffusion process subsequent to the deposition process. A memory array 616 is formed over the polysilicon layer 615.

Another forming process of the first semiconductor structure in the embodiment of the present disclosure includes: forming a memory array on a third substrate, and forming a first peripheral circuit on the first substrate; bonding the first peripheral circuit and the memory array; the first peripheral circuitry is located between the memory array and the first substrate; and removing the third substrate.

In some embodiments, the memory array and the first peripheral circuit are bonded in a face-to-face manner. In some embodiments, the memory array is flipped over and faced down towards the first peripheral circuitry such that the memory array is located over the first peripheral circuitry by hybrid bonding.

The disclosed embodiments also provide a memory including any of the semiconductor devices disclosed in the present disclosure.

In some embodiments, the memory comprises a three-dimensional memory. In a specific example, the three-dimensional memory may be a three-dimensional NAND memory.

An embodiment of the present disclosure further provides a storage system, where the storage system includes: at least one memory as described above; and a controller coupled to the memory and configured to control the memory.

The memory system and the memory are further described below.

As shown in fig. 7, system 700 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual Reality (VR) device, augmented Reality (AR) device, or any other suitable electronic device having memory therein, system 700 may include a host 704 and a storage system 701, storage system 701 having one or more memories 702 and a controller 703. The host 704 may be a processor (e.g., a Central Processing Unit (CPU)) or a system on a chip (SoC) (e.g., an Application Processor (AP)) of the electronic device. Host 704 may be configured to send data to memory 702 or receive data from memory 702.

The controller 703 and the one or more memories 702 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system 701 may be implemented and packaged into different types of end electronic products. In one example as shown in fig. 8A, a controller 703 and a single memory 702 may be integrated into a memory card 701. The memory card 801 may include a PC card (PCMCIA), CF card, smart Media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, and the like. The memory card 801 may also include a memory card connector 802 that couples the memory card 801 with a host. In another example as shown in fig. 8B, a controller 703 and a plurality of memories 702 may be integrated into an SSD 803. SSD803 may also include an SSD connector 804 that couples SSD803 with a host.

It should be appreciated that reference throughout this specification to "one embodiment" or "some embodiments" means that a particular feature, structure or characteristic described in connection with the embodiments is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in some embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not imply an order of execution, and the order of execution of the processes should be determined by their functions and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description, and do not represent the advantages or disadvantages of the embodiments.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

2. The semiconductor device of claim 1, wherein the first semiconductor structure further comprises:

3. The semiconductor device of claim 1, wherein the first semiconductor structure further comprises:

4. The semiconductor device according to claim 2 or 3, further comprising:

5. The semiconductor device of claim 4, wherein the second substrate includes opposing first and second sides, the second peripheral circuit being located on the first side of the second substrate;

the second semiconductor structure further comprises:

6. The semiconductor device according to claim 5, wherein the first peripheral circuit is configured to receive a first voltage signal, and wherein the second peripheral circuit is configured to receive a second voltage signal, the first voltage signal having a voltage higher than a voltage of the second voltage signal.

7. A method of manufacturing a semiconductor device, comprising:

8. The method of manufacturing according to claim 7, wherein the forming a first semiconductor structure comprises:

9. The method of manufacturing according to claim 7, wherein the forming a first semiconductor structure comprises:

sequentially forming the first peripheral circuit and a memory array on the first substrate; the first peripheral circuitry is located between the memory array and the first substrate.

10. The method of manufacturing of claim 7, further comprising:

forming a memory array on the third substrate;

the forming a first semiconductor structure includes:

forming the first peripheral circuit on the first substrate;

and removing the third substrate.

11. The manufacturing method according to any one of claims 8 to 10, characterized in that the method further comprises:

bonding the first semiconductor structure and the second semiconductor structure.

12. The method of manufacturing of claim 11, wherein the second substrate includes opposing first and second sides, the second peripheral circuit being located on the first side of the second substrate;

the method further comprises the following steps:

13. A memory characterized in that the memory comprises the semiconductor device according to any one of claims 1 to 6.

14. A memory system, the memory system comprising:

at least one memory as recited in claim 13; and

a controller coupled to the memory and configured to control the memory.