CN115775823A - Shielding gate power device and preparation method thereof - Google Patents
Shielding gate power device and preparation method thereof Download PDFInfo
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- CN115775823A CN115775823A CN202211505609.5A CN202211505609A CN115775823A CN 115775823 A CN115775823 A CN 115775823A CN 202211505609 A CN202211505609 A CN 202211505609A CN 115775823 A CN115775823 A CN 115775823A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention relates to a shielding grid power device and a preparation method thereof. The shielded gate power device includes: a semiconductor layer; a trench in the semiconductor layer; the air cavity is positioned at the bottom of the groove; the shielding grid is positioned in the groove and positioned on the air cavity; the shielding grid electrode has a distance with the side wall of the groove, and the upper surface of the shielding grid electrode is lower than the top surface of the groove; the grid electrode is positioned in the groove, positioned above the shielding grid electrode and spaced from the shielding grid electrode and the side wall of the groove; and the covering dielectric layer is positioned between the shielding grid and the grid and covers the exposed surface of the shielding grid. According to the shielding grid power device, the air cavity is formed at the bottom of the groove and is positioned at the bottom of the shielding grid, and the air has a good isolation and voltage-resistant effect, so that the breakdown voltage at the bottom of the shielding grid can be remarkably improved, and the device is not easy to break down at the bottom of the groove.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a shielded gate power device and a preparation method thereof.
Background
In a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, a Shielded Gate Trench (SGT) MOSFET has the advantages of lower on-resistance, faster switching speed, and the like compared with a conventional trench MOSFET, and thus is widely applied in many fields.
The structure of a shielded gate trench MOSFET is shown in fig. 1, and may specifically include: the semiconductor layer 10, the trench 11, the shielding grid electrode 12, the shielding grid dielectric layer 13, the isolation dielectric layer 14, the grid electrode 15 and the grid electrode dielectric layer 16. Because the shielding gate dielectric layer 13 is generally formed by growing or depositing along the inner wall of the trench 11, the thickness of the shielding gate dielectric layer 13 at the bottom of the trench 11 is smaller than the thickness of the shielding gate dielectric layer 13 on the sidewall of the trench 11, and the bottom of the shielding gate 12 is in a tip shape, so that a strong electric field exists at the bottom of the shielding gate 12, which may cause insufficient withstand voltage of the shielding gate dielectric layer 13, and the device is easily broken down at the bottom of the trench 11.
Disclosure of Invention
In view of the defects of the prior art, an object of the present invention is to provide a shielded gate power device and a manufacturing method thereof, and to solve the problem that in a shielded gate trench MOSFET in the prior art, because the thickness of the shielded gate dielectric layer at the bottom of the trench is smaller than the thickness of the shielded gate dielectric layer on the sidewall of the trench, and the bottom of the shielded gate is in a tip shape, a strong electric field exists at the bottom of the shielded gate, which may cause insufficient withstand voltage of the shielded gate dielectric layer, and the device is easily broken down at the bottom of the trench.
In a first aspect, the present invention provides a shielded gate power device, comprising:
a semiconductor layer;
a trench located within the semiconductor layer;
the air cavity is positioned at the bottom of the groove;
a shield grid located in the trench and on the air cavity; the shielding grid electrode has a distance with the side wall of the groove, and the upper surface of the shielding grid electrode is lower than the top surface of the groove;
the grid electrode is positioned in the groove, positioned above the shielding grid electrode and spaced from the shielding grid electrode and the side wall of the groove;
and the covering dielectric layer is positioned between the shielding grid and the grid and covers the exposed surface of the shielding grid.
According to the shielding grid power device, the air cavity is formed at the bottom of the groove and is positioned at the bottom of the shielding grid, and the air has a good isolation and pressure-resistant effect, so that the breakdown voltage at the bottom of the shielding grid can be remarkably improved, and the device is not easy to break down at the bottom of the groove. And the dielectric constant of air is very low, and the air cavity is arranged at the bottom of the groove, so that the source-drain parasitic capacitance Cds can be greatly reduced, the switching speed of the device is increased, and the switching loss is reduced.
In one embodiment, the shielded gate power device further comprises:
the first field oxide layer is at least positioned on the side wall and the bottom of the groove; the grid electrode is positioned on the surface of the first field oxide layer far away from the semiconductor layer;
the isolation medium layer is positioned between the air cavity and the grid electrode and positioned on the surface of the first field oxide layer far away from the semiconductor layer;
the second field oxide layer is positioned between the isolation medium layer and the grid electrode and positioned on the surface, far away from the semiconductor layer, of the first field oxide layer; the shielding grid penetrates through the second field oxide layer from top to bottom and extends into the isolation medium layer.
In a second aspect, the present invention further provides a method for manufacturing a shielded gate power device, including:
providing a semiconductor layer;
forming a groove in the semiconductor layer;
forming an air cavity at the bottom of the groove;
forming a shield grid in the groove, wherein the shield grid is positioned on the air cavity; the shielding grid electrode has a distance with the side wall of the groove, and the upper surface of the shielding grid electrode is lower than the top surface of the groove;
forming a covering dielectric layer, wherein the covering dielectric layer covers the exposed surface of the shielding grid;
and forming a grid electrode in the groove, wherein the grid electrode is positioned above the shielding grid electrode, covers the covering dielectric layer and has intervals with the shielding grid electrode and the side wall of the groove.
According to the manufacturing method of the shielded gate power device, the air cavity is formed at the bottom of the groove and is positioned at the bottom of the shielded gate, and the air has a good isolation and voltage-resistant effect, so that the breakdown voltage at the bottom of the shielded gate can be remarkably improved, and the device is not easy to break down at the bottom of the groove. And the air has very low dielectric constant, and the air cavity is arranged at the bottom of the groove, so that the source-drain parasitic capacitance Cds can be greatly reduced, the switching speed of the device is increased, and the switching loss is reduced.
In one embodiment, before forming the air cavity at the bottom of the trench, the method further includes:
and forming a first field oxide layer on the upper surface of the semiconductor layer, the side wall and the bottom of the groove.
In one embodiment, forming an air cavity at the bottom of the trench includes:
forming a sacrificial layer at the bottom of the groove, wherein the sacrificial layer is positioned on the surface of the first field oxide layer away from the semiconductor layer;
forming a polycrystalline silicon layer on the upper surface of the sacrificial layer, wherein the upper surface of the polycrystalline silicon layer is lower than the upper surface of the groove;
forming a through hole in the polycrystalline silicon layer, wherein the through hole exposes the sacrificial layer;
removing the sacrificial layer based on the via to form the air cavity.
In one embodiment, the number of the through holes is multiple, and the through holes are arranged at intervals.
In one embodiment, the polysilicon layer includes a central region and an outer region located outside the central region, and the via is located in the outer region; after forming an air cavity at the bottom of the trench and before forming a shield gate in the trench, the method further comprises:
and oxidizing the polycrystalline silicon layer to oxidize at least the polycrystalline silicon layer positioned in the outer side area into a silicon oxide layer and fill the through hole, wherein the silicon oxide layer obtained in the oxidizing treatment process is used as an isolation dielectric layer.
In one embodiment, during the oxidation treatment, a portion of the polysilicon layer in the central region is retained, and a silicon oxide layer is formed on both the upper surface and the lower surface of the retained polysilicon layer.
In one embodiment, before forming the shield gate in the trench, the method further includes: and forming a second field oxide layer on the upper surface of the isolation dielectric layer, wherein the upper surface of the second field oxide layer is lower than the upper surface of the groove.
In one embodiment, forming a shield gate in the trench includes:
forming a grid electrode hole in the second field oxide layer, wherein the grid electrode hole exposes the polysilicon layer remained after the oxidation treatment;
and filling a polysilicon layer in the gate hole, wherein the filled polysilicon layer and the polysilicon layer remained after the oxidation treatment jointly form the shielding gate.
In the preparation method of the shielding grid power device, after a second field oxide layer is formed on the upper surface of the isolation dielectric layer, a grid hole is formed in the second dielectric layer, and then a polycrystalline silicon layer is filled in the grid hole, wherein the filled polycrystalline silicon layer and the polycrystalline silicon layer remained after oxidation treatment jointly form the shielding grid, the bottom of the shielding grid cannot be in a tip shape, and the bottom of the shielding grid cannot have a strong electric field, so that the bottom of the groove cannot be broken down.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technologies, the drawings used in the description of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic cross-sectional structural view of a conventional shielded gate trench MOSFET;
fig. 2 is a flow chart of a method of fabricating a shielded gate power device provided in an embodiment;
fig. 3 is a schematic cross-sectional structure diagram of a structure obtained in step S10 in the manufacturing method of the shielded gate power device provided in an embodiment;
fig. 4 is a schematic cross-sectional structure diagram of a structure obtained in step S20 in the manufacturing method of the shielded gate power device provided in an embodiment;
fig. 5 is a schematic cross-sectional structure diagram of a structure obtained after a first field oxide layer is formed in a manufacturing method of a shielded gate power device according to an embodiment;
fig. 6 to 9 are schematic cross-sectional structure diagrams of structures obtained in step S30 in the method for manufacturing a shielded gate power device provided in an embodiment;
FIGS. 10 and 11 are schematic top views of the polysilicon layer of FIG. 9;
fig. 12 is a schematic cross-sectional structure diagram of a structure obtained after an isolation dielectric layer is formed in a manufacturing method of a shielded gate power device provided in an embodiment;
fig. 13 to fig. 15 are schematic cross-sectional structural diagrams of structures obtained in step S40 in the manufacturing method of the shielded gate power device provided in an embodiment;
fig. 16 is a schematic top-view structural diagram of a structure obtained in step S50 in the manufacturing method of the shielded gate power device provided in an embodiment;
fig. 17 is a schematic cross-sectional structure diagram of a structure obtained in step S60 in the method for manufacturing a shielded gate power device provided in an embodiment.
Description of reference numerals:
10. a semiconductor layer; 11. a trench; 12. a shield gate; 13. shielding the gate dielectric layer; 14. isolating the dielectric layer; 15. a gate electrode; 16. a gate dielectric layer; 20. a semiconductor layer; 21. a trench; 22. a first field oxide layer; 23. a sacrificial layer; 24. a polysilicon layer; 241. a through hole; 25. an air chamber; 26. isolating the dielectric layer; 27. a second field oxide layer; 271. a gate hole; 28. a shield gate; 29. covering the dielectric layer; 210. and a gate.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
In an embodiment, referring to fig. 2, the present invention provides a method for manufacturing a shielded gate power device, where the method for manufacturing the shielded gate power device may include the following steps:
s10: providing a semiconductor layer;
s20: forming a trench in the semiconductor layer;
s30: forming an air cavity at the bottom of the groove;
s40: forming a shield grid in the groove, wherein the shield grid is positioned on the air cavity; the shielding grid electrode has a distance with the side wall of the groove, and the upper surface of the shielding grid electrode is lower than the top surface of the groove;
s50: forming a covering dielectric layer, wherein the covering dielectric layer covers the exposed surface of the shielding grid;
s60: and forming a grid electrode in the groove, wherein the grid electrode is positioned above the shielding grid electrode, covers the covering dielectric layer and has intervals with the shielding grid electrode and the side wall of the groove.
According to the manufacturing method of the shielded gate power device, the air cavity is formed at the bottom of the groove and is positioned at the bottom of the shielded gate, and the air has a good isolation and voltage-resistant effect, so that the breakdown voltage at the bottom of the shielded gate can be remarkably improved, and the device is not easy to break down at the bottom of the groove. And the air has very low dielectric constant, and the air cavity is arranged at the bottom of the groove, so that the source-drain parasitic capacitance Cds can be greatly reduced, the switching speed of the device is increased, and the switching loss is reduced.
In step S10, please refer to step S10 in fig. 2 and fig. 3, a semiconductor layer 20 is provided.
As an example, the semiconductor layer 20 may be at least one doped layer, such as at least one epitaxially doped layer; at this time, the semiconductor layer 20 may be formed on a substrate (not shown). Of course, in other examples, the semiconductor layer 20 may also be a doped substrate. The doping concentration range in the semiconductor layer 20 may be set according to actual conditions, and is not limited herein.
By way of example, the material of the semiconductor layer 20 may include, but is not limited to, silicon germanium, silicon carbide, gallium nitride, or other suitable semiconductor materials, and the like.
In step S20, please refer to step S20 in fig. 2 and fig. 3, a trench 21 is formed in the semiconductor layer 20.
As an example, step S20 may include the steps of:
s201: forming a patterned mask layer (not shown) on the upper surface of the semiconductor layer 20, wherein the patterned mask layer has an opening pattern therein, and the opening pattern defines the shape and position of the trench 21;
s202: etching the semiconductor layer 20 based on the patterned mask layer to form the trench 21 in the semiconductor layer 20;
s203: and removing the patterned mask layer to obtain a structure as shown in fig. 4.
In an optional example, step S201 may include the steps of:
s2011: forming a mask layer on the upper surface of the semiconductor layer 20;
s2012: forming a photoresist layer on the upper surface of the mask layer;
s2013: exposing and developing the photoresist layer to form a patterned photoresist layer;
s2014: etching the mask layer based on the graphical photoresist layer to obtain the graphical mask layer;
s2015: and removing the patterned photoresist layer.
As an example, in step S2011, the formed mask layer may have a single-layer structure, and in this case, the mask layer may include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer; in step S2011, the formed mask layer may also have a multilayer structure, and in this case, the mask layer may include at least two layers of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.
As an example, in step S2011, the mask layer may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like.
In another alternative example, step S201 may include the steps of:
s2011: forming a photoresist layer on the upper surface of the semiconductor layer 20;
s2012: and exposing and developing the photoresist layer to form a patterned photoresist layer serving as the patterned mask layer.
As an example, the depth of the trench 21 is smaller than the thickness of the semiconductor layer 20.
As an example, the longitudinal sectional shape of the groove 21 may be, but is not limited to, a U shape as shown in fig. 4, or the like.
As an example, the number of the grooves 21 formed in step S20 may be set according to actual needs, fig. 4 only takes the number of the grooves 21 as two as an example, and in other examples, the number of the grooves 21 is not limited to the number in fig. 4, and may be one, three, four, five, six or more, and so on.
As an example, as shown in fig. 5, after step S20, the following steps may be further included:
a first field oxide layer 22 is formed on the upper surface of the semiconductor layer 20, the sidewall and the bottom of the trench 21.
As an example, but not limited to, a thermal oxidation process may be used to form an oxide layer on the upper surface of the semiconductor layer 20, the sidewall and the bottom of the trench 21 as the first field oxide layer 22. The thickness of the first field oxide layer 22 may be set according to actual needs, and is not limited herein.
In step S30, please refer to step S3 in fig. 2 and fig. 6 to 11, an air cavity 25 is formed at the bottom of the trench 21.
As an example, step S30 may include the steps of:
s301: forming a sacrificial layer 23 at the bottom of the trench 21, wherein the sacrificial layer 23 is located on the surface of the first field oxide layer 22 away from the semiconductor layer 20, as shown in fig. 6;
s302: forming a polysilicon layer 24 on the upper surface of the sacrificial layer 23, wherein the upper surface of the polysilicon layer 24 is lower than the upper surface of the trench 21, as shown in the figure;
s303: forming a via 241 in the polysilicon layer 24, wherein the via 241 exposes the sacrificial layer 23, as shown in fig. 8;
s304: the sacrificial layer 23 is removed based on the via 241 to form the air cavity 25, as shown in fig. 9.
As an example, step S301 may include the steps of:
s3011: forming a sacrificial material layer (not shown) in the trench 21 and on an upper surface of the first field oxide layer 22; specifically, the sacrificial material layer may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process;
s3012: removing the sacrificial material layer on the upper surface of the first field oxide layer 22 outside the trench 21; specifically, the sacrificial material layer on the upper surface of the first field oxide layer 22 outside the trench 21 may be removed by, but not limited to, a chemical mechanical polishing process or an etching process;
s3013: back-etching the sacrificial material layer in the trench 21, wherein the remaining sacrificial material layer is the sacrificial layer 22; specifically, the sacrificial material layer located in the trench 21 may be etched back by, but not limited to, a dry etching process.
By way of example, the sacrificial layer 22 may include, but is not limited to, a silicon nitride layer.
As an example, step S302 may include the steps of:
s3021: forming a first polysilicon material layer (not shown) in the trench 21 and on an upper surface of the first field oxide layer 22; specifically, the first polysilicon material layer may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process;
s3022: removing the first polysilicon material layer on the upper surface of the first field oxide layer 22 outside the trench 21; specifically, the first polysilicon material layer on the upper surface of the first field oxide layer 22 outside the trench 21 may be removed by, but not limited to, a chemical mechanical polishing process or an etching process;
s3023: back-etching the first polysilicon material layer in the trench 21, wherein the remaining first polysilicon material layer is the polysilicon layer 24; specifically, the first polysilicon material layer located in the trench 21 may be etched back by, but not limited to, a dry etching process.
As an example, the polysilicon layer 24 may include, but is not limited to, a doped polysilicon layer, and the doping concentration in the polysilicon layer 24 may be set according to actual needs, which is not limited herein.
As an example, in step S203, the polysilicon layer 24 may be etched by, but not limited to, a dry etching process, and a via 241 is formed in the polysilicon layer 24.
As an example, the through hole 241 may have a circular, rectangular, or elliptical shape, etc. In fig. 10, the shape of the through hole 241 is a circle, and the shape of the through hole 241 is a rectangle in fig. 11.
As an example, the number of the through holes 241 in the polysilicon layer 24 is plural, and the through holes 241 may be arranged at intervals.
By way of example, the polysilicon layer 24 includes a central region (not labeled) and an outer region (not labeled) located outside the central region, the via 241 being located in the outer region. Specifically, the through holes 241 may be correspondingly arranged at intervals in the outer region (as shown in fig. 10), or may be arranged at intervals in a staggered manner in the outer region (as shown in fig. 11).
As an example, in step S304, the sacrificial layer 23 may be removed based on the via 241 using a wet etching solution to form the air cavity 25. Specifically, the wet etching solution may be any one of wet etching solutions, which has a removal rate of the sacrificial layer 23 that is significantly greater than a removal rate of the polysilicon layer 24 and a removal rate of the first field oxide layer 22.
As an example, after step S30, the following steps may be further included:
and performing oxidation treatment on the polycrystalline silicon layer 24 to oxidize at least the polycrystalline silicon layer 24 located in the outer side region into a silicon oxide layer and fill the through hole 241, wherein the silicon oxide layer obtained in the oxidation treatment process is used as an isolation dielectric layer 26.
As an example, during the oxidation treatment, a part of the polysilicon layer 24 in the central region is retained, and silicon oxide layers are formed on the upper surface and the lower surface of the retained polysilicon layer 24, that is, the isolation dielectric layer 26 is formed on the upper surface and the lower surface of the retained polysilicon layer 24.
It should be noted that the aperture of the through hole 241 cannot be too large, and if the aperture of the through hole 241 is too large, it is difficult to seal the through hole 241 in the process of forming the isolation dielectric layer 26. In the outer region, the pitch between adjacent through holes 241 is also small enough to completely oxidize the polysilicon layer 24 between adjacent through holes 241 during the formation of the isolation dielectric layer 26.
Specifically, the aperture of the through hole 241 may be 0.1um to 0.5um, and specifically, the aperture of the through hole 241 may be 0.1um, 0.2um, 0.3um, 0.4 um, or 0.5um. In the outer region, the pitch between adjacent through holes 241 may be less than or equal to 2um, for example, the pitch between adjacent through holes 251 may be 2um, 5um, 10um, or 15um, etc.
As an example, after forming the isolation dielectric layer 26, the following steps may be further included:
a second field oxide layer 27 is formed on the upper surface of the isolation dielectric layer 26, and the upper surface of the second field oxide layer 27 is lower than the upper surface of the trench 21, as shown in fig. 13.
As an example, forming the second field oxide layer 27 on the upper surface of the isolation dielectric layer 26 may include the following steps:
forming a field oxide layer (not shown) on an upper surface of the first field oxide layer 22 inside the trench 21 and outside the trench 21; specifically, an oxide layer may be deposited as the field oxide layer by using, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process;
removing the field oxide layer on the upper surface of the first field oxide layer 22 outside the trench 21; specifically, the field oxide material layer on the upper surface of the first field oxide layer 22 outside the trench 21 may be removed by, but not limited to, a chemical mechanical polishing process or an etching process;
etching back to remove a portion of the field oxide layer located in the trench 21, where the remaining field oxide layer is the second field oxide layer 27; specifically, but not limited to, a dry etching process may be used to etch back and remove a portion of the field oxide layer located in the trench 21.
In step S40, referring to step S40 in fig. 2 and fig. 14 to 15, a shielding gate 28 is formed in the trench 2, and the shielding gate 28 is located on the air cavity 25; the shield gate 28 is spaced from the sidewalls of the trench 21 and has an upper surface lower than the top surface of the trench 21.
As an example, step S40 may include the steps of:
s401: forming a gate hole 271 in the second field oxide layer 27, wherein the gate hole 271 exposes the polysilicon layer 24 remaining after the oxidation treatment, as shown in fig. 14;
s402: a polysilicon layer is filled in the gate hole 271, and the filled polysilicon layer and the polysilicon layer remaining after the oxidation treatment together constitute the shield gate 28, as shown in fig. 15.
As an example, in step S401, the second field oxide layer 27 may be etched by, but not limited to, a dry etching process, so as to form the gate hole 271 in the second field oxide layer 27.
As an example, the width of the gate hole 271 may be the same as, greater than, or less than the width of the remaining polysilicon layer. In this embodiment, the width of the gate hole 271 is the same as the width of the remaining polysilicon layer.
As an example, step S402 may include the steps of:
s4021: forming a second polysilicon material layer (not shown) on the upper surface of the first field oxide layer 22 in the gate hole 271, in the trench 21 and outside the trench 2; specifically, the second polysilicon material layer may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process;
s4022: removing the second polysilicon material layer on the upper surface of the second field oxide layer 22 outside the trench 21; specifically, but not limited to, a chemical mechanical polishing process or an etching process may be used to remove the second polysilicon material layer on the upper surface of the second field oxide layer 22 outside the trench 21;
s4023: back-etching the second polysilicon material layer in the trench 21, wherein the remaining second polysilicon material layer is the required polysilicon layer; specifically, the second polysilicon material layer located in the trench 21 may be etched back by, but not limited to, a dry etching process.
As an example, the polysilicon layer formed in step S40 may include, but is not limited to, a doped polysilicon layer, and the doping concentration in the polysilicon layer may be set according to actual needs, which is not limited herein.
As an example, the upper surface of the shield gate 28 is not lower than the upper surface of the second field oxide layer 27; in this embodiment, the upper surface of the shielding gate 28 may be higher than the upper surface of the second field oxide layer 27, as shown in fig. 15.
In step S50, please refer to step S50 in fig. 2 and fig. 16, a cover dielectric layer 29 is formed, and the cover dielectric layer 29 covers the exposed surface of the shielding gate 28.
As an example, but not limited to, a thermal oxidation process may be used to form an oxide layer on the exposed surface of the shield gate 28 as the capping dielectric layer 29. The cover dielectric layer 29 covers the exposed surface of the shield gate 28.
In step S60, please refer to step S60 in fig. 2 and fig. 17, a gate 210 is formed in the trench 21, wherein the gate 210 is located above the shield gate 28, covers the capping dielectric layer 29, and has a distance from the shield gate 28 and the sidewall of the trench 21.
Specifically, the cover dielectric layer 29 is disposed between the gate 210 and the shield gate 28, and the first field oxide layer 22 is disposed between the gate 210 and the sidewall of the trench 21.
As an example, step S60 may include the steps of:
s601: forming a gate material layer (not shown) on an upper surface of the first field oxide layer 22 inside the trench 21 and outside the trench 21; specifically, the gate material layer may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process;
s602: removing the gate material layer on the upper surface of the first field oxide layer 22 outside the trench 21, wherein the gate material layer remaining in the trench 21 is the gate 210; specifically, the gate material layer on the upper surface of the first field oxide layer 22 outside the trench 21 may be removed by, but not limited to, a chemical polishing process or an etching process.
As an example, the gate 210 may include, but is not limited to, a polysilicon gate.
In the method for manufacturing the shielded gate power device, after the second field oxide layer 27 is formed on the upper surface of the isolation dielectric layer 26, the gate hole 271 is formed in the second dielectric layer 27, and then the polysilicon layer is filled in the gate hole 271, the filled polysilicon layer and the polysilicon layer remained after the oxidation treatment jointly form the shielded gate 28, the bottom of the shielded gate 28 does not take the shape of a tip, and the bottom of the shielded gate 28 does not have a strong electric field, thereby further ensuring that the bottom of the trench 11 is not broken down.
As an example, the following steps may be further included after step S60:
forming a body region (not shown) in the semiconductor layer 20, the body region being located at two opposite sides of the trench 21;
forming a source (not shown) in the body region;
forming a gate electrode (not shown), a source electrode (not shown), and a drain electrode (not shown), the gate electrode being electrically connected to the gate electrode 210; the source electrode penetrates through the source electrode and extends into the body region; the drain electrode is electrically connected to the lower surface of the semiconductor layer 10. Specifically, the drain electrode may be located on a lower surface of the semiconductor layer 10.
In another embodiment, with continuing reference to fig. 17 in conjunction with fig. 3-16, the present invention further provides a shielded gate power device, including: the invention provides a shielded gate power device, comprising: a semiconductor layer 20; a trench 21, the trench 21 being located within the semiconductor layer 20; an air cavity 25, the air cavity 25 being located at the bottom of the groove 21; a shield gate 28, the shield gate 28 being located within the trench 21 and over the air cavity 25; the shield grid 28 is spaced from the side wall of the trench 21, and the upper surface of the shield grid 28 is lower than the top surface of the trench 21; a gate 210, the gate 210 being located within the trench 21 and above the shield gate 28 with a spacing from the shield gate 28 and sidewalls of the trench 21; and the covering dielectric layer 29 is positioned between the shielding grid 28 and the grid 210, and covers the exposed surface of the shielding grid 28.
According to the shielded gate power device, the air cavity 25 is formed at the bottom of the groove 21, the air cavity 25 is located at the bottom of the shielded gate 28, and the air has a good isolation and voltage-resisting effect, so that the breakdown voltage at the bottom of the shielded gate 28 can be remarkably improved, and the device is not easy to break down at the bottom of the groove 21. The air cavity 25 is arranged at the bottom of the groove 21, so that the source-drain parasitic capacitance Cds can be greatly reduced, the switching speed of the device is increased, and the switching loss is reduced.
As an example, the semiconductor layer 20 may be at least one doped layer, such as at least one epitaxially doped layer; at this time, the semiconductor layer 20 may be formed on a substrate (not shown). Of course, in other examples, the semiconductor layer 20 may also be a doped substrate. The doping concentration range in the semiconductor layer 20 may be set according to actual conditions, and is not limited herein.
By way of example, the material of the semiconductor layer 20 may include, but is not limited to, silicon germanium, silicon carbide, gallium nitride, or other suitable semiconductor materials, and the like.
As an example, the depth of the trench 21 is smaller than the thickness of the semiconductor layer 20.
As an example, the longitudinal sectional shape of the groove 21 may be, but is not limited to, a U shape as shown in fig. 17, or the like.
As an example, the number of the grooves 21 formed in step S20 may be set according to actual needs, only two grooves 21 are illustrated in fig. 17, and in other examples, the number of the grooves 21 is not limited to the number illustrated in fig. 17, and may be one, three, four, five, six or more, and so on.
By way of example, the shield gate 28 may include, but is not limited to, a polysilicon shield gate; the gate 210 may include, but is not limited to, a polysilicon gate.
As an example, the shielded gate power device may further include: a first field oxide layer 22, wherein the first field oxide layer 22 is at least positioned on the side wall and the bottom of the trench 21; the gate 210 is located on the surface of the first field oxide layer 22 away from the semiconductor layer 20; an isolation dielectric layer 26, wherein the isolation dielectric layer 26 is located between the air cavity 25 and the gate 210 and is located on the surface of the first field oxide layer 22 away from the semiconductor layer 20; a second field oxide 27, wherein the second field oxide 27 is located between the isolation dielectric layer 26 and the gate 210 and is located on the surface of the first field oxide 22 away from the semiconductor layer 20; the shielding gate 28 penetrates through the second field oxide layer 27 from top to bottom, and extends into the isolation dielectric layer 26.
As an example, the first field oxide layer 27 also covers the upper surface of the semiconductor layer 20.
As an example, the first field oxide layer 27 may include, but is not limited to, a silicon oxide layer.
By way of example, the isolation dielectric layer 26 may include, but is not limited to, an oxide layer, a nitride layer, or an oxynitride layer.
As an example, the second field oxide layer 27 may include, but is not limited to, a silicon oxide layer.
As an example, the upper surface of the shielding gate 28 is not lower than the upper surface of the second field oxide layer 27; in this embodiment, the upper surface of the shielding gate 28 may be higher than the upper surface of the second field oxide layer 27, as shown in fig. 17.
As an example, the shielded gate power device may further include: a body region (not shown) on opposite sides of the trench 21; a source (not shown) located within the body region; a gate electrode (not shown) electrically connected to the gate 210; a drain electrode (not shown) extending through the source and into the body region; a drain electrode (not shown) electrically connected to a lower surface of the semiconductor layer 10. Specifically, the drain electrode may be located on a lower surface of the semiconductor layer 10.
It should be understood that, although the steps in the flowcharts related to the embodiments are shown in sequence as indicated by the arrows, the steps are not necessarily executed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the above embodiments may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a part of the steps or stages in other steps.
All possible combinations of the technical features of the above embodiments may not be described for the sake of brevity, but should be considered as being within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A shielded gate power device, comprising:
a semiconductor layer;
a trench located within the semiconductor layer;
the air cavity is positioned at the bottom of the groove;
a shield grid positioned in the trench and on the air cavity; the shielding grid electrode has a distance with the side wall of the groove, and the upper surface of the shielding grid electrode is lower than the top surface of the groove;
the grid electrode is positioned in the groove, positioned above the shielding grid electrode and spaced from the shielding grid electrode and the side wall of the groove;
and the covering dielectric layer is positioned between the shielding grid and the grid and covers the exposed surface of the shielding grid.
2. The shielded gate power device of claim 1, further comprising:
the first field oxide layer is at least positioned on the side wall and the bottom of the groove; the grid electrode is positioned on the surface of the first field oxide layer far away from the semiconductor layer;
the isolation medium layer is positioned between the air cavity and the grid electrode and positioned on the surface of the first field oxide layer far away from the semiconductor layer;
the second field oxide layer is positioned between the isolation medium layer and the grid electrode and positioned on the surface of the first field oxide layer far away from the semiconductor layer; the shielding grid electrode penetrates through the second field oxide layer from top to bottom and extends into the isolation medium layer.
3. A preparation method of a shielding grid power device is characterized by comprising the following steps:
providing a semiconductor layer;
forming a groove in the semiconductor layer;
forming an air cavity at the bottom of the groove;
forming a shielding grid in the groove, wherein the shielding grid is positioned on the air cavity; the shielding grid electrode has a distance with the side wall of the groove, and the upper surface of the shielding grid electrode is lower than the top surface of the groove;
forming a covering dielectric layer, wherein the covering dielectric layer covers the exposed surface of the shielding grid;
and forming a grid electrode in the groove, wherein the grid electrode is positioned above the shielding grid electrode, covers the covering dielectric layer and has intervals with the shielding grid electrode and the side wall of the groove.
4. The method of claim 3, further comprising, before forming the air cavity at the bottom of the trench:
and forming a first field oxide layer on the upper surface of the semiconductor layer, the side wall and the bottom of the groove.
5. The method of claim 4, wherein forming an air cavity at the bottom of the trench comprises:
forming a sacrificial layer at the bottom of the groove, wherein the sacrificial layer is positioned on the surface of the first field oxide layer away from the semiconductor layer;
forming a polycrystalline silicon layer on the upper surface of the sacrificial layer, wherein the upper surface of the polycrystalline silicon layer is lower than the upper surface of the groove;
forming a through hole in the polycrystalline silicon layer, wherein the through hole exposes the sacrificial layer;
removing the sacrificial layer based on the via to form the air cavity.
6. The method for manufacturing the shielded gate power device according to claim 5, wherein the number of the through holes is multiple, and the through holes are arranged at intervals.
7. The method according to claim 5, wherein the polysilicon layer comprises a central region and an outer region located outside the central region, and the through hole is located in the outer region; after forming the air cavity at the bottom of the trench and before forming the shield gate in the trench, the method further comprises:
and oxidizing the polycrystalline silicon layer to oxidize at least the polycrystalline silicon layer positioned in the outer side area into a silicon oxide layer and fill the through hole, wherein the silicon oxide layer obtained in the oxidizing treatment process is used as an isolation dielectric layer.
8. The method as claimed in claim 7, wherein during the oxidation process, a portion of the polysilicon layer in the central region is retained, and a silicon oxide layer is formed on both the upper surface and the lower surface of the retained polysilicon layer.
9. The method of claim 7, further comprising, before forming the shield gate in the trench: and forming a second field oxide layer on the upper surface of the isolation dielectric layer, wherein the upper surface of the second field oxide layer is lower than the upper surface of the groove.
10. The method of claim 9, wherein forming a shield gate in the trench comprises:
forming a grid hole in the second field oxide layer, wherein the grid hole exposes the polysilicon layer remained after the oxidation treatment;
and filling a polycrystalline silicon layer in the gate hole, wherein the filled polycrystalline silicon layer and the polycrystalline silicon layer remained after the oxidation treatment jointly form the shielding gate.
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